I am not sure which systems you may have used prior to Protel but of
the systems that I have used the reactions that you report below are the

        Putting a net label with the same name on two wires, connects the
wires exactly the same as if you drew a wire between them. Same with most
every CAD system going. Placing the net label on two unconnected wires tells
the netlist facility that you wanted those two wires connected together. How
is it to know otherwise or better, ESP? Does it ask you if you actually
wanted each and every wire between two connection points or not because one
of the wires may be misplaced for the circuit to function correctly?

        Putting your net label on the GND connection changed the net name
for the pin to the net named in the label. I would be pretty sure that all
of your GND nets were renamed by placing the net label on the GND net. It
also sounds as if you only checked the one pin! I am not sure but I would
bet that a net label has a higher priority over a power symbol net
assignment. If the net label had not changed the net name to the net label
name, how would you ever put a required netlabel on a net if the net label
name kept changing to some other already pre-assigned net name?

        Putting multiple net labels on a net, will result in one of the nets
being the one actually assigned in the netlist. Which one is the one used in
the netlist is based somehow on the physical locations of the net labels
within the schematic sheets, i.e. first one the netlister comes across or
possibly the last one it comes across as it is trying to compile the

        Multiple parts with same designators, this is why there is a special
check within the ERC simply to check for this occurrence. ERC, ERC, ERC,
learn it, use it , live it. It will save your butt almost every time you use
it. Remember that when you first brought in all those parts they had the
same R? reference designators. As well, using the annotation tools within
Protel is probably the easiest manner to update designators without
duplication errors. The only manner by which you should have duplicated
designators is through human intervention causing human errors.

        How do you stop designers from make errors like connecting two
unconnected nets with a misplaced netlabel? Extensive ERC, reviews and
procedural checks in your process. This is equivalent to how do you stop
somebody from putting the wrong component into the PCB, checks and measures!
There is no fool-proof method, fools are too numerous and they are
everywhere, give them enough time they will find a way to beat your best
planned processes and procedures. I have even been known to have beat my own
best processes.

        Mira, this all 'sounds' like you are very new to EDA CAD tools, but
yet you seem to be trying to define the future path and processes for
others. Shouldn't this task of defining processes, procedures and how to
utilize the tools, be performed by the most experienced of those who will
actually will do the work? I believe that if I was CAD designer working in
your company right now, I would be dusting and polishing my resume.

Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010

Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21.

> -----Original Message-----
> From: Mira [mailto:[EMAIL PROTECTED]]
> Sent: Monday, April 29, 2002 10:50 AM
> To: Protel EDA Forum
> Subject: [PEDA] duplicated net labels and refdes
> Thanks for the remark, Peter.
> I used "wires" and placed "net labels". It's amazing
> that I'm allowed to place parts with one and the same
> ref. designators.
> OK. I placed a net label on the wire that had GND
> power port connected expecting the name of the label
> to change to GND but it didn't.
> The ERC caught both the duplicated net labels and the
> duplicated parts. But when I updated the PCB the
> duplicated net labels were not reported as a problem.
> On the PCB I got this pin (with duplicated net)
> connected to the name of the label (not to GND).
> When I move the net label aside, the pin is connected
> to GND.
> So far so good. Lets think this is a feature. 
> I decided to check what will happen if I place a net
> label on top of two wires, which are crossing each
> other but not connected. They didn't have any other
> labels placed. ERC didn't catch it and the update PCB
> didn't complain either. It just shorted those two
> wires while on the schematic they are visibly not
> connected. 
> Is this another feature? How may I prevent designers
> for shorting nets this way?
> Is there any way to prevent Protel from placing
> duplicated ref. designators?
> Thanks,
> Mira

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
* Contact the list manager:
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to