I agree.  I wonder why Protel let the PLD tools wither and die?  I seem to
remember about 4 years ago that they bought some HDL tool from some other
company and repackaged it as PeakFPGA or PeakVHDL, or Peaksomething.  They
managed to waste that one off.

Personally, I think all those efforts were wasted.  I would much rather see
Protel supported by the chip vendors' design suites.  The main reason I have
used Lattice and Xilinx parts and nobody else's is because they have the
best free PLD/FPGA tools out there (sorry, Altera folks).  But the schematic
editor for both is awful.  Protel should work out a deal with them to supply
that proposed "free" version of the schematic program I mentioned yesterday,
with libs for the PLD and FPGA.  That would be another great way to seed the
market with Protel wares.  Yoo hoo, Altium, are you listening?...

Best regards,
Ivan Baggett
Bagotronix Inc.
website:  www.bagotronix.com


----- Original Message -----
From: "mike ingle" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, June 11, 2002 7:31 PM
Subject: Re: [PEDA] Protel PLD/CUPL Question


> I would consider the PLD section of PROTEL a dead design tool.
> I would either use the free wincupl or go to a commercial compiler from
one
> of the big boys.
>
> Mike
> Using altera parts and Max plus 2
>
>



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