> The synchronizer is fine on small boards.  We have one backplane,  a
> designer recently  took  4 hours to load a netlist.  Using the
synchronizer
> would have taken a week.

Yeow!  I wonder if the netlist load and sync algorithms are one of those n^2
problems.  You know, the ones where you double the complexity, the time to
solve goes up by 4.  I had some fairly large designs before that loaded the
netlist in a few seconds (on a dual PIII 1GHz).  If your design was more
complex by a linear factor, then it would have been 3600x as complex as
mine.  Somehow I doubt you had 108,000 chips on one PCB ;-)  So maybe you
had 60x as many chips as my board (still 1800 chips!).

I'd hate to do a clearance check on your board ;-)

Best regards,
Ivan Baggett
Bagotronix Inc.
website:  www.bagotronix.com


----- Original Message -----
From: "Mike Reagan" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, February 14, 2003 9:18 AM
Subject: Re: [PEDA] A Question About Netlist Compare and Partially Matched
Nets. Protel 99SE SP6.


> Ian,
> Time works against me.    Some boards of which I have Protel schematics,
I
> have found the synchronizer to take hours.  As much as 4 hours to use the
> synchronizer or to reload a netlist on top of one.    If you use my crazy
> method, (clear netlist)   not only is it fool proof,  but  it the entire
> process can be over and done with in 5- 15 minutes on large designs.
> The synchronizer is fine on small boards.  We have one backplane,  a
> designer recently  took  4 hours to load a netlist.  Using the
synchronizer
> would have taken a week.
>
>
> Mike Reagan
> EDSI
> Frederick MD
>
>
>
>
>
> ----- Original Message -----
> From: Ian Wilson <[EMAIL PROTECTED]>
> To: Protel EDA Forum <[EMAIL PROTECTED]>
> Sent: Friday, February 14, 2003 12:14 AM
> Subject: Re: [PEDA] A Question About Netlist Compare and Partially Matched
> Nets. Protel 99SE SP6.
>
>
> > On 07:38 PM 13/02/2003 -0500, Mike Reagan said:
> > >John
> > >You are welcomed...but I should practice what I preach.   I have been
> using
> > >this method with 99SE SP6 and have had flawless designs.   Ok until
last
> > >week ,  we got a board back with power and gnd were not connected to
the
> > >input connector.    The original  ECO was a minor change, I imported a
> > >netlist,  and since I knew what the ECO was,  made the quick changes.
> Ran
> > >DRCs and sent gerbers.     The problem was.....the footprint for the
> power
> > >connector had duplicate pin numbers.  A second import of  a netlist in
> > >Protel causes all of the pins to disconnect,  at third import will
cause
> > >only one of the pins to connect.  Every subsequent import will cause
> > >differnet results . I already was aware of it but didnt see the
> connector.
> > >This will not show up as an error when you import the netlist either.
> > >Had I stuck with my fool proof method and not taken a shortcut
 because
> I
> > >made an assumption)   I wouldnt have had mud in my face.   Clear the
> > >netlist, import the netlist , connect copper, run drcs .....100 percent
> of
> > >the time and you will never have a problem.     So said the fool of the
> week
> > >only because I made an assumption.
> >
> >
> > A solution to this issue, for some at least, is to use Update PCB (the
> > synchronizer) rather than netlist load.
> >
> > I know, Mike, that you get netlists often rather than P99SE sch so this
is
> > not always a solution, but the synch deals with the duplicate pins
> > correctly, I think.  I don't use duplicate pins (as it I don't like the
> > risks), but I think others have stated that the sycnh is OK but netlist
> > load has the oscillatory connect/disconnect behavior.
> >
> > Ian
> >
> >
> >
>
>
>



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