> Jan 12, 2020, 14:43 by mikeb...@gmail.com:
>
> Solution for your coreboot + discrete GPU problems like
>
> amdgpu kernel bo map failed [...] error -22
> amdgpu_vram_scratch_init failed [...] error -22
> fatal error in GPU initialization
>
> It turned out that a fix like
>
>
> Please don't suggest "cross-flashing". That it worked does not mean
> that it is a wise thing to do. Different boards have different
> settings, and some of these are critical. The worst case are GPIOs:
> configurable pins that can be either inputs or outputs. If a GPIO that
> is wired as an
On Mon, Jan 13, 2020 at 4:15 AM Lance Zhao wrote:
>
> Drop Win 7 for your case will be more realistic in the meantime.
>
> Marshall Dawson 于2020年1月13日周一 上午9:09写道：
>>
>> > Please guys repair coreboot to support my laptop motherboard.
>> > https://github.com/coreboot/coreboot/pull/18
>>
>> Ryzen
On Mon, Jan 13, 2020 at 11:10 AM Aaron Garza wrote:
>
> Does Coreboot work on every motherboard or does it have to be certain
> motherboards/PCs?
>
> I have an old Intel Core 2 Quad and an ASUS P5K-E motherboard that I
> would love to set up with a coreboot BIOS replacement. Is it even possible?
t to get RX590 working. So happy it was possible,
thanks to you all ;-)
Best regards,
Mike Banon
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If you know, please tell the AGESA versions of fam15h/fam16h AMD
vendorcode. For fam14h it is v1.103 - so no questions - but for fam15h
and fam16h it says v0.001: #define AGESA_VERSION_STRING {'V', '0',
'.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
Also, I wonder if there's an AGESA
It would be nice if the deleted commits get moved to some archive
outside of Gerrit instead of being simply removed, to ensure that if
anyone else is interested in these commits, they could be restored. A
bit later I discovered that only the "drop ROMCC" ones were removed -
so not much has been
OTBLOCK+status:abandoned
> >
> > De : "Carl-Daniel Hailfinger"
> > A : "Mike Banon" ,"HAOUAS Elyes"
> > ,jonzh...@fb.com,acidbu...@live.be,andycu...@gmail.com,"Martin Roth"
> > ,"Michal Zygowski" ,no-re...
ilar enough
except the vendorcode. I suggest doing " git reset --hard d777c78 " ,
" kdiff3 ./src/mainboard/asrock/imb-a180/
./src/mainboard/biostar/am1ml/ & " , and applying the same logic while
converting a G505S code. I don't have the time to do this c
of AMD boards,
so it's really sad to see it gone. Gogol burning Dead Souls volume 2
comes to mind...
Please, restore the changes deleted since Jan 5 2020, and make sure
this anti-feature "delete change" can't be used such easily in the
future.
Best regards,
Mike Banon
Same problem with many other "Drop boards with ROMCC_BOOTBLOCK"
changes. So much work has been lost...
On Wed, Jan 8, 2020 at 10:25 AM Mike Banon wrote:
>
> For some reason I couldn't open change 38107 - it gives me a 404 :
>
> https://review.coreboot.org/c/coreboot/+/3
board, so I
hope you could fix this Gerrit problem.
Best regards,
Mike Banon
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0x12
> and 0x13 devices are available from what i see). You would have to refer
> to a BKDG for your processor and chipset to check whether these problems
> I have listed are not copy-paste problems and EHCI 0x16 is really
> available for use without XHCI (IMO it should be).
>
>
16.0 and 16.2 at devicetree.cb (they
weren't mentioned here), but it doesn't help. What are my next steps?
Best regards,
Mike Banon
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a discrete GPU problem is fixed with this tiny change -
https://review.coreboot.org/c/coreboot/+/38214
On Thu, Dec 26, 2019 at 10:30 AM Mike Banon wrote:
>
> I hope this board is saved with a change
> https://review.coreboot.org/c/coreboot/+/37829 ( asus/am1i-a: Switch
&g
t it working - more info at
> https://review.coreboot.org/c/coreboot/+/30987/ comments.
>
>
>
> On Sat, Oct 19, 2019 at 11:05 PM Mike Banon wrote:
>
>
> Do you still have this problem? Please try obtaining a "cbmem log" and
> I'll try my best to help you
>
This has been superseded by 38202 , and together with 38200 + 38201 +
38203 really helped to get a discrete GPU working on G505S and
A88XM-E. These boards have both AMD integrated and discrete GPU, but
maybe the "CONFIG_MULTIPLE_VGA_ADAPTERS changes" like these will help
your NVidia as well! I
/+/30987/ comments.
On Sat, Oct 19, 2019 at 11:05 PM Mike Banon wrote:
>
> Do you still have this problem? Please try obtaining a "cbmem log" and
> I'll try my best to help you
>
> On Sat, Oct 12, 2019 at 8:40 PM Mike Banon wrote:
> >
> > Maybe this "cbmem
Sequel of a Turtle RAM issue [1] I had on fam16h AM1I-A : a pair of
[2] modules crawls as 1333MHz CL9 on A88XM-E (F2A85-M clone) with
A10-6700. That's despite a really similar pair [3], just 1600MHz CL9
and in a SO-DIMM shape, runs on its' top 1600MHz CL9 speed at Lenovo
G505S with A10-5750M which
Display is working fine on fam16h ASUS AM1I-A with Athlon-5370 APU
installed (pci1002,9830.rom, iGPU HD-8400 / R3-Series)
On Thu, Jan 2, 2020 at 2:32 AM awokd via coreboot wrote:
>
> Could someone with a Fam16 using integrated graphics test
> https://review.coreboot.org/c/coreboot/+/38056 and
t hash.
>
> Sincerely,
> -Matt
>
> On Thu, Dec 12, 2019 at 5:23 PM Kyösti Mälkki wrote:
>>
>> On Thu, Dec 12, 2019 at 11:58 AM Mike Banon wrote:
>> >
>> > It would be nice if this "drop time" could be extended until at least
>> > mid Jan
It would be nice if this "drop time" could be extended until at least
mid January (i.e 19th Jan), so that those of us who have New Year
holidays will be able to spend them working on coreboot. I also want
to save AM1I-A but don't have much time in December.
On Thu, Dec 12, 2019 at 12:52 AM Matt B
tter to copy it from HTTP tab to avoid
accidental mistakes). Then copy the files you would like to commit to
this repository, commit and push, and it should only ask your
password, without a username.
On Sun, Dec 8, 2019 at 11:37 AM Mike Banon wrote:
>
> My guess is that maybe you've configu
By the way, P2B build works fine for P2B-B board. In addition, if
you'd like to get some free space at your BIOS, check which microcode
blobs it is trying to include and remove those which aren't for your
CPU.
On Wed, Dec 4, 2019 at 9:50 PM Nico Huber wrote:
>
> Hi Keith,
>
> On 04.12.19 01:19,
Yes, feel free to send more advanced questions to this list, would be
an interesting discussion!
On Thu, Dec 5, 2019 at 11:26 PM Seth Rosenblatt wrote:
>
> Hello Coreboot community,
>
> I'm writing a story on new research by Ilja van Sprundel and Joseph Tartaro
> demonstrating vulnerabilities
> can you tell me a few good boards with a fresh status?
check it at https://coreboot.org/status/board-status.html
> the single boards and mini PC have good performance compared to desktop
> boards?
Check the boards at "Mini-ITX / Micro-ITX / Nano-ITX" category of a
page above, and their
.
>
> вс, 10 нояб. 2019 г. в 21:07, Mike Banon :
>>
>> No problem (this log is really huge for some reason). At the beginning
>> of it - the most interesting part - I've found that "MemBusFreqLimit :
>> 800" and "MemoryClockSelect : 667". Perhaps I'd
in first 10Mb and near a dedicated video
> memory). BTW i'm choose to use last free memtest86 (without plus), it work's.
>
> вс, 10 нояб. 2019 г. в 21:07, Mike Banon :
>>
>> No problem (this log is really huge for some reason). At the beginning
>> of it - th
You could add a custom message to a SeaBIOS boot menu screen, by a
manual modding of its' sources.
On Thu, Nov 14, 2019 at 6:01 AM Tom Hiller wrote:
>
> Is there a way to store contact information or in case of emergency
> information in a payload in the event my laptop if lost or stolen?
>
rm) or 800 (for 1600) at the vendorcode. Another interesting
thing is that memtest86+ is failing but all the OS are working
correctly.
On Sun, Nov 10, 2019 at 7:16 PM Kyösti Mälkki wrote:
>
> On Sun, Nov 10, 2019 at 3:52 PM Mike Banon wrote:
> >
> > Sorry it took me so long: u
Thank you, I've sent the reports for Lenovo G505S (AMD Fam15h) and
ASUS AM1I-A (AMD Fam16h). Hope this helps, especially AM1I-A since
its' previous report was from early 2018.
Best regards,
Mike Banon
On Mon, Nov 4, 2019 at 5:31 PM Patrick Georgi via coreboot
wrote:
>
> Hi everybody,
&
If your board is supported by flashrom internal flashing mode, you can
"recover flash" it internally if could boot to Linux. Any Linux
LiveUSB with iomem=relaxed added to Linux kernel parameters at GRUB
("e" button to temporarily edit this entry) would be sufficient: git
clone a flashrom
to make S3 resume working or disable for
increased security.
Enables CBMEM_STAGE_CACHE and disables
SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT.
(this is just a draft)
On Sun, Nov 3, 2019 at 5:23 PM Kyösti Mälkki wrote:
>
> On Sun, Nov 3, 2019 at 3:48 PM Mike Banon wrote:
> >
kki wrote:
>
> On Sun, Nov 3, 2019 at 3:48 PM Mike Banon wrote:
> >
> > Good day! Starting with commit
> > 0a4457ff44b10f22b711f64e8c757fbedf32 which introduced a
> > disabled-by-default CONFIG_CBMEM_STAGE_CACHE option -
> &g
without
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT
Best regards,
Mike Banon
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> which ones have best performance? AMD or INTEL?
If this ME/PSP thing matters to you, AMD no-PSP usually have a better
performance than Intel no-ME, but Intel with-ME could have a better
performance than AMD no-PSP. It all depends on which boards you are
comparing between each other. Try to find
compiled coreboot.rom with this command:
./build/cbfstool ./build/coreboot.rom add -f ./floppy/memtestp.bin -n
floppyimg/memtestp.lzma -t raw -c lzma
If done everything correctly, it will be available at SeaBIOS boot menu as
Ramdisk [memtestp]
Best regards,
Mike Banon
On Sun, Jul 28, 2019 at
Why are you considering only Intel boards? coreboot supports plenty of
AMD boards which don't contain ME/PSP and don't suffer from Meltdown +
some other Intel-only vulnerabilities, for which the
performance-crippling patches are required. IMHO, AMD seems to be a
wiser choice for a coreboot board,
Thank you very much for your reply. Still curious about this
"Pre-CBMEM log truncated" issue - how would you have solved it?
On Sun, Oct 27, 2019 at 10:08 AM Kyösti Mälkki wrote:
>
> On Sun, Oct 27, 2019 at 8:53 AM Mike Banon wrote:
> >
> > Good day, I'm researching
port: %d\n === dp=%d.
n_ports:%d\n === np=%d.
Best regards,
Mike Banon
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> There are some messages from a few years back from Reto Rayen but I’m not
> able to reproduce his work.
It would be easier to help you if you can tell, what have you already
tried and what exactly did not work.
On Sun, Oct 13, 2019 at 10:59 AM Karim El Chenawi wrote:
>
> Hi guys,
>
> I was
Know I'm a bit late, but for me it was much easier to use FT232H-based
USB board as a debug dongle. Initially I also wanted to build that
FX2LP sandwich, but some confusion regarding the revisions (it's a bit
tiresome to ask many sellers for a board revision in advance) and the
need for
r me only Nvidia GPUs work correctly.
>
> But using an older Version from 2018, because S3 works there.
>
>
> Am 10.09.19 um 11:05 schrieb Mike Banon:
> > Indeed, this patch -- https://review.coreboot.org/c/coreboot/+/31448 (
> > src/device/pci: Add support for discrete VG
You didn't mention on which board you are trying to boot Windows 10.
I've heard that Windows may get stuck while booting if ACPI
implementation at coreboot for your particular board is imperfect
enough. Maybe Windows became more demanding after this update. It
could help if you'd also test 1709,
That's because a supply of G505S has been distributed by Lenovo
unevenly between the different countries. Also, the majority (if not
all of) the G505S of UK seem to lack the discrete graphics (= internal
LA-A092P motherboard), although it doesn't matter much since the
performance of integrated vs
Do you have an EHCI debug dongle, like USB FT232H? If enabled at
coreboot's config, it could be plugged into a USB port (usually 2.0)
and will be printing a coreboot boot log to another computer.
On Wed, Sep 25, 2019 at 7:19 PM Benjamin Doron
wrote:
>
> Hi again,
> I've been working on this over
It may have tried initializing the graphics by itself, ignoring a
setting of the unknown-to-it BIOS. You may consider running OS X in a
virtual machine under Linux host.
On Wed, Sep 25, 2019 at 9:32 PM wrote:
>
> Hi,
>
> thanks for quick answer.
>
> Sorry, it wasn't far away, but I missed it.
>
to either change "off" to "on" or add some new lines with
"on". Please note that sometimes a coreboot can't boot with some of
these extra devices enabled.
Best regards,
Mike Banon
On Tue, Sep 17, 2019 at 10:04 AM wrote:
>
> Hi,
>
> I have an intel Xeon-D
ks there.
>
>
> Am 10.09.19 um 11:05 schrieb Mike Banon:
> > Indeed, this patch -- https://review.coreboot.org/c/coreboot/+/31448 (
> > src/device/pci: Add support for discrete VGA initialization and OpROM
> > loading ) -- could help, because it will create the ACPI V
Indeed, this patch -- https://review.coreboot.org/c/coreboot/+/31448 (
src/device/pci: Add support for discrete VGA initialization and OpROM
loading ) -- could help, because it will create the ACPI VFCT table
for discrete RX 570 GPU instead of doing this for integrated HD 8670D.
You could install
The proprietary graphics drivers for AMD GPUs found at G505S (
integrated HD-8650G and optional discrete HD-8570M or R5-M230 ) - are
all deprecated, not supported by any modern (newer than Kubuntu
14.04.4) Linux distro. If you are using a modern Linux, you can't use
the proprietary drivers for
that "#define
BLDCFG_MEMORY_CLOCK_SELECT" seemingly doesn't work for some reason.
Do you have any other ideas to fix this "turtle RAM" AMD 16h problem?
Best regards,
Mike Banon
On Fri, Jul 5, 2019 at 8:44 AM Kyösti Mälkki wrote:
>
> On Wed, Jul 3, 2019 at 8:54 PM Mike Ba
ot/+/33920 , but the things like
"#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY" sadly did not
help.
Any ideas how to improve the RAM speeds? How I can force this RAM to run faster?
Best regards,
Mike Banon
[*] Crucial Ballistix Tactical Series DDR3 1866MHz CL9 (PC3-14900
9-9-9-24) UDIMM 2
to manually patch them by
hand.
Best regards,
Mike Banon
On Fri, Jun 21, 2019 at 11:22 AM Sirsquishy wrote:
>
> This has been an issue since before AM2+, but AM2+ is when I first started to
> deal with it. For AMD IOMMU does not fully work behind the DMI. If you break
> out IOMMU from t
f IOMMU to 16h Puma
together with the introduction of AMD PSP - is just a pure
coincidence.
Best regards,
Mike Banon
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seems that IOMMU is impossible at AM1I-A because it is
16h Jaguar. And I tested this on the latest available CPU for AM1
socket, ultra rare Athlon 5370 (slightly faster than Athlon 5350 but
no major differences). Hope this report helps to save some of your
t
At least Windows 10 supports the Legacy BIOS, and most likely 12 will
too. As long as they are making a 32-bit version of Windows they're
still caring about the "legacy" PCs and we shouldn't be worried. Also,
it's hard to imagine a coreboot'er who would be running 12 natively -
not inside some
gt; CONFIG_SLAB_FREELIST_RANDOM=y
> > CONFIG_SLAB_FREELIST_HARDENED=y
> > lg@chi:~$ cat /boot/config-4.19.0-5-amd64 | grep -i slub
> > CONFIG_SLUB_DEBUG=y
> > # CONFIG_SLUB_MEMCG_SYSFS_ON is not set
> > CONFIG_SLUB=y
> > CONFIG_SLUB_CPU_PARTIAL=y
> >
I see that it failed on "deactivate_slab". What if at the Linux kernel
configuration you'd choose SLUB instead of SLAB, for example? And is
this kernel working on the other computers?
On Tue, Jun 11, 2019 at 1:43 AM Kinky Nekoboi wrote:
>
> Just tested a Rom without microcode. Doesnt work
> Am 05.06.2019 07:58 schrieb Martin Kepplinger:
>> I can test later but I think I can see what happens. It fixes the issue,
>> but still prints "ERROR: Keyboard set scancode failed!".
There's also a chance that it'd prematurely "return;" slightly later -
in this case my tiny patch wouldn't fix
t; basically
> > to roll back the commits for the kcma-d8 that has been done since the
> > libreboot fork.
> >
> > Another approach would be to figure out why only very few RAM modules are
> > supported. I can offer test support, but the analysis exceeds my knowledge
> > and
&
Martin, could you please check what happens if you apply this patch
but then remove a return that follows ""ERROR: Keyboard set scancode
failed!" ? Perhaps we'll have to do the same for all these returns :
"Still print this message but don't abort prematurely"
Signed-off
zation problem by not aborting prematurely
if its' reset has failed.
Signed-off-by: Mike Banon
---
diff --git a/payloads/libpayload/drivers/i8042/keyboard.c
b/payloads/libpayload/drivers/i8042/keyboard.c
index 12255fb..b34dbca 100644
--- a/payloads/libpayload/drivers/i8042/keyboard.c
+++ b/pay
us
> for them, but figured knowing a good range of platforms/boards were known
> working just prior to release was useful (and the purpose of the list)
>
> On Mon, Jun 3, 2019 at 9:14 AM Mike Banon wrote:
>>
>> Just noticed that someone included i.e. some Purism Librem dev
Zinoviev via coreboot
wrote:
>
> Your plan worked, I've just uploaded board status for 4 more boards.
>
> On 6/2/19 9:26 PM, Mike Banon wrote:
> > I've just added a "Recently tested mainboards:" section to the end of
> > https://piratenpad.de/p/coreboot4.
T530 baseboard
* Lenovo Thinkpad X131e Chromebook (Google Stout)
* Lenovo ThinkPad X200
* Lenovo Thinkpad X220
* Lenovo Thinkpad X230
* Gigabyte GA-B75M-D3H
* Asrock E350M1
* PC Engines APU1
* PC Engines APU2
On Mon, Jun 3, 2019 at 4:55 PM Mike Banon wrote:
>
> If the upstream edk2 is s
ch is working fine though.
>>
>> On Mon, Jun 3, 2019, 3:28 AM Matt DeVillier wrote:
>>>
>>> On Sun, Jun 2, 2019 at 1:27 PM Mike Banon wrote:
>>>>
>>>>
>>>> Also, regarding the significant changes: " ### Tianocore
I've just added a "Recently tested mainboards:" section to the end of
https://piratenpad.de/p/coreboot4.10-release-checklist . I think its'
existence could encourage the people to submit a board status report
for their board, to increase its' visibility and attract more
potential users/developers
> Why libreboot works and coreboot doesn't?
Libreboot is some older version of coreboot where all the blobs have
been removed. If something works at libreboot but doesn't work at
coreboot, most likely that means there was a breaking commit at
coreboot which came later than a libreboot release
could test it or take a look on its' code and share some
feedback, e.g. regarding its' POSIX compatibility (I'm trying to make
this script as portable as possible)
Best regards,
Mike Banon
On Sun, May 26, 2019 at 12:00 PM Kinky Nekoboi
wrote:
>
> Hello Mike,
>
> thank you for
t;.
[1] -
https://review.coreboot.org/c/coreboot/+/29272/2#message-771016d7aa4633189e22b3354dbba0494d8c8d0e
[2] -
https://review.coreboot.org/c/coreboot/+/28273/6#message-cbbdcce72362a39ad3edb056f25cd54037dce59a
Best regards,
Mike Banon
On Fri, May 24, 2019 at 11:04 PM Kinky Nekoboi
wrote:
&g
> did the ASUS KFSN4-DRE ever receive family 15h support, in addition to 10h?
> or was that only the KGPE boards?
When I go to a "./src/mainboard/asus/kgpe-d16" or
"./src/mainboard/asus/kcma-d8" and do this search:
find . -type f -print0 | xargs -0 grep -n "15h"
- there are multiple matches at
ying memory and I/O
addresses. While this option prevents Option ROMs from doing dirty
tricks with the CPU (such as installing SMM modules or hypervisors),
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.
Best regards,
Mike Banon
t; controller were mentioned previously here:
>> https://review.coreboot.org/c/coreboot/+/2610
>>
>> There is also an abandoned port that was based on this board:
>> https://review.coreboot.org/c/coreboot/+/5551
>>
>> And it was mentioned here:
>> https://r
for the AtomBIOS ROMs - should be successful
there as well, although perhaps would take another year or so :P
Best regards,
Mike Banon
On Mon, May 20, 2019 at 6:43 PM Mike Banon wrote:
>
> > there is no way for me to compare AMD patches directly since it appears AMD
> > doesn
urce and you could
look through it to verify that there are no harmful options enabled,
and I'm using such a config by myself without any problems.
Best regards,
Mike Banon
On Mon, May 20, 2019 at 4:32 AM Chris Laprise wrote:
>
> On 5/16/19 2:35 PM, Mike Banon wrote:
> > Hi Chris, if
er M5A88-V patches at review.coreboot.org . Hope you
could share your findings here then, to save the time for others.
Best regards,
Mike Banon
On Sat, May 18, 2019 at 4:59 PM Robin C wrote:
>
> Hi all,
>
> On coreboot status page, I can see that M5A88-V status is unknown (EVO?
> M5A
ove another AtomBIOS, which is already there, manually
(with cbfstool). Also, you could use the cbfstool to add a
floppy-based operating system - such as KolibriOS - or simply to print
a memory map of your coreboot.rom to see how much of a free space
there's left.
Best regards,
Mike Banon
___
Hi Chris, if you'd like to verify the microcodes inside my AMD ucode
patch: convert the hexadecimal arrays at their .c files back to
binary, extract the microcodes from proprietary UEFI updates for those
few AMD boards that are still getting them ( or get them already
extracted by platomav from
02,6665.rom or pci1002,6663.rom).
> is running the cbfstool line mandatory after building the coreboot even if I
> built for each laptop separately?
> (if not, then maybe i should do a rebuild)
>
>
> De : Mike Banon
> À : br...@netc.fr
> Sujet : Re: Lenovo G505s, results irqpoll
>
Here's a final part of coreboot build log for crossgcc-x64 build
attempt. This does not happen while building with crossgcc-i386, so
seems to be x64-only problem.
CC romstage/lib/stack.o
CC romstage/lib/timestamp.o
CC romstage/lib/version.o
CC
Hi there Rogier,
Why no tint? ;-) tint patch adds a checksum verification for the
archive that will be downloaded later from Free Software Foundation
during the compilation, so no security risk there. Perhaps the only
downside of this tint tetris is that currently it's not compressed
while being
Matt, what a great research! Thank you very much for your findings! No
need to replace your screen (unless you'd like to upgrade it for other
reasons). Soon I'm going to get my own eDP_EDID.bin for comparison.
Also, I could run your version of iGPU blob out of curiosity, while
you could try to run
uot; quests when you have some free time ;-)
Best regards,
Mike Banon
P.S. It could be that a few diffs, e.g. a couple of tiny diffs at the
beginning, may have gone unnoticed while using AtomDis :P
[*]
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/GZNWISLFHUTYN6C7RTWSQU
y to
figure out what are these differences and report back. Hopefully these
differences aren't significant and this iGPU ROM "from G505S with R5
M230" really could be used by everyone without any downsides (also
because I don't want to overcomplicate my patches with multiple ROM
versions for the same iGPU)
needed.
> 3) The moderboard datasheet has a section called:
> "Force BIOS recovery setting"
Of course this method relies on the functionality of proprietary UEFI,
like Matt said.
Best regards,
Mike Banon
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is running its' own blob? )
Best regards,
Mike Banon
On Mon, Apr 22, 2019 at 8:42 AM Kinky Nekoboi
wrote:
> Here is the filelink:
>
> https://nekoboi.moe/nextcloud/index.php/s/DfYGsdNzHHxGKHA
>
> the .config file should be included in the rom.
> Am 21.04.19 um 20:13 schrieb
>
> IMC was dropped out of the standart config and also out of the nconfig
> menu as i experienced. You can see this in the absensce of fan control (
> what is not problem if you have a FAN that is not extrem loud at 12V)
> Am 21.04.19 um 09:29 schrieb Mike Banon:
>
> So IOMMU is w
oi
wrote:
>
>
>
> Weitergeleitete Nachricht
> Betreff: Re: [coreboot] Re: Fwd: Re: Fwd: F2A85M IOMMU still not working
> for RIchland CPUS
> Datum: Thu, 18 Apr 2019 16:24:42 +0200
> Von: Kinky Nekoboi
> An: Mike Banon ,
> coreboot@coreboot.org
>
&g
Fwd: F2A85M IOMMU still not working for
> RIchland CPUS
> Datum: Thu, 18 Apr 2019 11:38:16 +0200
> Von: Kinky Nekoboi
> An: Mike Banon
>
> CPU : A8-6600K
>
> [1.271514] microcode: CPU0: patch_level=0x0600110f
> [1.271521] microcode: CPU1: patch_level=0x060
> also it seems that IOMMU is working now...
Congratulations with these amazing news! Please tell, what version of
coreboot you've currently installed? Also, have you used this
microcode updating patch from DangerousPrototypes page before building
your current coreboot build?
> maybe cause i
didn't ask you to confirm through Linux the
microcode version that you see.
(btw, for some reason your message is not visible at the mailing list
and reached only some of the recepients, luckily my friend resent it
to me)
Best regards,
Mike Banon
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d didn't have time to even test if my new (actually used) board is
working, so you'll have to rely on your own for a while.
Best regards,
Mike Banon
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Run this coreboot.rom by executing this QEMU command: (some floppies are 64-bit)
qemu-system-x86_64 -L . -m 768 -localtime -vga vmware \
-net nic,model=rtl8139 -net user -soundhw ac97 -bios ./coreboot.rom \
-boot menu=on -serial stdio
Best regards,
Mike Banon
On Fri, Apr 12, 2019 at 6:45 AM
""
and so on. Maybe a segmentation fault somewhere?
P.S. I miss the old Pipermail: with its' convenient old school web UI,
short clear links and working attachments... :P
Best regards,
Mike Banon
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tps://pastebin.com/raw/hv9sSuMU
I will also try searching the mailing list archives for these patches.
Remember seeing at least one useful patch from someone else...
Best regards,
Mike Banon
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Usually the size of CBFS filesystem should be equal to the size of
your chip. In your case - ~15MB rounded up to 16MB - it should be
0x100 (16*1024*1024 = 16777216 in dec = 0x100) . So
CONFIG_CBFS_SIZE=0x100 . By the way I noticed a strange thing:
If you don't have any .config and try
to
enlarge a "console" window, so that when I type "ls" command I will be
able to see the whole list of commands and not just the second half of
them ( I had to look at mcopy build log to find out the names for the
rest of apps to run them ).
Best regards,
Mike Banon
On Mon, Mar
SeaBIOS - perhaps the most popular coreboot payload - supports booting
the virtual floppies stored at CBFS (coreboot filesystem). You could
add any floppy by
./build/cbfstool ./build/coreboot.rom add -f ./floppy.img -n
floppyimg/myfloppy.lzma -t raw -c lzma
command - and then you will see it as
Matt B :
>
> Is there any conceivable reason that the dGPU present would have bearing on
> the iGPU voltages?
>
> Is it possible that this is a mistake, and that the voltage was intended for
> the iGPU by the original developer?
> Is it possible that the two reflect different revisions, that one
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