};
} // namespace o3
--
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ateCheck', 'SoftIntGateCheck', 'SSCheck', 'IretCheck',
+ 'IntCSCheck', 'TRCheck', 'TSSCheck', 'InGDTCheck', 'LDTCheck'):
symbols[check] = f'Seg{check}'
for reg in ('TR', &#
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
e gate type.
+srli t9, t1, 40, dataSize=8
+# Extract the IF bit from the flags.
+srli t10, t6, 9, dataSize=8
+# Xor them, so that *that* xored with flags will leave the gate LSB in
IF.
+xor t9, t10, t9, dataSize=8
+# Make sure no other bits are set.
+an
rom
-{
-# This vectors the CPU into an interrupt handler in legacy mode.
-extern legacyModeInterrupt:
- panic "Legacy mode interrupts not implemented (in microcode)"
-eret
-};
-
-def rom
-{
extern initIntHalt:
rflags t1
limm t2, "~IFBit"
--
To vie
t = std::make_shared(selector);
+}
break;
case SegSoftIntGateCheck:
// Check permissions.
--
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;legacy_mode_int_get_gate"
+
+# Make sure the descriptor is a legal gate.
+chks t0, t0, t1, IntGateCheck, dataSize=8
+legacy_int with_ec=True
};
undef macro legacy_int;
--
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
icroFlags.remove('IsLastMicroop')
+if not 'IsDelayedCommit' in microFlags:
+ microFlags.append('IsDelayedCommit')
+
+return f'''new {self.className}(machInst, macrocodeBlock,
+{self.microFlagsText(microFlags)}, {self.cond})'''
ase t10, hs, dataSize=8
-wrbase ss, t10, dataSize=8
+m_copy_seg_info dest="ss", source="hs", temp_reg="t10"
{start_label}_updateESP:
mov rsp, rsp, t6, dataSize=4
--
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a_size=4
-
-legacy_mode_int_dsz_is_4:
+legacy_mode_int_push_frame_dsz_is_4:
st t6, hs, [1, t0, t5], -4, dataSize=4, addressSize=ssz
st t3, hs, [1, t0, t5], -8, dataSize=4, addressSize=ssz
--
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ss, t10, dataSize=8
+
+{start_label}_updateESP:
+mov rsp, rsp, t6, dataSize=4
wrip t0, t9, dataSize=8
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"[0a 0807 0605 0403 0201]");
+EXPECT_EQ(printByteBuf(buf.data(), 9, ByteOrder::big, 3),
+"[0a0807 060504 030201]");
+EXPECT_EQ(printByteBuf(buf.data(), 9, ByteOrder::big, 4),
+"[0a 08070605 04030201]");
+EXPECT_EQ(printByteBuf
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,
+PortID idx=InvalidPortID) override;
+
+void postInterrupt(bool is_primary) override;
+ void clearInterrupt(bool is_primary) override;
+};
+
+} // namespace gem5
+
+#endif // __DEV_X86_IDE_CTRL_HH_
--
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DPRINTF(TLB, "In protected mode.\n");
@@ -361,11 +365,11 @@
}
Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
-bool sizeOverride = (flags & (AddrSizeFlagB
.\n", getSize());
}
void
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0504 030201]");
+EXPECT_EQ(printByteBuf(buf.data(), 9, ByteOrder::big, 4),
+"[0a 08070605 04030201]");
+EXPECT_EQ(printByteBuf(buf.data(), 9, ByteOrder::big, 5),
+"[0a080706 0504030201]");
+ EXPECT_EQ(printByteBuf(buf.d
"CCFLAGS": [ "-Wno-array-bounds",
"-Wno-stringop-overflow" ]
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em5
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
lt;%s>();\n' % (
self.base_name, rindex,
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Ge
const auto ®_class = reg_file.regClass;
+
+ DPRINTFV(reg_class.debug(), "Setting %s register %d to %s.\n",
+reg.className(), idx, reg_class.valString(val));
+reg_file.set(idx, val);
}
// hardware transactional memory
--
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egVal)) :
-RegClass(num_regs, new_zero, reg_bytes)
+RegClass(num_regs, debug_flag, new_zero, reg_bytes)
{
_ops = &new_ops;
}
@@ -107,6 +110,7 @@
RegIndex zeroReg() const { return _zeroReg; }
size_t regBytes() const { return _regBytes; }
size_t r
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r.lineno}: '
+ f'{message}')
print()
##
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o"
+mnemonic = "ldio"
+
+microops["ldio"] = LdioOp
+
+class StioOp(LdStIoOp):
+className = "Stio"
+mnemonic = "stio"
+
+microops["stio"] = StioOp
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index a0cac21..c193341 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -57,9 +57,6 @@
constexpr int NumSegments = 6;
constexpr int NumSysSegments = 4;
-constexpr Addr IntAddrPrefixMask = 0xULL;
-constexpr Addr IntAddrPrefixIO = 0x3ULL;
-
constexpr Addr PhysAddrPrefixIO = 0x8000ULL;
constexpr Addr PhysAddrPrefixLocalAPIC = 0x2000ULL;
constexpr Addr PhysAddrPrefixInterrupts = 0xA000ULL;
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set in the IO permissions bitmap,
+# and raise a #GP if they are.
+def macro m_check_iopb io_port, temp1, temp2 {
+ # Get the IO-permission bitmap base address.
+ld {temp1}, tr, [1, t0, t0], 0x66, dataSize=2, addressSize=8,
atCPL0=True
+
+# Figure out what bytes the bits we want are in.
+srli {temp2}, {io_por
"segment" : self.segment,
-"dataSize" : self.dataSize, "addressSize" : self.addressSize,
-"memFlags" : self.memFlags}
-return allocator
+allocatorTemplate = '''new {self.className}(machInst, macrocodeBlock,
+
}
}
-if (m5Reg.submode != SixtyFourBitMode && addrSize != 64)
-vaddr &= mask(32);
// If paging is enabled, do the translation.
if (m5Reg.paging) {
DPRINTF(TLB, "Paging enabled.\n");
diff --git a/src/arch/x86/uc
ress(0xCFC);
+static const inline AddrRange ConfDataRange =
+{ConfDataAddr, ConfDataAddr + 4};
+
+ public:
+PARAMS(PcPciHost);
+
+PcPciHost(const Params &p) : GenericPciHost(p) {}
+
+AddrRangeList getAddrRanges() const override;
+
+Tick read(PacketPtr pkt) override;
+Tick writ
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--git a/src/dev/storage/ide_ctrl.hh b/src/dev/storage/ide_ctrl.hh
index 635c446..53b4486 100644
--- a/src/dev/storage/ide_ctrl.hh
+++ b/src/dev/storage/ide_ctrl.hh
@@ -204,8 +204,8 @@
virtual void postInterrupt(bool is_primary);
virtual void clearInterrupt(bool is_primary);
-Tick
57010
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const Addr IntAddrPrefixMask = 0xULL;
-const Addr IntAddrPrefixMSR = 0x2ULL;
const Addr IntAddrPrefixIO = 0x3ULL;
const Addr PhysAddrPrefixIO = 0x8000ULL;
--
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case VecRegClass:
+execContextStats.numVecRegWrites++;
+break;
+ case VecPredRegClass:
+execContextStats.numVecPredRegWrites++;
+break;
+ default:
+ break;
+ }
+ return thread->getWritableReg(reg);
}
void
-
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-saved_env = os.environ
-os.environ.update({key: str(val) for key, val in
-kconfig_env['ENV'].items()})
-kconfig = kconfiglib.Kconfig(filename=base_kconfig)
-os.environ = saved_env
+kconfig = _process_kconfig(kconfig_env, base_kconfig)
kconfig.load
config(env, base_kconfig, config_path, main_menu_text,
style='aquatic'):
kconfig_env = _prep_env(env, base_kconfig, config_path)
--
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t;Failed to run savedefconfig")
+
def setconfig(env, base_kconfig, config_path, assignments):
kconfig_env = _prep_env(env, base_kconfig, config_path)
--
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quot;Failed to run oldconfig")
+
def menuconfig(env, base_kconfig, config_path, main_menu_text,
style='aquatic'):
kconfig_env = _prep_env(env, base_kconfig, config_path)
--
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config_env = _prep_env(env, base_kconfig, config_path)
# Provide a little visual separation between SCons output and
--
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G
ource.com/c/public/gem5/+/56929
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ck_type="SoftIntGateCheck"
-legacy_int "legacyModeInterruptWithError", error_code_size=4, \
- error_code_code="st t15, ss, [1, t0, rsp]"
+legacy_int "legacyModeInterruptWithError", with_ec=True
};
undef macro legacy_int;
--
To view, vi
instruction
StaticInstPtr instPtr = NULL;
--
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flags=(CEZF,)
+br "end", flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
ld t1, tsg, [8, t4, t0], dataSize=8
@@ -341,7 +341,7 @@
ld t5, seg, sib, disp, dataSize=2
chks t0, t5, t0, InGDTCheck
andi
ataSize=8
fault "std::make_shared(0)", flags=(CEZF,)
-# Extract the index.
-andi t11, t8, 0xF8, dataSize=8
- # Check if this is a global or local descriptor.
-andi t0, t8, 0x4, flags=(EZF,), dataSize=2
-br "{start_label}_globalSS", flags=(CEZF,)
-ld t12,
de
+++ b/src/arch/x86/microcode/romutil.ucode
@@ -253,8 +253,6 @@
# Go get the stack segment descriptor
# Check for a null selector.
-andi t0, t8, 0xFC, flags=(EZF,), dataSize=8
-fault "std::make_shared(0)", flags=(CEZF,)
m_read_descriptor desc="t12", select
self.microops = microops
self.rom = rom
+self.include_paths = include_paths
self.symbols = {}
def assemble(self, asm, path=None):
--
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t
index 238ce2f..6dd3868 100644
--- a/src/mem/ruby/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -36,7 +36,7 @@
Import('*')
-if env['CONF']['PROTOCOL'] == 'None':
+if not env['CONF']['RUBY']:
Return()
output_dir = Dir(
@@
-TARGET_ISA = 'x86'
-PROTOCOL = 'MI_example'
diff --git a/build_opts/X86_MOESI_AMD_Base b/build_opts/X86_MOESI_AMD_Base
deleted file mode 100644
index 261bedb..000
--- a/build_opts/X86_MOESI_AMD_Base
+++ /dev/null
@@ -1,2 +0,0 @@
-PROTOCOL = 'MOESI_AM
ttings
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+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLI
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