[gem5-dev] [S] Change in gem5/gem5[develop]: base: Remove the Stats namespace
@@
UNIT_UNSPECIFIED, statistics::units::Unspecified::get(), \
"Use statistics::units::Unspecified::get()")
-GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 2c60b47..266f47e 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -83,7 +83,6 @@
#undef TRY_CAST
}
-GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
diff --git a/src/sim/power/mathexpr_powermodel.hh
b/src/sim/power/mathexpr_powermodel.hh
index 25338ee..f05214a 100644
--- a/src/sim/power/mathexpr_powermodel.hh
+++ b/src/sim/power/mathexpr_powermodel.hh
@@ -47,7 +47,6 @@
namespace gem5
{
-GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
class Info;
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index c388539..99c694a 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -57,7 +57,6 @@
namespace gem5
{
-GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
diff --git a/src/sim/stat_control.hh b/src/sim/stat_control.hh
index 22d3134..35d3ea8 100644
--- a/src/sim/stat_control.hh
+++ b/src/sim/stat_control.hh
@@ -48,7 +48,6 @@
namespace gem5
{
-GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
diff --git a/src/sim/stat_register.cc b/src/sim/stat_register.cc
index fb3db1e..5e4bf39 100644
--- a/src/sim/stat_register.cc
+++ b/src/sim/stat_register.cc
@@ -42,7 +42,6 @@
namespace gem5
{
-GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
diff --git a/src/sim/stat_register.hh b/src/sim/stat_register.hh
index d2504f3..e84e8eb 100644
--- a/src/sim/stat_register.hh
+++ b/src/sim/stat_register.hh
@@ -47,7 +47,6 @@
namespace gem5
{
-GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
--
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Gerrit-Change-Id: I80f25af68e03fff3df8316cb4d1d2669687d0fe4
Gerrit-Change-Number: 67359
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Remove the QoS namespace
/public/gem5/+/67356?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2fa66e5fc77f19beaac3251602617704dadaec99 Gerrit-Change-Number: 67356 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Carvalho Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: mem-cache: Remove the ReplacementPolicy namespace
;
-GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
diff --git a/src/mem/cache/replacement_policies/tree_plru_rp.cc
b/src/mem/cache/replacement_policies/tree_plru_rp.cc
index 2ee987c..5014785 100644
--- a/src/mem/cache/replacement_policies/tree_plru_rp.cc
+++ b/src/mem/cache/replacement_policies/tree_plru_rp.cc
@@ -43,7 +43,6 @@
namespace gem5
{
-GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
diff --git a/src/mem/cache/replacement_policies/tree_plru_rp.hh
b/src/mem/cache/replacement_policies/tree_plru_rp.hh
index 3356704..1f7e91c 100644
--- a/src/mem/cache/replacement_policies/tree_plru_rp.hh
+++ b/src/mem/cache/replacement_policies/tree_plru_rp.hh
@@ -80,7 +80,6 @@
struct TreePLRURPParams;
-GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
diff --git a/src/mem/cache/replacement_policies/weighted_lru_rp.cc
b/src/mem/cache/replacement_policies/weighted_lru_rp.cc
index ed6a7f6..ac8fd10 100644
--- a/src/mem/cache/replacement_policies/weighted_lru_rp.cc
+++ b/src/mem/cache/replacement_policies/weighted_lru_rp.cc
@@ -39,7 +39,6 @@
namespace gem5
{
-GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
diff --git a/src/mem/cache/replacement_policies/weighted_lru_rp.hh
b/src/mem/cache/replacement_policies/weighted_lru_rp.hh
index bc0e573..117b73b 100644
--- a/src/mem/cache/replacement_policies/weighted_lru_rp.hh
+++ b/src/mem/cache/replacement_policies/weighted_lru_rp.hh
@@ -42,7 +42,6 @@
struct WeightedLRURPParams;
-GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
diff --git a/src/mem/cache/tags/sector_tags.hh
b/src/mem/cache/tags/sector_tags.hh
index c646212..bad1321 100644
--- a/src/mem/cache/tags/sector_tags.hh
+++ b/src/mem/cache/tags/sector_tags.hh
@@ -47,7 +47,6 @@
namespace gem5
{
-GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
class Base;
--
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Gerrit-Change-Id: If4904706b897999e9200b163d47679519f01e4d4
Gerrit-Change-Number: 67352
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: use origin/develop as default upstream branch
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67331?usp=email ) Change subject: util: use origin/develop as default upstream branch .. util: use origin/develop as default upstream branch The master branch is not in use anymore and it has been renamed to develop instead Change-Id: Ib9ea6e137f1b9284fb8147268b8691d002d3f90a Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67331 Reviewed-by: Richard Cooper Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M util/maint/list_changes.py M util/maint/show_changes_by_file.py 2 files changed, 20 insertions(+), 2 deletions(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/maint/list_changes.py b/util/maint/list_changes.py index 465ae1abb..87e4ea2 100755 --- a/util/maint/list_changes.py +++ b/util/maint/list_changes.py @@ -178,7 +178,7 @@ "--upstream", "-u", type=str, -default="origin/master", +default="origin/develop", help="Upstream branch for comparison. Default: %(default)s", ) parser.add_argument( diff --git a/util/maint/show_changes_by_file.py b/util/maint/show_changes_by_file.py index ea739f7..d5055c1 100755 --- a/util/maint/show_changes_by_file.py +++ b/util/maint/show_changes_by_file.py @@ -94,7 +94,7 @@ "--upstream", "-u", type=str, -default="origin/master", +default="origin/develop", help="Upstream branch for comparison. Default: %(default)s", ) parser.add_argument( -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67331?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib9ea6e137f1b9284fb8147268b8691d002d3f90a Gerrit-Change-Number: 67331 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Export the "reset_in" reset signal from the PL330.
Attention is currently required from: Yu-hsin Wang.
Hello kokoro, Yu-hsin Wang,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/67351?usp=email
to review the following change.
Change subject: fastmodel: Export the "reset_in" reset signal from the
PL330.
..
fastmodel: Export the "reset_in" reset signal from the PL330.
This is essentially the same as how the reset signals were exported
from the CortexR52 which I used as an example, except here there is
only one reset. I passed through with the same name rather than calling
it "model_reset" as in the CortexR52 since the pass through is trivial,
and renaming the signal with no additional functionality seemed like it
would just create confusion. In the CortexR52 case it makes more sense
since there are multiple reset lines that need to be toggled to
actually cause a reset, and a level of abstraction is actually helpful.
Change-Id: I6b61fed6eb1566d131d4b0367fe4ae65031b25f8
Reviewed-on:
https://soc-sim-external-review.googlesource.com/c/gem5/gem5/+/9473
Reviewed-by: Yu-hsin Wang
Presubmit-Ready: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
M src/arch/arm/fastmodel/PL330_DMAC/PL330.lisa
M src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
M src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
4 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
b/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
index ad43fed..21ead52 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
+++ b/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
@@ -26,6 +26,7 @@
from m5.params import *
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
from m5.objects.IntPin import IntSourcePin
+from m5.objects.ResetPort import ResetResponsePort
from m5.objects.SystemC import SystemC_ScModule
@@ -197,6 +198,8 @@
pio_s = AmbaTargetSocket(64, "Register accesses (secure)")
pio_ns = AmbaTargetSocket(64, "Register accesses (non-secure)")
+reset_in = ResetResponsePort("System reset")
+
# irq_abort_master_port
# irq_master_port
# pvbus_m
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/PL330.lisa
b/src/arch/arm/fastmodel/PL330_DMAC/PL330.lisa
index 3c31c90..d57dfda 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/PL330.lisa
+++ b/src/arch/arm/fastmodel/PL330_DMAC/PL330.lisa
@@ -64,6 +64,9 @@
// Interrupts.
pl330.irq_master_port => self.irq;
pl330.irq_abort_master_port => self.irq_abort;
+
+// Reset signals.
+self.reset_in => pl330.reset_in;
}
properties
@@ -85,4 +88,6 @@
master port irq[32];
master port irq_abort;
+
+slave port reset_in;
}
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
index e582404..13162bd 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
+++ b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
@@ -45,7 +45,8 @@
dma(amba_m, params.name + ".dma", -1),
pioS(amba_s, params.name + ".pio_s", -1),
pioNs(amba_s_ns, params.name + ".pio_ns", -1),
-irqAbortReceiver("irq_abort_receiver")
+irqAbortReceiver("irq_abort_receiver"),
+resetIn("reset_in", 0)
{
set_parameter("pl330.fifo_size", params.fifo_size);
set_parameter("pl330.max_transfer", params.max_transfer);
@@ -211,6 +212,9 @@
// And install it.
irqAbortReceiver.onChange(abort_change);
+
+// Plumb the reset signal.
+resetIn.signal_out.bind(this->reset_in);
}
void
@@ -250,6 +254,8 @@
}
if (port != -1 && port < irqPort.size())
return *irqPort[port].at(idx);
+} else if (if_name == "reset_in") {
+return resetIn;
}
return scx_evs_PL330::gem5_getPort(if_name, idx);
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
b/src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
index 3af56f2..389f704 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
+++ b/src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
@@ -39,6 +39,7 @@
#include "arch/arm/fastmodel/amba_ports.hh"
#include "arch/arm/fastmodel/common/signal_receiver.hh"
+#include "arch/arm/fastmodel/common/signal_sender.hh"
#include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh"
#include "dev/intpin.hh"
#include "params/FastModelPL330.hh"
@@ -73,6 +74,8 @@
void allocateIrq(int idx, int count);
+SignalSender resetIn;
+
public:
PL330(const FastModelPL330Params , sc_core::sc_module_name
_name);
PL330(const FastModelPL330Params ) :
--
To view, visit
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: use origin/develop as default upstream branch
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67331?usp=email ) Change subject: util: use origin/develop as default upstream branch .. util: use origin/develop as default upstream branch The master branch is not in use anymore and it has been renamed to develop instead Change-Id: Ib9ea6e137f1b9284fb8147268b8691d002d3f90a Signed-off-by: Giacomo Travaglini --- M util/maint/list_changes.py M util/maint/show_changes_by_file.py 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/util/maint/list_changes.py b/util/maint/list_changes.py index 465ae1abb..87e4ea2 100755 --- a/util/maint/list_changes.py +++ b/util/maint/list_changes.py @@ -178,7 +178,7 @@ "--upstream", "-u", type=str, -default="origin/master", +default="origin/develop", help="Upstream branch for comparison. Default: %(default)s", ) parser.add_argument( diff --git a/util/maint/show_changes_by_file.py b/util/maint/show_changes_by_file.py index ea739f7..d5055c1 100755 --- a/util/maint/show_changes_by_file.py +++ b/util/maint/show_changes_by_file.py @@ -94,7 +94,7 @@ "--upstream", "-u", type=str, -default="origin/master", +default="origin/develop", help="Upstream branch for comparison. Default: %(default)s", ) parser.add_argument( -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67331?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib9ea6e137f1b9284fb8147268b8691d002d3f90a Gerrit-Change-Number: 67331 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: cpu: Formalize a CPU cluster class in the gem5 standard library
ler()
+cpu.socket_id = CpuCluster._NUM_CLUSTERS
+
+# "Register" the cluster/cpus by augmenting the
+# class variables
+CpuCluster._NUM_CPUS += num_cpus
+CpuCluster._NUM_CLUSTERS += 1
+
+def connect(self, membus: "SystemXBar"):
+"""
+Connects every cpu within the cluster with the
+provided bus
+
+:param membus: The system crossbar
+"""
+for cpu in self.cpus:
+cpu.connectBus(membus)
+
+def memory_mode(self) -> "MemoryMode":
+return type(self.cpus[0]).memory_mode()
+
+def require_caches(self) -> bool:
+return type(self.cpus[0]).require_caches()
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 0466f11..d6dcd2f 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -93,6 +93,7 @@
SimObject('CheckerCPU.py', sim_objects=['CheckerCPU'])
SimObject('BaseCPU.py', sim_objects=['BaseCPU'])
+SimObject('CpuCluster.py', sim_objects=['CpuCluster'])
SimObject('CPUTracers.py', sim_objects=[
'ExeTracer', 'IntelTrace', 'NativeTrace'])
SimObject('TimingExpr.py', sim_objects=[
diff --git a/src/cpu/cluster.hh b/src/cpu/cluster.hh
new file mode 100644
index 000..623378a
--- /dev/null
+++ b/src/cpu/cluster.hh
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2022 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_CLUSTER_HH__
+#define __CPU_CLUSTER_HH__
+
+#include "sim/sub_system.hh"
+#include "params/CpuCluster.hh"
+
+namespace gem5
+{
+
+class CpuCluster : public SubSystem
+{
+ public:
+PARAMS(CpuCluster);
+CpuCluster(const Params )
+ : SubSystem(p)
+{}
+};
+
+} // namespace gem5
+
+#endif // __CPU_CLUSTER_HH__
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Idb05263a244e28bffa9eac811c6deb62ebb76a74
Gerrit-Change-Number: 65891
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-CC: Bobby Bruce
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Start using the new CpuCluster class in example/arm
# Add CPU clusters to the system system.cpu_cluster = [ -devices.CpuCluster( +devices.ArmCpuCluster( system, args.num_cores, args.cpu_freq, "1.0V", *cpu_types[args.cpu] ) ] diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py index 08c3d74..ccdbe4f 100644 --- a/configs/example/arm/starter_se.py +++ b/configs/example/arm/starter_se.py @@ -102,14 +102,14 @@ # Create a cache hierarchy (unless we are simulating a # functional CPU in atomic memory mode) for the CPU cluster # and connect it to the shared memory bus. -if self.cpu_cluster.memoryMode() == "timing": +if self.cpu_cluster.memory_mode() == "timing": self.cpu_cluster.addL1() self.cpu_cluster.addL2(self.cpu_cluster.clk_domain) self.cpu_cluster.connectMemSide(self.membus) # Tell gem5 about the memory mode used by the CPUs we are # simulating. -self.mem_mode = self.cpu_cluster.memoryMode() +self.mem_mode = self.cpu_cluster.memory_mode() def numCpuClusters(self): return len(self._clusters) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/65892?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I061c6255449dd126cdd1a6935bea510ebe2e8e14 Gerrit-Change-Number: 65892 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: Yu-hsin Wang Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [L] Change in gem5/gem5[develop]: mem: create port_wrapper classes
bool recvTimingResp(PacketPtr) override;
+void recvReqRetry() override;
+
+void setRangeChangeCallback(RecvReqRetryCallback);
+void setTimingCallbacks(RecvTimingRespCallback, RecvReqRetryCallback);
+
+ private:
+RecvRangeChangeCallback recvRangeChangeCb = nullptr;
+RecvTimingRespCallback recvTimingRespCb = nullptr;
+RecvReqRetryCallback recvReqRetryCb = nullptr;
+};
+
+/**
+ * The ResponsePortWrapper converts inherit-based ResponsePort into
+ * callback-based.
+ */
+class ResponsePortWrapper : public ResponsePort
+{
+ public:
+using GetAddrRangesCallback = std::function;
+// Timing Protocol
+using RecvTimingReqCallback = std::function;
+// Atomic Protocol
+using RecvAtomicCallback = std::function;
+using RecvAtomicBackdoorCallback =
+std::function;
+
+// Functional Protocol
+using RecvFunctionalCallback = std::function;
+using RecvMemBackdoorReqCallback =
+std::function;
+
+using RecvRespRetryCallback = std::function;
+
+ResponsePortWrapper(const std::string& name, SimObject* _owner,
+PortID id = InvalidPortID);
+
+AddrRangeList getAddrRanges() const override;
+
+// TimingResponseProtocol
+bool recvTimingReq(PacketPtr) override;
+void recvRespRetry() override;
+
+// AtomicResponseProtocol
+Tick recvAtomic(PacketPtr) override;
+Tick recvAtomicBackdoor(PacketPtr, MemBackdoorPtr&) override;
+
+// FunctionalResponseProtocol
+void recvFunctional(PacketPtr) override;
+void recvMemBackdoorReq(const MemBackdoorReq&, MemBackdoorPtr&)
override;
+
+void setGetAddrRangesCallback(GetAddrRangesCallback);
+void setTimingCallbacks(RecvTimingReqCallback, RecvRespRetryCallback);
+void setAtomicCallbacks(RecvAtomicCallback,
+RecvAtomicBackdoorCallback = nullptr);
+void setFunctionalCallbacks(RecvFunctionalCallback,
+RecvMemBackdoorReqCallback = nullptr);
+
+ private:
+GetAddrRangesCallback getAddrRangesCb = nullptr;
+RecvTimingReqCallback recvTimingReqCb = nullptr;
+RecvRespRetryCallback recvRespRetryCb = nullptr;
+RecvAtomicCallback recvAtomicCb = nullptr;
+RecvAtomicBackdoorCallback recvAtomicBackdoorCb = nullptr;
+RecvFunctionalCallback recvFunctionalCb = nullptr;
+RecvMemBackdoorReqCallback recvMemBackdoorReqCb = nullptr;
+};
+
+} // namespace gem5
+
+#endif //__MEM_PORT_WRAPPER_HH__
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ia13cc62507ac8425bd7cf143a2e080d041c173f9
Gerrit-Change-Number: 67232
Gerrit-PatchSet: 6
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: fix -Wno-free-nonheap-object for building scheduler.cc
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67237?usp=email )
Change subject: systemc: fix -Wno-free-nonheap-object for building
scheduler.cc
..
systemc: fix -Wno-free-nonheap-object for building scheduler.cc
-Wno-free-nonheap-object can happen at compile or link time depending on
the versions. To better disable this false alarm, we move the memory
management part into .cc file, so the check is always done at link time.
This change also removes the global flags so other code is still checked
with the flags.
Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67237
Tested-by: kokoro
Reviewed-by: Yu-hsin Wang
Maintainer: Gabe Black
---
M SConstruct
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/systemc/core/SConscript
4 files changed, 52 insertions(+), 22 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index bd26e45..e08c2984 100755
--- a/SConstruct
+++ b/SConstruct
@@ -447,10 +447,6 @@
error('gcc version 7 or newer required.\n'
'Installed version:', env['CXXVERSION'])
-with gem5_scons.Configure(env) as conf:
-# This warning has a false positive in the systemc in g++ 11.1.
-conf.CheckCxxFlag('-Wno-free-nonheap-object')
-
# Add the appropriate Link-Time Optimization (LTO) flags if
# `--with-lto` is set.
if GetOption('with_lto'):
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index 66d0385..23ca2f6 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -109,6 +109,32 @@
}
void
+Event::acquire()
+{
+if (flags.isSet(Event::Managed))
+acquireImpl();
+}
+
+void
+Event::release()
+{
+if (flags.isSet(Event::Managed))
+releaseImpl();
+}
+
+void
+Event::acquireImpl()
+{
+}
+
+void
+Event::releaseImpl()
+{
+if (!scheduled())
+delete this;
+}
+
+void
EventQueue::insert(Event *event)
{
// Deal with the head case
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index cd5d285f..62495bf 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -381,26 +381,16 @@
/**
* Managed event scheduled and being held in the event queue.
*/
-void acquire()
-{
-if (flags.isSet(Event::Managed))
-acquireImpl();
-}
+void acquire();
/**
* Managed event removed from the event queue.
*/
-void release() {
-if (flags.isSet(Event::Managed))
-releaseImpl();
-}
+void release();
-virtual void acquireImpl() {}
+virtual void acquireImpl();
-virtual void releaseImpl() {
-if (!scheduled())
-delete this;
-}
+virtual void releaseImpl();
/** @} */
diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 2b88111..c7c9dbb 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -40,6 +40,7 @@
Source('port.cc')
Source('process.cc')
Source('sched_event.cc')
+Source('scheduler.cc')
Source('sensitivity.cc')
Source('time.cc')
@@ -75,7 +76,4 @@
# Disable the false positive warning for the event members of the
scheduler.
with gem5_scons.Configure(env) as conf:
flag = '-Wno-free-nonheap-object'
-append = {}
-if conf.CheckCxxFlag(flag, autoadd=False):
-append['CCFLAGS'] = [flag]
-Source('scheduler.cc', append=append)
+conf.CheckLinkFlag(flag)
--
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Gerrit-Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Gerrit-Change-Number: 67237
Gerrit-PatchSet: 3
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
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[gem5-dev] [M] Change in gem5/gem5[develop]: mem: Implemement backdoor interface for Bridge
Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67291?usp=email )
Change subject: mem: Implemement backdoor interface for Bridge
..
mem: Implemement backdoor interface for Bridge
Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67291
Reviewed-by: Nicolas Boichat
Tested-by: kokoro
Maintainer: Gabe Black
Reviewed-by: Gabe Black
---
M src/mem/bridge.cc
M src/mem/bridge.hh
2 files changed, 49 insertions(+), 8 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
Nicolas Boichat: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 0f744f7..36832eb 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -347,6 +347,14 @@
return delay * bridge.clockPeriod() + memSidePort.sendAtomic(pkt);
}
+Tick
+Bridge::BridgeResponsePort::recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr )
+{
+return delay * bridge.clockPeriod() + memSidePort.sendAtomicBackdoor(
+pkt, backdoor);
+}
+
void
Bridge::BridgeResponsePort::recvFunctional(PacketPtr pkt)
{
@@ -371,6 +379,13 @@
memSidePort.sendFunctional(pkt);
}
+void
+Bridge::BridgeResponsePort::recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr )
+{
+memSidePort.sendMemBackdoorReq(req, backdoor);
+}
+
bool
Bridge::BridgeRequestPort::trySatisfyFunctional(PacketPtr pkt)
{
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index f56cef1..e4a6837 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -195,23 +195,35 @@
/** When receiving a timing request from the peer port,
pass it to the bridge. */
-bool recvTimingReq(PacketPtr pkt);
+bool recvTimingReq(PacketPtr pkt) override;
/** When receiving a retry request from the peer port,
pass it to the bridge. */
-void recvRespRetry();
+void recvRespRetry() override;
-/** When receiving a Atomic requestfrom the peer port,
+/** When receiving an Atomic request from the peer port,
pass it to the bridge. */
-Tick recvAtomic(PacketPtr pkt);
+Tick recvAtomic(PacketPtr pkt) override;
+
+/** When receiving an Atomic backdoor request from the peer port,
+pass it to the bridge. */
+Tick recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr ) override;
+
/** When receiving a Functional request from the peer port,
pass it to the bridge. */
-void recvFunctional(PacketPtr pkt);
+void recvFunctional(PacketPtr pkt) override;
+
+/** When receiving a Functional backdoor request from the peer
port,
+pass it to the bridge. */
+void recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr ) override;
+
/** When receiving a address range request the peer port,
pass it to the bridge. */
-AddrRangeList getAddrRanges() const;
+AddrRangeList getAddrRanges() const override;
};
@@ -303,11 +315,11 @@
/** When receiving a timing request from the peer port,
pass it to the bridge. */
-bool recvTimingResp(PacketPtr pkt);
+bool recvTimingResp(PacketPtr pkt) override;
/** When receiving a retry request from the peer port,
pass it to the bridge. */
-void recvReqRetry();
+void recvReqRetry() override;
};
/** Response port of the bridge. */
--
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Gerrit-Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458
Gerrit-Change-Number: 67291
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Nicolas Boichat
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Yan Lee
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: dev: Add a "resetter" callback to the typed register class.
+ 1;
+EXPECT_EQ(reg.get(), initial_value + 1);
+
+reg.reset();
+
+EXPECT_EQ(reg.get(), initial_value);
+}
+
+// Set a custom resetter for a register.
+TEST_F(TypedRegisterTest, Resetter)
+{
+RegisterBankLE::Register *reg_ptr = nullptr;
+
+reg.resetter([_ptr](auto ) {
+reg_ptr =
+});
+
+reg.reset();
+
+EXPECT_EQ(reg_ptr, );
+}
+
+// Set a custom resetter for a register which is a class method.
+TEST_F(TypedRegisterTest, ResetterMF)
+{
+using Reg = RegisterBankLE::Register;
+
+struct ResetStruct
+{
+Reg *reg_ptr = nullptr;
+
+void
+resetter(Reg )
+{
+reg_ptr =
+}
+} reset_struct;
+
+reg.resetter(_struct, ::resetter);
+
+reg.reset();
+
+EXPECT_EQ(reset_struct.reg_ptr, );
+}
+
TEST_F(TypedRegisterTest, Serialize)
{
std::ostringstream os;
--
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Gerrit-Change-Number: 67203
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jui-min Lee
Gerrit-Reviewer: Yu-hsin Wang
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[gem5-dev] [M] Change in gem5/gem5[develop]: mem: Implemement backdoor interface for Bridge
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67291?usp=email )
Change subject: mem: Implemement backdoor interface for Bridge
..
mem: Implemement backdoor interface for Bridge
Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458
---
M src/mem/bridge.cc
M src/mem/bridge.hh
2 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 0f744f7..36832eb 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -347,6 +347,14 @@
return delay * bridge.clockPeriod() + memSidePort.sendAtomic(pkt);
}
+Tick
+Bridge::BridgeResponsePort::recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr )
+{
+return delay * bridge.clockPeriod() + memSidePort.sendAtomicBackdoor(
+pkt, backdoor);
+}
+
void
Bridge::BridgeResponsePort::recvFunctional(PacketPtr pkt)
{
@@ -371,6 +379,13 @@
memSidePort.sendFunctional(pkt);
}
+void
+Bridge::BridgeResponsePort::recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr )
+{
+memSidePort.sendMemBackdoorReq(req, backdoor);
+}
+
bool
Bridge::BridgeRequestPort::trySatisfyFunctional(PacketPtr pkt)
{
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index f56cef1..e4a6837 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -195,23 +195,35 @@
/** When receiving a timing request from the peer port,
pass it to the bridge. */
-bool recvTimingReq(PacketPtr pkt);
+bool recvTimingReq(PacketPtr pkt) override;
/** When receiving a retry request from the peer port,
pass it to the bridge. */
-void recvRespRetry();
+void recvRespRetry() override;
-/** When receiving a Atomic requestfrom the peer port,
+/** When receiving an Atomic request from the peer port,
pass it to the bridge. */
-Tick recvAtomic(PacketPtr pkt);
+Tick recvAtomic(PacketPtr pkt) override;
+
+/** When receiving an Atomic backdoor request from the peer port,
+pass it to the bridge. */
+Tick recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr ) override;
+
/** When receiving a Functional request from the peer port,
pass it to the bridge. */
-void recvFunctional(PacketPtr pkt);
+void recvFunctional(PacketPtr pkt) override;
+
+/** When receiving a Functional backdoor request from the peer
port,
+pass it to the bridge. */
+void recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr ) override;
+
/** When receiving a address range request the peer port,
pass it to the bridge. */
-AddrRangeList getAddrRanges() const;
+AddrRangeList getAddrRanges() const override;
};
@@ -303,11 +315,11 @@
/** When receiving a timing request from the peer port,
pass it to the bridge. */
-bool recvTimingResp(PacketPtr pkt);
+bool recvTimingResp(PacketPtr pkt) override;
/** When receiving a retry request from the peer port,
pass it to the bridge. */
-void recvReqRetry();
+void recvReqRetry() override;
};
/** Response port of the bridge. */
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct interrupt order
Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67211?usp=email )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-riscv: Correct interrupt order
..
arch-riscv: Correct interrupt order
In Section 3.1.14 of Volume II Riscv Spec., the interrupt order
should be MEI, MSI, MTI, SEI, SSI, STI and so on.
issues:
https://gem5.atlassian.net/browse/GEM5-889
Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67211
Maintainer: Jason Lowe-Power
Reviewed-by: Yu-hsin Wang
Tested-by: kokoro
Reviewed-by: Jui-min Lee
Reviewed-by: Jason Lowe-Power
---
M src/arch/riscv/interrupts.hh
1 file changed, 24 insertions(+), 3 deletions(-)
Approvals:
kokoro: Regressions pass
Jui-min Lee: Looks good to me, but someone else must approve
Yu-hsin Wang: Looks good to me, approved
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index f10c5f3..a1ee396 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -125,9 +125,9 @@
return std::make_shared();
std::bitset mask = globalMask();
const std::vector interrupt_order {
-INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE,
-INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER,
-INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER
+INT_EXT_MACHINE, INT_SOFTWARE_MACHINE, INT_TIMER_MACHINE,
+INT_EXT_SUPER, INT_SOFTWARE_SUPER, INT_TIMER_SUPER,
+INT_EXT_USER, INT_SOFTWARE_USER, INT_TIMER_USER
};
for (const int : interrupt_order)
if (checkInterrupt(id) && mask[id])
--
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Gerrit-Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Gerrit-Change-Number: 67211
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jui-min Lee
Gerrit-Reviewer: Peter Yuen
Gerrit-Reviewer: Roger Chang
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Earl Ou
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check RISCV process run in matched CPU
Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67251?usp=email )
Change subject: arch-riscv: Check RISCV process run in matched CPU
..
arch-riscv: Check RISCV process run in matched CPU
1. Remove set RV32 flag in RiscvProcess32
2. Check if binary run appropriate CPU
Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67251
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/process.cc
1 file changed, 24 insertions(+), 5 deletions(-)
Approvals:
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index dc7abae..cd00f5d 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -101,8 +101,12 @@
Process::initState();
argsInit(PageBytes);
-for (ContextID ctx: contextIds)
-system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+for (ContextID ctx: contextIds) {
+auto *tc = system->threads[ctx];
+tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+auto *isa = dynamic_cast(tc->getIsaPtr());
+fatal_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits
mode");
+}
}
void
@@ -114,9 +118,8 @@
for (ContextID ctx: contextIds) {
auto *tc = system->threads[ctx];
tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
-PCState pc = tc->pcState().as();
-pc.rvType(RV32);
-tc->pcState(pc);
+auto *isa = dynamic_cast(tc->getIsaPtr());
+fatal_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits
mode");
}
}
--
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Gerrit-Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Gerrit-Change-Number: 67251
Gerrit-PatchSet: 4
Gerrit-Owner: Roger Chang
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jui-min Lee
Gerrit-Reviewer: Roger Chang
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Earl Ou
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: dev: Add a "resetter" callback to the typed register class.
EQ(reg.get(), initial_value + 1);
+
+reg.reset();
+
+EXPECT_EQ(reg.get(), initial_value);
+}
+
+// Set a custom resetter for a register.
+TEST_F(TypedRegisterTest, Resetter)
+{
+RegisterBankLE::Register *reg_ptr = nullptr;
+
+reg.resetter([_ptr](auto ) {
+reg_ptr =
+});
+
+reg.reset();
+
+EXPECT_EQ(reg_ptr, );
+}
+
+// Set a custom resetter for a register which is a class method.
+TEST_F(TypedRegisterTest, ResetterMF)
+{
+using Reg = RegisterBankLE::Register;
+
+struct ResetStruct
+{
+Reg *reg_ptr = nullptr;
+
+void
+resetter(Reg )
+{
+reg_ptr =
+}
+} reset_struct;
+
+reg.resetter(_struct, ::resetter);
+
+reg.reset();
+
+EXPECT_EQ(reset_struct.reg_ptr, );
+}
+
TEST_F(TypedRegisterTest, Serialize)
{
std::ostringstream os;
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: fix -Wno-free-nonheap-object for building scheduler.cc
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67237?usp=email )
Change subject: systemc: fix -Wno-free-nonheap-object for building
scheduler.cc
..
systemc: fix -Wno-free-nonheap-object for building scheduler.cc
-Wno-free-nonheap-object need to be added into linker flag as
the this check is actually at link time. This change also removes
the global flags so other code is still checked with the flags.
Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
---
M SConstruct
M src/systemc/core/SConscript
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/SConstruct b/SConstruct
index bd26e45..e08c2984 100755
--- a/SConstruct
+++ b/SConstruct
@@ -447,10 +447,6 @@
error('gcc version 7 or newer required.\n'
'Installed version:', env['CXXVERSION'])
-with gem5_scons.Configure(env) as conf:
-# This warning has a false positive in the systemc in g++ 11.1.
-conf.CheckCxxFlag('-Wno-free-nonheap-object')
-
# Add the appropriate Link-Time Optimization (LTO) flags if
# `--with-lto` is set.
if GetOption('with_lto'):
diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 2b88111..c7c9dbb 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -40,6 +40,7 @@
Source('port.cc')
Source('process.cc')
Source('sched_event.cc')
+Source('scheduler.cc')
Source('sensitivity.cc')
Source('time.cc')
@@ -75,7 +76,4 @@
# Disable the false positive warning for the event members of the
scheduler.
with gem5_scons.Configure(env) as conf:
flag = '-Wno-free-nonheap-object'
-append = {}
-if conf.CheckCxxFlag(flag, autoadd=False):
-append['CCFLAGS'] = [flag]
-Source('scheduler.cc', append=append)
+conf.CheckLinkFlag(flag)
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Gerrit-Change-Number: 67237
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: gpu-compute : Fix incorrect TLB stats when FunctionalTLB is used
VISHNU RAMADAS has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67202?usp=email )
Change subject: gpu-compute : Fix incorrect TLB stats when FunctionalTLB is
used
..
gpu-compute : Fix incorrect TLB stats when FunctionalTLB is used
When FunctionalTLB is used in SE mode, the stats tlbLatency and
tlbCycles report negative values. This patch fixes it by disabling the
updates that result in negative values when FunctionalTLB is set to true
Change-Id: I6962785fc1730b166b6d5b879e9c7618a8d6d4b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67202
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
Maintainer: Matthew Poremba
Reviewed-by: Matthew Poremba
Tested-by: kokoro
---
M src/gpu-compute/compute_unit.cc
1 file changed, 22 insertions(+), 1 deletion(-)
Approvals:
kokoro: Regressions pass
Matt Sinclair: Looks good to me, approved
Matthew Poremba: Looks good to me, approved; Looks good to me, approved
Matt Sinclair: Looks good to me, approved
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index 62cfbf9..06fe28f 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -1078,7 +1078,9 @@
fatal("pkt is not a read nor a write\n");
}
-stats.tlbCycles -= curTick();
+if (!functionalTLB) {
+stats.tlbCycles -= curTick();
+}
++stats.tlbRequests;
PortID tlbPort_index = perLaneTLB ? index : 0;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I6962785fc1730b166b6d5b879e9c7618a8d6d4b3
Gerrit-Change-Number: 67202
Gerrit-PatchSet: 2
Gerrit-Owner: VISHNU RAMADAS
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: VISHNU RAMADAS
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: gpu-compute : Fix incorrect TLB stats when FunctionalTLB is used
VISHNU RAMADAS has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67202?usp=email )
Change subject: gpu-compute : Fix incorrect TLB stats when FunctionalTLB is
used
..
gpu-compute : Fix incorrect TLB stats when FunctionalTLB is used
When FunctionalTLB is used in SE mode, the stats tlbLatency and
tlbCycles report negative values. This patch fixes it by disabling the
updates that result in negative values when FunctionalTLB is set to true
Change-Id: I6962785fc1730b166b6d5b879e9c7618a8d6d4b3
---
M src/gpu-compute/compute_unit.cc
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index 62cfbf9..06fe28f 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -1078,7 +1078,9 @@
fatal("pkt is not a read nor a write\n");
}
-stats.tlbCycles -= curTick();
+if (!functionalTLB) {
+stats.tlbCycles -= curTick();
+}
++stats.tlbRequests;
PortID tlbPort_index = perLaneTLB ? index : 0;
--
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Gerrit-Change-Id: I6962785fc1730b166b6d5b879e9c7618a8d6d4b3
Gerrit-Change-Number: 67202
Gerrit-PatchSet: 1
Gerrit-Owner: VISHNU RAMADAS
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check RISCV process run in matched CPU
Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67251?usp=email )
Change subject: arch-riscv: Check RISCV process run in matched CPU
..
arch-riscv: Check RISCV process run in matched CPU
The process should run correct CPU configuration instead of setting
RISCV flags by process
Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
---
M src/arch/riscv/process.cc
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index dc7abae..e76933e 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -101,8 +101,12 @@
Process::initState();
argsInit(PageBytes);
-for (ContextID ctx: contextIds)
-system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+for (ContextID ctx: contextIds) {
+auto *tc = system->threads[ctx];
+tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+auto isa = dynamic_cast(tc->getIsaPtr());
+panic_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits
mode");
+}
}
void
@@ -114,9 +118,8 @@
for (ContextID ctx: contextIds) {
auto *tc = system->threads[ctx];
tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
-PCState pc = tc->pcState().as();
-pc.rvType(RV32);
-tc->pcState(pc);
+auto isa = dynamic_cast(tc->getIsaPtr());
+panic_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits
mode");
}
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Gerrit-Change-Number: 67251
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: fix warning of auto event deletion
gem5 to let it run events, etc.
gem5::Fiber::primaryFiber()->run();
-if (pauseEvent.scheduled())
-deschedule();
-if (stopEvent.scheduled())
-deschedule();
-if (maxTickEvent.scheduled())
-deschedule();
-if (starvationEvent.scheduled())
-deschedule();
+if (pauseEvent->scheduled())
+deschedule(pauseEvent.get());
+if (stopEvent->scheduled())
+deschedule(stopEvent.get());
+if (maxTickEvent->scheduled())
+deschedule(maxTickEvent.get());
+if (starvationEvent->scheduled())
+deschedule(starvationEvent.get());
if (_throwUp) {
const ::sc_core::sc_report *to_throw = _throwUp;
@@ -449,10 +470,10 @@
void
Scheduler::schedulePause()
{
-if (pauseEvent.scheduled())
+if (pauseEvent->scheduled())
return;
-schedule();
+schedule(pauseEvent.get());
}
void
@@ -472,7 +493,7 @@
void
Scheduler::scheduleStop(bool finish_delta)
{
-if (stopEvent.scheduled())
+if (stopEvent->scheduled())
return;
if (!finish_delta) {
@@ -481,7 +502,7 @@
// pending activity.
clear();
}
-schedule();
+schedule(stopEvent.get());
}
void
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index 6eabb56..a1ee558 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -465,13 +465,16 @@
}
void runReady();
-gem5::EventWrapper readyEvent;
+std::unique_ptr>
+readyEvent;
void scheduleReadyEvent();
void pause();
void stop();
-gem5::EventWrapper pauseEvent;
-gem5::EventWrapper stopEvent;
+std::unique_ptr>
+pauseEvent;
+std::unique_ptr>
+stopEvent;
const ::sc_core::sc_report *_throwUp;
@@ -484,7 +487,8 @@
timeSlots.front()->targeted_when > maxTick) &&
initList.empty());
}
-gem5::EventWrapper starvationEvent;
+std::unique_ptr>
+starvationEvent;
void scheduleStarvationEvent();
bool _elaborationDone;
@@ -502,15 +506,17 @@
_changeStamp++;
pause();
}
-gem5::EventWrapper maxTickEvent;
+std::unique_ptr>
+maxTickEvent;
void timeAdvances() { trace(false); }
-gem5::EventWrapper
timeAdvancesEvent;
+std::unique_ptr::timeAdvances>>
+timeAdvancesEvent;
void
scheduleTimeAdvancesEvent()
{
-if (!traceFiles.empty() && !timeAdvancesEvent.scheduled())
-schedule();
+if (!traceFiles.empty() && !timeAdvancesEvent->scheduled())
+schedule(timeAdvancesEvent.get());
}
uint64_t _numCycles;
--
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Gerrit-Change-Id: Iadff0240b5d108a448799ee55f9e6c24992d7af2
Gerrit-Change-Number: 67236
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: fix TCP spacing/spelling
Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67200?usp=email )
Change subject: mem-ruby: fix TCP spacing/spelling
..
mem-ruby: fix TCP spacing/spelling
Change-Id: I3fd9009592c8716a3da19dcdccf68f16af6522ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67200
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
1 file changed, 19 insertions(+), 6 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 14bdcec..6a977c4 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -261,7 +261,7 @@
// If L1 is disabled or requests have GLC or SLC flag set,
// then, the requests should not cache in the L1. The
response
// from L2/global memory should bypass the cache
- trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
+ trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
} else {
if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.addr)) {
trigger(Event:TCC_Ack, in_msg.addr, cache_entry, tbe);
@@ -288,7 +288,7 @@
DPRINTF(RubySlicc, "%s\n", in_msg);
if (in_msg.Type == RubyRequestType:LD) {
if ((in_msg.isGLCSet || in_msg.isSLCSet) &&
is_valid(cache_entry)) {
-// Read rquests with GLC or SLC bit set should not cache in
the L1.
+// Read requests with GLC or SLC bit set should not cache in
the L1.
// They need to bypass the L1 and go to the L2. If an entry
exists
// in the L1, it needs to be evicted
trigger(Event:LoadBypassEvict, in_msg.LineAddress,
cache_entry, tbe);
@@ -609,15 +609,15 @@
p_popMandatoryQueue;
}
-// Transition to be called when a load request with GLC or SLC flag set
arrives
-// at L1. This transition invalidates any existing entry and forwards the
-// request to L2.
+ // Transition to be called when a load request with GLC or SLC flag set
arrives
+ // at L1. This transition invalidates any existing entry and forwards the
+ // request to L2.
transition(V, LoadBypassEvict, I) {TagArrayRead, TagArrayWrite} {
uu_profileDataMiss;
ic_invCache;
n_issueRdBlk;
p_popMandatoryQueue;
-}
+ }
transition({V, I}, Atomic, A) {TagArrayRead, TagArrayWrite} {
t_allocateTBE;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3fd9009592c8716a3da19dcdccf68f16af6522ef
Gerrit-Change-Number: 67200
Gerrit-PatchSet: 2
Gerrit-Owner: Matt Sinclair
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: VISHNU RAMADAS
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby, gpu-compute: fix TCP GLC cache bypassing
Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67199?usp=email )
Change subject: mem-ruby, gpu-compute: fix TCP GLC cache bypassing
..
mem-ruby, gpu-compute: fix TCP GLC cache bypassing
66d4a158 added support for AMD's GPU cache bypassing flags (GLC
for bypassing L1 caches, SLC for bypassing all caches). However,
for applications that use the GLC flag but intermix GLC- and
non-GLC accesses to the same address, this previous commit
has a bug. This bug manifests when the address is currently
valid in the L1 (TCP). In this case, the previous commit chose
to evict the line before letting the bypassing access to proceed.
However, to do this the previous commit was using the inv_invDone
action as part of the process of evicting it. This action is only
intended to be called when load acquires are being performed
(i.e., when the entire L1 cache is being flash invalidated). Thus,
calling inv_invDone for a GLC (or SLC) bypassing request caused an
assert failure since the bypassing request was not performing a
load acquire.
This commit resolves this by changing the support in this case to
simply invalidate the entry in the cache.
Change-Id: Ibaa4976f8714ac93650020af1c0ce2b6732c95a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67199
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
Maintainer: Jason Lowe-Power
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
1 file changed, 31 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 3be1397..14bdcec 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -614,7 +614,6 @@
// request to L2.
transition(V, LoadBypassEvict, I) {TagArrayRead, TagArrayWrite} {
uu_profileDataMiss;
-inv_invDone;
ic_invCache;
n_issueRdBlk;
p_popMandatoryQueue;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ibaa4976f8714ac93650020af1c0ce2b6732c95a2
Gerrit-Change-Number: 67199
Gerrit-PatchSet: 2
Gerrit-Owner: Matt Sinclair
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: VISHNU RAMADAS
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: add GPU cache bypass I->I transition
Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67201?usp=email )
Change subject: mem-ruby: add GPU cache bypass I->I transition
..
mem-ruby: add GPU cache bypass I->I transition
66d4a158 added support for AMD's GPU cache bypassing flags (GLC
for bypassing L1 caches, SLC for bypassing all caches). However,
it did not add a transition for the situation where the cache line
is currently I (Invalid). This commit adds this support, which
resolves an assert failure in Pannotia workloads when this situation
arises.
Change-Id: I59a62ce70c01dd8b73aacb733fb3d1d0dab2624b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67201
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
Maintainer: Jason Lowe-Power
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
1 file changed, 29 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 6a977c4..7e0ad4e 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -619,6 +619,15 @@
p_popMandatoryQueue;
}
+ // Transition to be called when a load request with GLC or SLC flag set
arrives
+ // at L1. Since the entry is invalid, there isn't anything to forward to
L2,
+ // so just issue read.
+ transition(I, LoadBypassEvict) {TagArrayRead, TagArrayWrite} {
+uu_profileDataMiss;
+n_issueRdBlk;
+p_popMandatoryQueue;
+ }
+
transition({V, I}, Atomic, A) {TagArrayRead, TagArrayWrite} {
t_allocateTBE;
mru_updateMRU;
--
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Gerrit-Change-Id: I59a62ce70c01dd8b73aacb733fb3d1d0dab2624b
Gerrit-Change-Number: 67201
Gerrit-PatchSet: 2
Gerrit-Owner: Matt Sinclair
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: VISHNU RAMADAS
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add handler to catch DMI warnings
Nicolas Boichat has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67235?usp=email )
Change subject: fastmodel: Add handler to catch DMI warnings
..
fastmodel: Add handler to catch DMI warnings
Catch DMI warnings from fastmodel, and abort the simulation when
they happen (instead of slowing down simulation).
This is controlled by an exit_on_dmi_warning flag passed to
fm.setup_simulation, defaulting to false.
Change-Id: I07fbc9b2579989d40d601ff0b6af9bfe719309a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67235
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/arm_fast_model.py
M src/arch/arm/fastmodel/fastmodel.cc
2 files changed, 47 insertions(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/arm_fast_model.py
b/src/arch/arm/fastmodel/arm_fast_model.py
index 1100417..d2d911f 100644
--- a/src/arch/arm/fastmodel/arm_fast_model.py
+++ b/src/arch/arm/fastmodel/arm_fast_model.py
@@ -141,7 +141,11 @@
# This should be called once per simulation
-def setup_simulation(sim_name, min_sync_latency=100.0 / 1):
+def setup_simulation(
+sim_name, min_sync_latency=100.0 / 1, exit_on_dmi_warning=False
+):
set_armlmd_license_file()
scx_initialize(sim_name)
scx_set_min_sync_latency(min_sync_latency)
+if exit_on_dmi_warning:
+_m5.arm_fast_model.gem5.enable_exit_on_dmi_warning_handler()
diff --git a/src/arch/arm/fastmodel/fastmodel.cc
b/src/arch/arm/fastmodel/fastmodel.cc
index 33a0c43..2edf1fa 100644
--- a/src/arch/arm/fastmodel/fastmodel.cc
+++ b/src/arch/arm/fastmodel/fastmodel.cc
@@ -37,9 +37,11 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "base/logging.hh"
#include "python/pybind11/pybind.hh"
#include "scx/scx.h"
#include "sim/init.hh"
+#include "systemc/utils/report.hh"
namespace gem5
{
@@ -48,6 +50,21 @@
{
void
+fastmodel_sc_report_handler(
+ const sc_core::sc_report , const sc_core::sc_actions )
+{
+const char *msg = report.get_msg();
+if (!msg)
+return;
+
+panic_if(
+strstr(msg, "Simulation code-translation cache failed to gain
DMI") ||
+strstr(msg, "I-side given unusable DMI"),
+"DMI warning from fastmodel, "
+"aborting simulation instead of running slowly.");
+}
+
+void
arm_fast_model_pybind(pybind11::module_ _internal)
{
auto arm_fast_model = m_internal.def_submodule("arm_fast_model");
@@ -118,6 +135,12 @@
static_cast *)>(
::scx_get_min_sync_latency))
;
+
+// submodule for gem5-specific functions
+auto gem5 = arm_fast_model.def_submodule("gem5");
+gem5.def("enable_exit_on_dmi_warning_handler", []() {
+
sc_gem5::addExtraSystemCReportHandler(fastmodel_sc_report_handler);
+});
}
EmbeddedPyBind embed_("arm_fast_model", _fast_model_pybind);
--
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Gerrit-Change-Id: I07fbc9b2579989d40d601ff0b6af9bfe719309a1
Gerrit-Change-Number: 67235
Gerrit-PatchSet: 3
Gerrit-Owner: Nicolas Boichat
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Nicolas Boichat
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: Add facilities to add extra SystemC message handlers
Nicolas Boichat has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67234?usp=email )
Change subject: systemc: Add facilities to add extra SystemC message
handlers
..
systemc: Add facilities to add extra SystemC message handlers
Some clients (e.g. fastmodel integration) would like to catch specific
warning messages from SystemC. Adding facilities to chain extra report
handler (instead of just replacing the default one), that are run
after the default/set handler.
Change-Id: I8ef140fc897ae5eee0fc78c70caf081f625efbfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67234
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/systemc/utils/report.cc
M src/systemc/utils/report.hh
M src/systemc/utils/sc_report_handler.cc
3 files changed, 55 insertions(+), 0 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/utils/report.cc b/src/systemc/utils/report.cc
index 2b15fce..5f3425f 100644
--- a/src/systemc/utils/report.cc
+++ b/src/systemc/utils/report.cc
@@ -68,6 +68,31 @@
sc_core::sc_report_handler_proc reportHandlerProc =
_core::sc_report_handler::default_handler;
+namespace
+{
+
+std::list extraReportHandlerProcs;
+
+} // anonymous namespace
+
+const std::list &
+getExtraSystemCReportHandlers()
+{
+return extraReportHandlerProcs;
+}
+
+void
+addExtraSystemCReportHandler(sc_core::sc_report_handler_proc proc)
+{
+extraReportHandlerProcs.push_back(proc);
+}
+
+void
+removeExtraSystemCReportHandler(sc_core::sc_report_handler_proc proc)
+{
+extraReportHandlerProcs.remove(proc);
+}
+
std::unique_ptr globalReportCache;
bool reportWarningsAsErrors = false;
diff --git a/src/systemc/utils/report.hh b/src/systemc/utils/report.hh
index 1f12eef..d7ea340 100644
--- a/src/systemc/utils/report.hh
+++ b/src/systemc/utils/report.hh
@@ -29,6 +29,7 @@
#define __SYSTEMC_UTILS_REPORT_HH__
#include
+#include
#include
#include
#include
@@ -103,6 +104,13 @@
extern sc_core::sc_report_handler_proc reportHandlerProc;
+// gem5-specific support for extra SystemC report handlers. Called _after_
+// the default/set handler.
+const std::list
+();
+void addExtraSystemCReportHandler(sc_core::sc_report_handler_proc proc);
+void removeExtraSystemCReportHandler(sc_core::sc_report_handler_proc proc);
+
extern std::unique_ptr globalReportCache;
extern bool reportWarningsAsErrors;
diff --git a/src/systemc/utils/sc_report_handler.cc
b/src/systemc/utils/sc_report_handler.cc
index b893b1d..3421ab9 100644
--- a/src/systemc/utils/sc_report_handler.cc
+++ b/src/systemc/utils/sc_report_handler.cc
@@ -103,6 +103,10 @@
}
sc_gem5::reportHandlerProc(report, actions);
+
+for (auto& handler : sc_gem5::getExtraSystemCReportHandlers()) {
+handler(report, actions);
+}
}
void
--
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Gerrit-Change-Number: 67234
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Gerrit-Owner: Nicolas Boichat
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Nicolas Boichat
Gerrit-Reviewer: kokoro
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby, gpu-compute: fix TCP GLC cache bypassing
Matt Sinclair has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67199?usp=email )
Change subject: mem-ruby, gpu-compute: fix TCP GLC cache bypassing
..
mem-ruby, gpu-compute: fix TCP GLC cache bypassing
66d4a158 added support for AMD's GPU cache bypassing flags (GLC
for bypassing L1 caches, SLC for bypassing all caches). However,
for applications that use the GLC flag but intermix GLC- and
non-GLC accesses to the same address, this previous commit
has a bug. This bug manifests when the address is currently
valid in the L1 (TCP). In this case, the previous commit chose
to evict the line before letting the bypassing access to proceed.
However, to do this the previous commit was using the inv_invDone
action as part of the process of evicting it. This action is only
intended to be called when load acquires are being performed
(i.e., when the entire L1 cache is being flash invalidated). Thus,
calling inv_invDone for a GLC (or SLC) bypassing request caused an
assert failure since the bypassing request was not performing a
load acquire.
This commit resolves this by changing the support in this case to
simply invalidate the entry in the cache.
Change-Id: Ibaa4976f8714ac93650020af1c0ce2b6732c95a2
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 3be1397..14bdcec 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -614,7 +614,6 @@
// request to L2.
transition(V, LoadBypassEvict, I) {TagArrayRead, TagArrayWrite} {
uu_profileDataMiss;
-inv_invDone;
ic_invCache;
n_issueRdBlk;
p_popMandatoryQueue;
--
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Gerrit-Change-Id: Ibaa4976f8714ac93650020af1c0ce2b6732c95a2
Gerrit-Change-Number: 67199
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: fix TCP spacing/spelling
Matt Sinclair has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67200?usp=email )
Change subject: mem-ruby: fix TCP spacing/spelling
..
mem-ruby: fix TCP spacing/spelling
Change-Id: I3fd9009592c8716a3da19dcdccf68f16af6522ef
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 14bdcec..6a977c4 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -261,7 +261,7 @@
// If L1 is disabled or requests have GLC or SLC flag set,
// then, the requests should not cache in the L1. The
response
// from L2/global memory should bypass the cache
- trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
+ trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
} else {
if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.addr)) {
trigger(Event:TCC_Ack, in_msg.addr, cache_entry, tbe);
@@ -288,7 +288,7 @@
DPRINTF(RubySlicc, "%s\n", in_msg);
if (in_msg.Type == RubyRequestType:LD) {
if ((in_msg.isGLCSet || in_msg.isSLCSet) &&
is_valid(cache_entry)) {
-// Read rquests with GLC or SLC bit set should not cache in
the L1.
+// Read requests with GLC or SLC bit set should not cache in
the L1.
// They need to bypass the L1 and go to the L2. If an entry
exists
// in the L1, it needs to be evicted
trigger(Event:LoadBypassEvict, in_msg.LineAddress,
cache_entry, tbe);
@@ -609,15 +609,15 @@
p_popMandatoryQueue;
}
-// Transition to be called when a load request with GLC or SLC flag set
arrives
-// at L1. This transition invalidates any existing entry and forwards the
-// request to L2.
+ // Transition to be called when a load request with GLC or SLC flag set
arrives
+ // at L1. This transition invalidates any existing entry and forwards the
+ // request to L2.
transition(V, LoadBypassEvict, I) {TagArrayRead, TagArrayWrite} {
uu_profileDataMiss;
ic_invCache;
n_issueRdBlk;
p_popMandatoryQueue;
-}
+ }
transition({V, I}, Atomic, A) {TagArrayRead, TagArrayWrite} {
t_allocateTBE;
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: add GPU cache bypass I->I transition
Matt Sinclair has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67201?usp=email )
Change subject: mem-ruby: add GPU cache bypass I->I transition
..
mem-ruby: add GPU cache bypass I->I transition
66d4a158 added support for AMD's GPU cache bypassing flags (GLC
for bypassing L1 caches, SLC for bypassing all caches). However,
it did not add a transition for the situation where the cache line
is currently I (Invalid). This commit adds this support, which
resolves an assert failure in Pannotia workloads when this situation
arises.
Change-Id: I59a62ce70c01dd8b73aacb733fb3d1d0dab2624b
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
1 file changed, 25 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 6a977c4..7e0ad4e 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -619,6 +619,15 @@
p_popMandatoryQueue;
}
+ // Transition to be called when a load request with GLC or SLC flag set
arrives
+ // at L1. Since the entry is invalid, there isn't anything to forward to
L2,
+ // so just issue read.
+ transition(I, LoadBypassEvict) {TagArrayRead, TagArrayWrite} {
+uu_profileDataMiss;
+n_issueRdBlk;
+p_popMandatoryQueue;
+ }
+
transition({V, I}, Atomic, A) {TagArrayRead, TagArrayWrite} {
t_allocateTBE;
mru_updateMRU;
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: cleanup m5out directly in weekly
Matt Sinclair has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67198?usp=email )
Change subject: tests: cleanup m5out directly in weekly
..
tests: cleanup m5out directly in weekly
The weekly test script was implicitly assuming that no m5out
directory existed in the folder where the script was run.
However, if a prior test ran and failed, it would not clean up
its m5out directory, causing the weekly tests to fail.
This commit resolves this by removing the m5out directory before
trying to run any tests in the weekly script. Moreover, we also
update the weekly script to explicitly remove this m5out directory
at the end of the script.
Change-Id: If10c59034528e171cc2c5dacb928b3a81d6b8c50
---
M tests/weekly.sh
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/tests/weekly.sh b/tests/weekly.sh
index c7f834b..f218729 100755
--- a/tests/weekly.sh
+++ b/tests/weekly.sh
@@ -70,10 +70,11 @@
# GPU weekly tests start here
# before pulling gem5 resources, make sure it doesn't exist already
+# likewise, remove any lingering m5out folder
docker run --rm --volume "${gem5_root}":"${gem5_root}" -w \
"${gem5_root}" --memory="${docker_mem_limit}" \
gcr.io/gem5-test/gcn-gpu:${tag} bash -c \
- "rm -rf ${gem5_root}/gem5-resources"
+ "rm -rf ${gem5_root}/gem5-resources ${gem5_root}/m5out"
# delete Pannotia datasets and output files in case a failed regression
run left
# them around
rm -f coAuthorsDBLP.graph 1k_128k.gr result.out
@@ -383,5 +384,11 @@
"${gem5_root}" --memory="${docker_mem_limit}" hacc-test-weekly bash
-c \
"rm -rf ${gem5_root}/gem5-resources"
+# Delete the gem5 m5out folder we created -- need to do in docker because
it
+# creates
+docker run --rm --volume "${gem5_root}":"${gem5_root}" -w \
+ "${gem5_root}" --memory="${docker_mem_limit}" hacc-test-weekly bash
-c \
+ "rm -rf ${gem5_root}/m5out"
+
# delete Pannotia datasets we downloaded and output files it created
rm -f coAuthorsDBLP.graph 1k_128k.gr result.out
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: Add facilities to add extra SystemC message handlers
Nicolas Boichat has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67234?usp=email )
Change subject: systemc: Add facilities to add extra SystemC message
handlers
..
systemc: Add facilities to add extra SystemC message handlers
Some clients (e.g. fastmodel integration) would like to catch specific
warning messages from SystemC. Adding facilities to chain extra report
handler (instead of just replacing the default one), that are run
after the default/set handler.
Change-Id: I8ef140fc897ae5eee0fc78c70caf081f625efbfd
---
M src/systemc/utils/report.cc
M src/systemc/utils/report.hh
M src/systemc/utils/sc_report_handler.cc
3 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/src/systemc/utils/report.cc b/src/systemc/utils/report.cc
index 2b15fce..5f3425f 100644
--- a/src/systemc/utils/report.cc
+++ b/src/systemc/utils/report.cc
@@ -68,6 +68,31 @@
sc_core::sc_report_handler_proc reportHandlerProc =
_core::sc_report_handler::default_handler;
+namespace
+{
+
+std::list extraReportHandlerProcs;
+
+} // anonymous namespace
+
+const std::list &
+getExtraSystemCReportHandlers()
+{
+return extraReportHandlerProcs;
+}
+
+void
+addExtraSystemCReportHandler(sc_core::sc_report_handler_proc proc)
+{
+extraReportHandlerProcs.push_back(proc);
+}
+
+void
+removeExtraSystemCReportHandler(sc_core::sc_report_handler_proc proc)
+{
+extraReportHandlerProcs.remove(proc);
+}
+
std::unique_ptr globalReportCache;
bool reportWarningsAsErrors = false;
diff --git a/src/systemc/utils/report.hh b/src/systemc/utils/report.hh
index 1f12eef..d7ea340 100644
--- a/src/systemc/utils/report.hh
+++ b/src/systemc/utils/report.hh
@@ -29,6 +29,7 @@
#define __SYSTEMC_UTILS_REPORT_HH__
#include
+#include
#include
#include
#include
@@ -103,6 +104,13 @@
extern sc_core::sc_report_handler_proc reportHandlerProc;
+// gem5-specific support for extra SystemC report handlers. Called _after_
+// the default/set handler.
+const std::list
+();
+void addExtraSystemCReportHandler(sc_core::sc_report_handler_proc proc);
+void removeExtraSystemCReportHandler(sc_core::sc_report_handler_proc proc);
+
extern std::unique_ptr globalReportCache;
extern bool reportWarningsAsErrors;
diff --git a/src/systemc/utils/sc_report_handler.cc
b/src/systemc/utils/sc_report_handler.cc
index b893b1d..3421ab9 100644
--- a/src/systemc/utils/sc_report_handler.cc
+++ b/src/systemc/utils/sc_report_handler.cc
@@ -103,6 +103,10 @@
}
sc_gem5::reportHandlerProc(report, actions);
+
+for (auto& handler : sc_gem5::getExtraSystemCReportHandlers()) {
+handler(report, actions);
+}
}
void
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add handler to catch DMI warnings
Nicolas Boichat has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67235?usp=email )
Change subject: fastmodel: Add handler to catch DMI warnings
..
fastmodel: Add handler to catch DMI warnings
Catch DMI warnings from fastmodel, and abort the simulation when
they happen (instead of slowing down simulation).
This is controlled by an exit_on_dmi_warning flag passed to
fm.setup_simulation, defaulting to false.
Change-Id: I07fbc9b2579989d40d601ff0b6af9bfe719309a1
---
M src/arch/arm/fastmodel/arm_fast_model.py
M src/arch/arm/fastmodel/fastmodel.cc
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/arm_fast_model.py
b/src/arch/arm/fastmodel/arm_fast_model.py
index 1100417..48b4634 100644
--- a/src/arch/arm/fastmodel/arm_fast_model.py
+++ b/src/arch/arm/fastmodel/arm_fast_model.py
@@ -141,7 +141,10 @@
# This should be called once per simulation
-def setup_simulation(sim_name, min_sync_latency=100.0 / 1):
+def setup_simulation(sim_name, min_sync_latency=100.0 / 1,
+ exit_on_dmi_warning=False):
set_armlmd_license_file()
scx_initialize(sim_name)
scx_set_min_sync_latency(min_sync_latency)
+if exit_on_dmi_warning:
+_m5.arm_fast_model.gem5.enable_exit_on_dmi_warning_handler()
diff --git a/src/arch/arm/fastmodel/fastmodel.cc
b/src/arch/arm/fastmodel/fastmodel.cc
index 33a0c43..2edf1fa 100644
--- a/src/arch/arm/fastmodel/fastmodel.cc
+++ b/src/arch/arm/fastmodel/fastmodel.cc
@@ -37,9 +37,11 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "base/logging.hh"
#include "python/pybind11/pybind.hh"
#include "scx/scx.h"
#include "sim/init.hh"
+#include "systemc/utils/report.hh"
namespace gem5
{
@@ -48,6 +50,21 @@
{
void
+fastmodel_sc_report_handler(
+ const sc_core::sc_report , const sc_core::sc_actions )
+{
+const char *msg = report.get_msg();
+if (!msg)
+return;
+
+panic_if(
+strstr(msg, "Simulation code-translation cache failed to gain
DMI") ||
+strstr(msg, "I-side given unusable DMI"),
+"DMI warning from fastmodel, "
+"aborting simulation instead of running slowly.");
+}
+
+void
arm_fast_model_pybind(pybind11::module_ _internal)
{
auto arm_fast_model = m_internal.def_submodule("arm_fast_model");
@@ -118,6 +135,12 @@
static_cast *)>(
::scx_get_min_sync_latency))
;
+
+// submodule for gem5-specific functions
+auto gem5 = arm_fast_model.def_submodule("gem5");
+gem5.def("enable_exit_on_dmi_warning_handler", []() {
+
sc_gem5::addExtraSystemCReportHandler(fastmodel_sc_report_handler);
+});
}
EmbeddedPyBind embed_("arm_fast_model", _fast_model_pybind);
--
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Gerrit-Change-Id: I07fbc9b2579989d40d601ff0b6af9bfe719309a1
Gerrit-Change-Number: 67235
Gerrit-PatchSet: 1
Gerrit-Owner: Nicolas Boichat
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Clone env before modifying it in SharedLib
Nicolas Boichat has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67233?usp=email ) Change subject: scons: Clone env before modifying it in SharedLib .. scons: Clone env before modifying it in SharedLib Without this, modifications to env propagate to unexpected places. This mirrors behaviour in Executable (where the code was copied from). Change-Id: I35bbf2f3cc2786eb50ff751c813853971ab284fe Signed-off-by: Nicolas Boichat Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67233 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Reviewed-by: Gabe Black Tested-by: kokoro --- M src/SConscript 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass Gabe Black: Looks good to me, approved diff --git a/src/SConscript b/src/SConscript index 51b4bd9..3179849 100644 --- a/src/SConscript +++ b/src/SConscript @@ -376,6 +376,8 @@ def declare(self, env): objs = self.srcs_to_objs(env, self.sources(env)) +env = env.Clone() + libs = self.libs(env) # Higher priority libraries should be earlier in the list. libs.sort(key=lambda l: l.priority, reverse=True) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67233?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I35bbf2f3cc2786eb50ff751c813853971ab284fe Gerrit-Change-Number: 67233 Gerrit-PatchSet: 2 Gerrit-Owner: Nicolas Boichat Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nicolas Boichat Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Added LoopPoint checkpoint specific generator
Zhantong Qiu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67197?usp=email )
Change subject: stdlib: Added LoopPoint checkpoint specific generator
..
stdlib: Added LoopPoint checkpoint specific generator
Added looppoint_save_checkpoint_generator to take checkpoints for
LoopPoint methodology.
Users can decide to update the relative counts storing in the LoopPoint
module and exit when all the target PC-count pairs are encountered or
not.
Change-Id: Id1cf1516f4fa838e20a67530e94b361e42ca09f3
---
M src/python/gem5/simulate/exit_event_generators.py
1 file changed, 59 insertions(+), 0 deletions(-)
diff --git a/src/python/gem5/simulate/exit_event_generators.py
b/src/python/gem5/simulate/exit_event_generators.py
index d6732bb..7d940d5 100644
--- a/src/python/gem5/simulate/exit_event_generators.py
+++ b/src/python/gem5/simulate/exit_event_generators.py
@@ -29,6 +29,7 @@
from ..components.processors.abstract_processor import AbstractProcessor
from ..components.processors.switchable_processor import
SwitchableProcessor
from ..utils.simpoint import SimPoint
+from gem5.utils.looppoint import LoopPoint
from m5.util import warn
from pathlib import Path
@@ -167,3 +168,46 @@
yield False
else:
yield True
+
+
+def looppoint_save_checkpoint_generator(
+checkpoint_dir: Path,
+looppoint: LoopPoint,
+update_relatives: bool = True,
+exit_when_empty: bool = True,
+):
+"""
+A generator for taking a checkpoint for LoopPoint. It will save the
+checkpoints in the checkpoint_dir path with the Region id.
+(i.e. "cpt.Region10) It only takes a checkpoint if the current PC Count
+pair is a significant PC Count Pair. This is determined in the
LoopPoint
+module. The simulation loop continues after exiting this generator.
+:param checkpoint_dir: where to save the checkpoints
+:param loopoint: the looppoint object used in the configuration script
+:param update_relative: if the generator should update the relative
count
+information in the output json file, then it should be True. It is
default
+as True.
+:param exit_when_empty: if the generator should exit the simulation
loop if
+all PC paris have been discovered, then it should be True. It is
default as
+True.
+"""
+if exit_when_empty:
+total_pairs = len(looppoint.get_targets())
+else:
+total_pairs = -1
+# it will never equal to 0 if exit_when_empty is false
+
+while total_pairs != 0:
+region = looppoint.get_current_region()
+# if it is a significant PC Count pair, then the
get_current_region()
+# will return an integer greater than 0. By significant PC Count
pair,
+# it means the PC Count pair that indicates where to take the
+# checkpoint at. This is determined in the LoopPoint module.
+if region != -1:
+if update_relatives:
+looppoint.update_relatives_counts()
+m5.checkpoint((checkpoint_dir /
f"cpt.Region{region}").as_posix())
+total_pairs -= 1
+yield False
+
+yield True
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Allow se_binary_workload to setup LoopPoints
Zhantong Qiu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67196?usp=email )
Change subject: stdlib: Allow se_binary_workload to setup LoopPoints
..
stdlib: Allow se_binary_workload to setup LoopPoints
Added a set_se_looppoint_workload function to take in information for
workload and a stdlib LoopPoint object that stores all the information
the workload needed to run the LoopPoint sampling method.
Added a get_looppoint function to return the stdlib LoopPoint object.
Change-Id: I7afc5c4c743256f7df97345f331b6f72b7a5fd07
---
M src/python/gem5/components/boards/se_binary_workload.py
1 file changed, 59 insertions(+), 0 deletions(-)
diff --git a/src/python/gem5/components/boards/se_binary_workload.py
b/src/python/gem5/components/boards/se_binary_workload.py
index 8ec112e..253e796 100644
--- a/src/python/gem5/components/boards/se_binary_workload.py
+++ b/src/python/gem5/components/boards/se_binary_workload.py
@@ -27,6 +27,7 @@
from .abstract_board import AbstractBoard
from ...resources.resource import AbstractResource
from gem5.utils.simpoint import SimPoint
+from gem5.utils.looppoint import LoopPoint
from m5.objects import SEWorkload, Process
@@ -169,3 +170,47 @@
if getattr(self, "_simpoint_object", None):
return self._simpoint_object
raise Exception("This board does not have a simpoint set.")
+
+def set_se_looppoint_workload(
+self,
+binary: AbstractResource,
+arguments: List[str] = [],
+looppoint: Optional[Union[AbstractResource, LoopPoint]] = None,
+checkpoint: Optional[Union[Path, AbstractResource]] = None,
+) -> None:
+"""Set up the system to run a LoopPoint workload.
+
+**Limitations**
+* Dynamically linked executables are partially supported when the
host
+ ISA and the simulated ISA are the same.
+
+:param binary: The resource encapsulating the binary to be run.
+:param arguments: The input arguments for the binary
+:param looppoint: The LoopPoint object that contain all the
information
+gather from the LoopPoint files and a LoopPointManager that will
raise
+exit events for LoopPoints
+"""
+
+if isinstance(looppoint, AbstractResource):
+self._looppoint_object = LoopPoint(looppoint)
+else:
+assert isinstance(looppoint, LoopPoint)
+self._looppoint_object = looppoint
+
+self._looppoint_object.setup_processor(self.get_processor())
+
+# Call set_se_binary_workload after LoopPoint setup is complete
+self.set_se_binary_workload(
+binary=binary,
+arguments=arguments,
+checkpoint=checkpoint,
+)
+
+def get_looppoint(self) -> LoopPoint:
+"""
+Returns the LoopPoint object set. If no LoopPoint object has been
set
+an exception is thrown.
+"""
+if getattr(self, "_looppoint_object", None):
+return self._looppoint_object
+raise Exception("This board does not have a looppoint set.")
--
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[gem5-dev] [L] Change in gem5/gem5[develop]: stdlib: Added stdlib LoopPoint classes
+start = sim_start
+region_id[start] = rid
+
+
+class LoopPointRestore(LoopPoint):
+def __init__(self, looppoint_file: Path, checkpoint_path: Path) ->
None:
+"""
+This class is specifically designed to take in the LoopPoint data
file and
+generator information needed to restore a checkpoint taken by the
+LoopPointCheckPoint.
+:param looppoint_file: a json file generated by gem5 that has all
the
+LoopPoint data information
+:param checkpoint_path: the director of the checkpoint taken by
the gem5
+standard library looppoint_save_checkpoint_generator
+
+"""
+
+_json_file = {}
+_targets = []
+_region_id = {}
+
+self.profile_restore(
+looppoint_file, checkpoint_path, _targets, _json_file,
_region_id
+)
+
+super().__init__(
+_targets,
+_region_id,
+_json_file,
+)
+
+def profile_restore(
+self,
+looppoint_file_path: Path,
+checkpoint_dir: Path,
+targets: List[PcCountPair],
+json_file: Dict[int, Dict],
+region_id: Dict[PcCountPair, int],
+) -> None:
+"""
+This function is used to profile data from the LoopPoint data file
to
+information needed to restore the LoopPoint checkpoint
+:param looppoint_file_path: the director of the LoopPoint data file
+:param targets: a list of PcCountPair
+:param json_file: a dictionary for all the LoopPoint data
+:param region_id: a dictionary for all the significant PcCountPair
and
+its corresponding region id
+"""
+regex = re.compile(r"cpt.Region([0-9]+)")
+rid = regex.findall(checkpoint_dir.as_posix())[0]
+# finds out the region id from the directory name
+with open(looppoint_file_path) as file:
+json_file = json.load(file)
+ if rid not in json_file:
+ # if the region id does not exist in the LoopPoint data
file
+ # raise a fatal message
+ fatal(f"{rid} is not a valid region\n")
+region = json_file[rid]
+if "warmup" in region:
+if "relative" not in region["simulation"]["start"]:
+# if there are not relative counts for the PC Count
pair
+# then it means there is not enough information to
restore
+# this checkpoint
+fatal(f"region {rid} doesn't have relative count
info\n")
+start = PcCountPair(
+region["simulation"]["start"]["pc"],
+region["simulation"]["start"]["relative"],
+)
+region_id[start] = rid
+targets.append(start)
+if "relative" not in region["simulation"]["end"]:
+fatal(f"region {rid} doesn't have relative count info\n")
+end = PcCountPair(
+region["simulation"]["end"]["pc"],
+region["simulation"]["end"]["relative"],
+)
+region_id[end] = rid
+targets.append(end)
--
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[gem5-dev] [L] Change in gem5/gem5[develop]: sim: Added PcCountTracker and PcCountTrackerManager
d Program
+ * Counter address
+ */
+int
+getPcCount(Addr pc) const
+{
+if (counter.find(pc) != counter.end()) {
+return counter.find(pc)->second;
+}
+return -1;
+}
+
+/** this function returns the current PC Count pair
+ *
+ * @return current PC Count pair
+ */
+PcCountPair
+getCurrentPcCountPair() const
+{
+return currentPair;
+}
+
+/** this function print all targets
+ *
+ * @return formatted string that contains all targets
+ */
+ std::string
+printAllTargets() const
+{
+std::string s;
+for(auto itr = targetPair.begin();
+itr != targetPair.end();
+ ++itr) {
+s += itr->to_string();
+s += "\n";
+}
+return s;
+}
+};
+
+}
+
+#endif // __CPU_PROBES_PC_COUNT_TRACKER_MANAGER_HH__
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: base,python: Added PcCountPair type and parameter
tPair into C++ PcCountPair
+from _m5.pc import PcCountPair
+
+return PcCountPair(self.pc, self.count)
+
+def __str__(self):
+return "(%i,%i)" % (self.pc, self.count)
+
+def __eq__(self, other):
+return self.pc == other.getPC() and self.count == other.getCount()
+
+def __hash__(self):
+return hash((int(self.pc), int(self.count)))
+
+@classmethod
+def cxx_predecls(cls, code):
+code('#include "cpu/probes/pc_count_pair.hh"')
+
+@classmethod
+def pybind_predecls(cls, code):
+code('#include "cpu/probes/pc_count_pair.hh"')
+
+
class AddrRange(ParamValue):
cxx_type = "AddrRange"
@@ -2426,4 +2466,5 @@
"VectorMasterPort",
"VectorSlavePort",
"DeprecatedParam",
+"PcCountPair",
]
diff --git a/src/python/pybind11/core.cc b/src/python/pybind11/core.cc
index 8946675..44a52a8 100644
--- a/src/python/pybind11/core.cc
+++ b/src/python/pybind11/core.cc
@@ -58,6 +58,7 @@
#include "sim/drain.hh"
#include "sim/serialize.hh"
#include "sim/sim_object.hh"
+#include "cpu/probes/pc_count_pair.hh"
namespace py = pybind11;
@@ -164,6 +165,31 @@
}
static void
+init_pc(py::module_ _native)
+{
+py::module_ m = m_native.def_submodule("pc");
+py::class_(m, "PcCountPair")
+.def(py::init<>())
+.def(py::init())
+.def("__eq__", [](const PcCountPair& self, py::object other) {
+py::int_ pyPC = other.attr("getPC")();
+py::int_ pyCount = other.attr("getCount")();
+uint64_t cPC = pyPC.cast();
+int cCount = pyCount.cast();
+return (self.getPC() == cPC && self.getCount() == cCount);
+})
+.def("__hash__", [](const PcCountPair& self){
+py::int_ pyPC = py::cast(self.getPC());
+py::int_ pyCount = py::cast(self.getCount());
+return py::hash(py::make_tuple(pyPC, pyCount));
+})
+.def("__str__", ::to_string)
+.def("getPC", ::getPC)
+.def("getCount", ::getCount)
+;
+}
+
+static void
init_net(py::module_ _native)
{
py::module_ m = m_native.def_submodule("net");
@@ -307,6 +333,7 @@
init_range(m_native);
init_net(m_native);
init_loader(m_native);
+init_pc(m_native);
}
} // namespace gem5
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Clone env before modifying it in SharedLib
Nicolas Boichat has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67233?usp=email ) Change subject: scons: Clone env before modifying it in SharedLib .. scons: Clone env before modifying it in SharedLib Without this, modifications to env propagate to unexpected places. This mirrors behaviour in Executable (where the code was copied from). Change-Id: I35bbf2f3cc2786eb50ff751c813853971ab284fe Signed-off-by: Nicolas Boichat --- M src/SConscript 1 file changed, 15 insertions(+), 0 deletions(-) diff --git a/src/SConscript b/src/SConscript index 51b4bd9..3179849 100644 --- a/src/SConscript +++ b/src/SConscript @@ -376,6 +376,8 @@ def declare(self, env): objs = self.srcs_to_objs(env, self.sources(env)) +env = env.Clone() + libs = self.libs(env) # Higher priority libraries should be earlier in the list. libs.sort(key=lambda l: l.priority, reverse=True) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67233?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I35bbf2f3cc2786eb50ff751c813853971ab284fe Gerrit-Change-Number: 67233 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: cpu-o3: Resolve the skid buffer overflow issue at decode stage
Hanhwi Jang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67231?usp=email )
Change subject: cpu-o3: Resolve the skid buffer overflow issue at decode
stage
..
cpu-o3: Resolve the skid buffer overflow issue at decode stage
When decode width is larger than fetch width, the skid buffer
overflow happens at decode stage. The decode stage assumes
that fetch stage sends instructions as many as the fetch width,
but it sends them at decode width rate.
This patch makes the decode stage set its skid buffer size
according to the decode width.
Change-Id: I90ee43d16c59a4c9305c77bbfad7e4cdb2b9cffa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67231
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Reviewed-by: Hanhwi Jang
Reviewed-by: Tom Rollet
Tested-by: kokoro
---
M src/cpu/o3/decode.cc
1 file changed, 24 insertions(+), 1 deletion(-)
Approvals:
Tom Rollet: Looks good to me, but someone else must approve
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
kokoro: Regressions pass
Hanhwi Jang: Looks good to me, approved
diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index 9555e32..ac728a2 100644
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -77,7 +77,7 @@
decodeWidth, static_cast(MaxWidth));
// @todo: Make into a parameter
-skidBufferMax = (fetchToDecodeDelay + 1) * params.fetchWidth;
+skidBufferMax = (fetchToDecodeDelay + 1) * params.decodeWidth;
for (int tid = 0; tid < MaxThreads; tid++) {
stalls[tid] = {false};
decodeStatus[tid] = Idle;
--
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Gerrit-PatchSet: 2
Gerrit-Owner: Hanhwi Jang
Gerrit-Reviewer: Hanhwi Jang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tom Rollet
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: gpu-compute, mem-ruby: Add p_popRequestQueue to some transitions
VISHNU RAMADAS has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67192?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: gpu-compute, mem-ruby: Add p_popRequestQueue to some
transitions
..
gpu-compute, mem-ruby: Add p_popRequestQueue to some transitions
Two W->WI transitions, on events RdBlk and Atomic in the GPU L2 cache
coherence protocol do not clear the request from the request queue upon
completing the transition. This action is not performed in the respone
path. This update adds the p_popRequestQueue action to each of these
transitions to remove the stale request from the queue.
Change-Id: Ia2679fe3dd702f4df2bc114f4607ba40c18d6ff1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67192
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 21 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index ca4c543..0f93339 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -721,6 +721,7 @@
p_profileHit;
t_allocateTBE;
wb_writeBack;
+p_popRequestQueue;
}
transition(I, RdBlk, IV) {TagArrayRead} {
@@ -815,6 +816,7 @@
p_profileHit;
t_allocateTBE;
wb_writeBack;
+p_popRequestQueue;
}
transition(I, WrVicBlk) {TagArrayRead} {
--
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Gerrit-Owner: VISHNU RAMADAS
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: VISHNU RAMADAS
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: gpu-compute, mem-ruby: Update GPU cache bypassing to use TBE
k := in_msg.DataBlk;
-out_msg.isGLCSet := in_msg.isGLCSet;
-out_msg.isSLCSet := in_msg.isSLCSet;
}
}
}
@@ -636,8 +624,6 @@
out_msg.Type := MemoryRequestType:MEMORY_READ;
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Request_Control;
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
}
}
}
@@ -753,8 +739,6 @@
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Destination := probe_dests;
tbe.NumPendingAcks := out_msg.Destination.count();
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
DPRINTF(RubySlicc, "%s\n", out_msg);
APPEND_TRANSITION_COMMENT(" dc: Acks remaining: ");
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
@@ -858,8 +842,6 @@
out_msg.ReturnData := true;
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Destination := probe_dests;
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
tbe.NumPendingAcks := out_msg.Destination.count();
DPRINTF(RubySlicc, "%s\n", (out_msg));
APPEND_TRANSITION_COMMENT(" sc: Acks remaining: ");
@@ -915,8 +897,6 @@
out_msg.ReturnData := false;
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Destination := probe_dests;
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
tbe.NumPendingAcks := out_msg.Destination.count();
APPEND_TRANSITION_COMMENT(" ic: Acks remaining: ");
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
@@ -943,8 +923,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := in_msg.DataBlk;
-out_msg.isGLCSet := in_msg.isGLCSet;
-out_msg.isSLCSet := in_msg.isSLCSet;
}
if (tbe.Dirty == false) {
// have to update the TBE, too, because of how this
@@ -1007,8 +985,6 @@
tbe.NumPendingAcks := 0;
tbe.Cached := in_msg.ForceShared;
tbe.InitialRequestTime := in_msg.InitialRequestTime;
- tbe.isGLCSet := in_msg.isGLCSet;
- tbe.isSLCSet := in_msg.isSLCSet;
}
}
@@ -1028,8 +1004,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := tbe.DataBlk;
-out_msg.isGLCSet := tbe.isGLCSet;
-out_msg.isSLCSet := tbe.isSLCSet;
DPRINTF(ProtocolTrace, "%s\n", out_msg);
}
}
@@ -1130,8 +1104,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := victim_entry.DataBlk;
-out_msg.isGLCSet := in_msg.isGLCSet;
-out_msg.isSLCSet := in_msg.isSLCSet;
}
L3CacheMemory.deallocate(victim);
}
@@ -1164,8 +1136,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := victim_entry.DataBlk;
-out_msg.isGLCSet := tbe.isGLCSet;
-out_msg.isSLCSet := tbe.isSLCSet;
}
L3CacheMemory.deallocate(victim);
}
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
index 6ff19e9..bb3a013 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
@@ -168,8 +168,6 @@
MachineID Requestor, desc="Requestor id for 3-hop requests";
bool NoAckNeeded, default="false", desc="For short circuting acks";
int ProgramCounter, desc="PC that accesses to this block";
- bool isGLCSet,desc="Bypass L1 Cache";
- bool isSLCSet,desc="Bypass L1 and L2 Caches";
bool functionalRead(Packet *pkt) {
return false;
--
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Gerrit-Change-Id: I20ffa6682d109270adb921de078cfd47fb4e137c
Gerrit-Change-Number: 67191
Gerrit-PatchSet: 6
Gerrit-Owner: VISHNU RAMADAS
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: VISHNU RAMADAS
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Read one dword for SGPR base global insts
}
if (isFlat()) {
@@ -974,6 +980,12 @@
}
}
+bool
+vgprIsOffset()
+{
+return (extData.SADDR != 0x7f);
+}
+
// first instruction DWORD
InFmt_FLAT instData;
// second instruction DWORD
@@ -987,7 +999,7 @@
void generateGlobalDisassembly();
void
-calcAddrSgpr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 ,
+calcAddrSgpr(GPUDynInstPtr gpuDynInst, ConstVecOperandU32 ,
ConstScalarOperandU64 , ScalarRegI32 offset)
{
// Use SGPR pair as a base address and add VGPR-offset and
--
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Gerrit-Change-Number: 67077
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_write2st64_b64
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67078?usp=email )
Change subject: arch-vega: Implement ds_write2st64_b64
..
arch-vega: Implement ds_write2st64_b64
Write two qwords at offsets multiplied by 8 * 64 bytes.
Change-Id: I0d0e05f3e848c2fd02d32095e32b7f023bd8803b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67078
Reviewed-by: Matt Sinclair
Tested-by: kokoro
Maintainer: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 62 insertions(+), 1 deletion(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 4b27afa..6cf01fb 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -36595,8 +36595,52 @@
void
Inst_DS__DS_WRITE2ST64_B64::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU64 data0(gpuDynInst, extData.DATA0);
+ConstVecOperandU64 data1(gpuDynInst, extData.DATA1);
+
+addr.read();
+data0.read();
+data1.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(
+gpuDynInst->d_data))[lane * 2] = data0[lane];
+(reinterpret_cast(
+gpuDynInst->d_data))[lane * 2 + 1] = data1[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_WRITE2ST64_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0 * 8 * 64;
+Addr offset1 = instData.OFFSET1 * 8 * 64;
+
+initDualMemWrite(gpuDynInst, offset0, offset1);
+}
+
+void
+Inst_DS__DS_WRITE2ST64_B64::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+}
// --- Inst_DS__DS_CMPST_B64 class methods ---
Inst_DS__DS_CMPST_B64::Inst_DS__DS_CMPST_B64(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 9f017f9..2896732 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33572,6 +33572,8 @@
} // getOperandSize
void execute(GPUDynInstPtr) override;
+void initiateAcc(GPUDynInstPtr) override;
+void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_WRITE2ST64_B64
class Inst_DS__DS_CMPST_B64 : public Inst_DS
--
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Gerrit-Change-Number: 67078
Gerrit-PatchSet: 3
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_read_i8
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67076?usp=email )
Change subject: arch-vega: Implement ds_read_i8
..
arch-vega: Implement ds_read_i8
Read one byte with sign extended from LDS.
Change-Id: I9cb9b4033c6f834241cba944bc7e6a7ebc5401be
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67076
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 60 insertions(+), 1 deletion(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index a54f426..c803656 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -35636,8 +35636,50 @@
void
Inst_DS__DS_READ_I8::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+addr.read();
+
+calcAddr(gpuDynInst, addr);
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_READ_I8::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initMemRead(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_READ_I8::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+vdst[lane] =
(VecElemU32)sext<8>((reinterpret_cast(
+gpuDynInst->d_data))[lane]);
+}
+}
+
+vdst.write();
+} // completeAcc
// --- Inst_DS__DS_READ_U8 class methods ---
Inst_DS__DS_READ_U8::Inst_DS__DS_READ_U8(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index f8fc98b..b2cf2b9 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -32848,6 +32848,8 @@
} // getOperandSize
void execute(GPUDynInstPtr) override;
+void initiateAcc(GPUDynInstPtr) override;
+void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_READ_I8
class Inst_DS__DS_READ_U8 : public Inst_DS
--
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Gerrit-Change-Number: 67076
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_u64
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67075?usp=email )
Change subject: arch-vega: Implement ds_add_u64
..
arch-vega: Implement ds_add_u64
This instruction does an atomic add of an unsigned 64-bit data with a
VGPR and value in LDS atomically without return.
Change-Id: I6a7d6713b256607c4e69ddbdef5c83172493c077
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67075
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
Tested-by: kokoro
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 64 insertions(+), 3 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 3d9808a..a54f426 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -36088,6 +36088,10 @@
Inst_DS__DS_ADD_U64::Inst_DS__DS_ADD_U64(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u64")
{
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U64
Inst_DS__DS_ADD_U64::~Inst_DS__DS_ADD_U64()
@@ -36096,14 +36100,53 @@
// --- description from .arch file ---
// 64b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA[0:1];
-// RETURN_DATA[0:1] = tmp.
void
Inst_DS__DS_ADD_U64::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU64 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_U64::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_U64::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_SUB_U64 class methods ---
Inst_DS__DS_SUB_U64::Inst_DS__DS_SUB_U64(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 05a0002..f8fc98b 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33079,6 +33079,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U64
--
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Gerrit-Change-Number: 67075
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[gem5-dev] [M] Change in gem5/gem5[develop]: base: Specialize bitwise atomics so FP types can be used
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67073?usp=email )
Change subject: base: Specialize bitwise atomics so FP types can be used
..
base: Specialize bitwise atomics so FP types can be used
The current atomic memory operations are templated so any type can be
used. However floating point types can not perform bitwise operations.
The GPU model contains some instructions which do atomics on floating
point types, so they need to be supported. To allow this, template
specialization is added to atomic AND, OR, and XOR which does nothing
if the type is floating point and operates as normal for integral
types.
Change-Id: I60f935756355462e99c59a9da032c5bf5afa246c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67073
Reviewed-by: Matt Sinclair
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
Maintainer: Matt Sinclair
---
M src/base/amo.hh
1 file changed, 52 insertions(+), 3 deletions(-)
Approvals:
kokoro: Regressions pass
Daniel Carvalho: Looks good to me, approved
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
diff --git a/src/base/amo.hh b/src/base/amo.hh
index 81bf069..c990d15 100644
--- a/src/base/amo.hh
+++ b/src/base/amo.hh
@@ -129,30 +129,57 @@
template
class AtomicOpAnd : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b &= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpAnd(T _a) : a(_a) { }
-void execute(T *b) { *b &= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpAnd(a); }
};
template
class AtomicOpOr : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b |= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpOr(T _a) : a(_a) { }
-void execute(T *b) { *b |= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpOr(a); }
};
template
class AtomicOpXor : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b ^= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpXor(T _a) : a(_a) {}
-void execute(T *b) { *b ^= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpXor(a); }
};
--
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Gerrit-Change-Number: 67073
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_f32 atomic
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67074?usp=email )
Change subject: arch-vega: Implement ds_add_f32 atomic
..
arch-vega: Implement ds_add_f32 atomic
This instruction does an atomic add of a 32-bit float with a VGPR and
value in LDS atomically without return.
Change-Id: Id4f23a1ab587a23edfd1d88ede1cbcc5bdedc0cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67074
Maintainer: Matt Sinclair
Reviewed-by: Matt Sinclair
Tested-by: kokoro
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 64 insertions(+), 3 deletions(-)
Approvals:
kokoro: Regressions pass
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index afdfde3..3d9808a 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34755,6 +34755,10 @@
: Inst_DS(iFmt, "ds_add_f32")
{
setFlag(F32);
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_F32
Inst_DS__DS_ADD_F32::~Inst_DS__DS_ADD_F32()
@@ -34763,15 +34767,54 @@
// --- description from .arch file ---
// 32b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA;
-// RETURN_DATA = tmp.
// Floating point add that handles NaN/INF/denormal values.
void
Inst_DS__DS_ADD_F32::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandF32 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_F32::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_F32::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_WRITE_B8 class methods ---
Inst_DS__DS_WRITE_B8::Inst_DS__DS_WRITE_B8(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 33be33e..05a0002 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31895,6 +31895,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_F32
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id4f23a1ab587a23edfd1d88ede1cbcc5bdedc0cb
Gerrit-Change-Number: 67074
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update run_gem5_fs.sh script with AArch64 platform
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66856?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: util: Update run_gem5_fs.sh script with AArch64 platform
..
util: Update run_gem5_fs.sh script with AArch64 platform
The example script is using VExpress_EMM, which is a deprecated platform
and it is referring to an AArch32 kernel. With this patch we
use the VExpress_GEM5_Foundation platform instead and point
to a AArch64 kernel
Change-Id: I961d5d5de71bc284c7492ee7b04088148909ca1b
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66856
Maintainer: Daniel Carvalho
Reviewed-by: Matthias Jung
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
---
M util/tlm/README
M util/tlm/run_gem5_fs.sh
2 files changed, 26 insertions(+), 7 deletions(-)
Approvals:
Matthias Jung: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/tlm/README b/util/tlm/README
index 8098afa..3ae43c5 100644
--- a/util/tlm/README
+++ b/util/tlm/README
@@ -145,10 +145,9 @@
> ../../build/ARM/gem5.opt ../../configs/example/fs.py \
--tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1 \
--mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
- --l2cache --machine-type=VExpress_EMM \
- --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb\
- --kernel=vmlinux.aarch32.ll_20131205.0-gem5\
- --disk-image=linux-aarch32-ael.img
+ --l2cache --machine-type=VExpress_GEM5_Foundation \
+ --kernel=vmlinux.arm64 \
+ --disk-image=ubuntu-18.04-arm64-docker.img
The message "fatal: Can't find port handler type 'tlm_slave'" is okay.
The configuration will be stored in the m5out/ directory
diff --git a/util/tlm/run_gem5_fs.sh b/util/tlm/run_gem5_fs.sh
index 9065cbf..d8ab847 100755
--- a/util/tlm/run_gem5_fs.sh
+++ b/util/tlm/run_gem5_fs.sh
@@ -42,9 +42,9 @@
--mem-size=512MB\
--mem-channels=1\
--caches --l2cache \
---machine-type=VExpress_EMM \
---dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
---kernel=vmlinux.aarch32.ll_20131205.0-gem5
+--machine-type=VExpress_GEM5_Foundation \
+--kernel=vmlinux.arm64 \
+--disk-image=ubuntu-18.04-arm64-docker.img
echo -e "\n${BGre}Run gem5 ${RCol}\n"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I961d5d5de71bc284c7492ee7b04088148909ca1b
Gerrit-Change-Number: 66856
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Matthias Jung
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Include libraries when building gem5 as a shared object
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66855?usp=email ) Change subject: scons: Include libraries when building gem5 as a shared object .. scons: Include libraries when building gem5 as a shared object While we include shared libraries in the Executable class, we are not doing it when linking the SharedLib. This means the resulting Shared library won't have the library as a dependency (it won't appear in ldd) and the symbols will remain undefined. Any executable will fail to link with the shared library as the executable will contain undefined references. This bug was exposed when I tried to link util/tlm sources with libgem5.so. As I have libpng/libpng-dev installed in my machine, the shared library included libpng headers, but didn't link to the library as scons didn't append "-lpng" to the linking CL. Those png functions thus remained ubdefined symbols. Change-Id: Id9c4a65607a7177f71659f1ac400a67edf7080fd Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66855 Tested-by: kokoro Reviewed-by: Gabe Black Maintainer: Daniel Carvalho Reviewed-by: Daniel Carvalho Reviewed-by: Bobby Bruce --- M src/SConscript 1 file changed, 36 insertions(+), 0 deletions(-) Approvals: Daniel Carvalho: Looks good to me, but someone else must approve; Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass Bobby Bruce: Looks good to me, approved diff --git a/src/SConscript b/src/SConscript index 4e7139c..51b4bd9 100644 --- a/src/SConscript +++ b/src/SConscript @@ -376,6 +376,12 @@ def declare(self, env): objs = self.srcs_to_objs(env, self.sources(env)) +libs = self.libs(env) +# Higher priority libraries should be earlier in the list. +libs.sort(key=lambda l: l.priority, reverse=True) +if libs: +env.Append(LIBS=list(lib.source for lib in libs)) + date_obj = env.SharedObject(date_source) env.Depends(date_obj, objs) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66855?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id9c4a65607a7177f71659f1ac400a67edf7080fd Gerrit-Change-Number: 66855 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [L] Change in gem5/gem5[develop]: base: socket: add UnixSocketAddr for representing socket paths
edMemoryServer(const SharedMemoryServerParams&
params)
-: SimObject(params),
unixSocketPath(simout.resolve(params.server_path)),
- system(params.system), serverFd(-1)
+: SimObject(params),
+ sockAddr(UnixSocketAddr::build(params.server_path)),
+ system(params.system),
+ serverFd(-1)
{
fatal_if(system == nullptr, "Requires a system to share memory from!");
// Create a new unix socket.
serverFd = ListenSocket::socketCloexec(AF_UNIX, SOCK_STREAM, 0);
panic_if(serverFd < 0, "%s: cannot create unix socket: %s", name(),
strerror(errno));
-// Bind to the specified path.
-sockaddr_un serv_addr = {};
-serv_addr.sun_family = AF_UNIX;
-strncpy(serv_addr.sun_path, unixSocketPath.c_str(),
-sizeof(serv_addr.sun_path) - 1);
-// If the target path is truncated, warn the user that the actual path
is
-// different and update the target path.
-if (strlen(serv_addr.sun_path) != unixSocketPath.size()) {
-warn("%s: unix socket path truncated, expect '%s' but get '%s'",
- name(), unixSocketPath, serv_addr.sun_path);
-unixSocketPath = serv_addr.sun_path;
+
+const auto& [serv_addr, addr_size, is_abstract, formatted_path] =
sockAddr;
+
+if (!is_abstract) {
+// Ensure the unix socket path to use is not occupied. Also, if
there's
+// actually anything to be removed, warn the user something might
be
+// off.
+bool old_sock_removed = unlink(serv_addr.sun_path) == 0;
+warn_if(old_sock_removed,
+"%s: server path %s was occupied and will be replaced.
Please "
+"make sure there is no other server using the same path.",
+name(), serv_addr.sun_path);
}
-// Ensure the unix socket path to use is not occupied. Also, if there's
-// actually anything to be removed, warn the user something might be
off.
-bool old_sock_removed = unlink(unixSocketPath.c_str()) == 0;
-warn_if(old_sock_removed,
-"%s: the server path %s was occupied and will be replaced.
Please "
-"make sure there is no other server using the same path.",
-name(), unixSocketPath);
-int bind_retv = bind(serverFd, reinterpret_cast(_addr),
- sizeof(serv_addr));
-fatal_if(bind_retv != 0, "%s: cannot bind unix socket: %s", name(),
- strerror(errno));
+int bind_retv = bind(
+serverFd, reinterpret_cast(_addr),
addr_size);
+fatal_if(bind_retv != 0, "%s: cannot bind unix socket '%s': %s",
name(),
+ formatted_path, strerror(errno));
// Start listening.
int listen_retv = listen(serverFd, 1);
fatal_if(listen_retv != 0, "%s: listen failed: %s", name(),
strerror(errno));
listenSocketEvent.reset(new ListenSocketEvent(serverFd, this));
pollQueue.schedule(listenSocketEvent.get());
-inform("%s: listening at %s", name(), unixSocketPath);
+inform("%s: listening at %s", name(), formatted_path);
}
SharedMemoryServer::~SharedMemoryServer()
{
-int unlink_retv = unlink(unixSocketPath.c_str());
-warn_if(unlink_retv != 0, "%s: cannot unlink unix socket: %s", name(),
-strerror(errno));
+if (!sockAddr.isAbstract) {
+int unlink_retv = unlink(sockAddr.addr.sun_path);
+warn_if(unlink_retv != 0, "%s: cannot unlink unix socket: %s",
name(),
+strerror(errno));
+}
int close_retv = close(serverFd);
warn_if(close_retv != 0, "%s: cannot close unix socket: %s", name(),
strerror(errno));
diff --git a/src/mem/shared_memory_server.hh
b/src/mem/shared_memory_server.hh
index 8f573fe..d9fbeb3 100644
--- a/src/mem/shared_memory_server.hh
+++ b/src/mem/shared_memory_server.hh
@@ -33,6 +33,7 @@
#include
#include "base/pollevent.hh"
+#include "base/socket.hh"
#include "params/SharedMemoryServer.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
@@ -82,7 +83,7 @@
void process(int revent) override;
};
-std::string unixSocketPath;
+UnixSocketAddr sockAddr;
System* system;
int serverFd;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibf105b92a6a6ac7fc9136ed307f824c83e45c06c
Gerrit-Change-Number: 66471
Gerrit-PatchSet: 11
Gerrit-Owner: Simon Park
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jui-min Lee
Gerrit-Reviewer: Simon Park
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [L] Change in gem5/gem5[develop]: mem: create simple_port classes
override; +Tick recvAtomicBackdoor(PacketPtr, MemBackdoorPtr&) override; + +// FunctionalResponseProtocol +void recvFunctional(PacketPtr) override; +void recvMemBackdoorReq(const MemBackdoorReq&, MemBackdoorPtr&) override; + +void setGetAddrRangesCallback(GetAddrRangesCallback); +void setTimingCallbacks(RecvTimingReqCallback, RecvRespRetryCallback); +void setAtomicCallbacks(RecvAtomicCallback, +RecvAtomicBackdoorCallback = nullptr); +void setFunctionalCallbacks(RecvFunctionalCallback, +RecvMemBackdoorReqCallback = nullptr); + + private: +GetAddrRangesCallback getAddrRangesCb = nullptr; +RecvTimingReqCallback recvTimingReqCb = nullptr; +RecvRespRetryCallback recvRespRetryCb = nullptr; +RecvAtomicCallback recvAtomicCb = nullptr; +RecvAtomicBackdoorCallback recvAtomicBackdoorCb = nullptr; +RecvFunctionalCallback recvFunctionalCb = nullptr; +RecvMemBackdoorReqCallback recvMemBackdoorReqCb = nullptr; +}; + +} // namespace gem5 + +#endif //__MEM_SIMPLE_PORT_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67232?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia13cc62507ac8425bd7cf143a2e080d041c173f9 Gerrit-Change-Number: 67232 Gerrit-PatchSet: 1 Gerrit-Owner: Earl Ou Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: cpu-o3: Resolve the skid buffer overflow issue at decode stage
Hanhwi Jang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67231?usp=email )
Change subject: cpu-o3: Resolve the skid buffer overflow issue at decode
stage
..
cpu-o3: Resolve the skid buffer overflow issue at decode stage
When decode width is larger than fetch width, the skid buffer
overflow happens at decode stage. The decode stage assumes
that fetch stage sends instructions as many as the fetch width,
but it sends them at decode width rate.
This patch makes the decode stage set its skid buffer size
according to the decode width.
Change-Id: I90ee43d16c59a4c9305c77bbfad7e4cdb2b9cffa
---
M src/cpu/o3/decode.cc
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index 9555e32..ac728a2 100644
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -77,7 +77,7 @@
decodeWidth, static_cast(MaxWidth));
// @todo: Make into a parameter
-skidBufferMax = (fetchToDecodeDelay + 1) * params.fetchWidth;
+skidBufferMax = (fetchToDecodeDelay + 1) * params.decodeWidth;
for (int tid = 0; tid < MaxThreads; tid++) {
stalls[tid] = {false};
decodeStatus[tid] = Idle;
--
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Gerrit-Change-Id: I90ee43d16c59a4c9305c77bbfad7e4cdb2b9cffa
Gerrit-Change-Number: 67231
Gerrit-PatchSet: 1
Gerrit-Owner: Hanhwi Jang
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: gpu-compute, mem-ruby: Add p_popRequestQueue to some transitions
VISHNU RAMADAS has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67192?usp=email )
Change subject: gpu-compute, mem-ruby: Add p_popRequestQueue to some
transitions
..
gpu-compute, mem-ruby: Add p_popRequestQueue to some transitions
Two W->WI transitions, on events RdBlk and Atomic in the GPU L2 cache
coherence protocol do not clear the request from the request queue upon
completing the transition. This action is not performed in the respone
path. This update adds the p_popRequestQueue action to each of these
transitions to remove the stale request from the queue.
Change-Id: Ia2679fe3dd702f4df2bc114f4607ba40c18d6ff1
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 17 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index 56a04e6..cd73da4 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -722,6 +722,7 @@
p_profileHit;
t_allocateTBE;
wb_writeBack;
+p_popRequestQueue;
}
transition(I, RdBlk, IV) {TagArrayRead} {
@@ -816,6 +817,7 @@
p_profileHit;
t_allocateTBE;
wb_writeBack;
+p_popRequestQueue;
}
transition(I, WrVicBlk) {TagArrayRead} {
--
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Gerrit-Change-Id: Ia2679fe3dd702f4df2bc114f4607ba40c18d6ff1
Gerrit-Change-Number: 67192
Gerrit-PatchSet: 1
Gerrit-Owner: VISHNU RAMADAS
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: gpu-compute, mem-ruby: Update GPU cache bypassing to use TBE
-636,8 +624,6 @@
out_msg.Type := MemoryRequestType:MEMORY_READ;
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Request_Control;
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
}
}
}
@@ -753,8 +739,6 @@
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Destination := probe_dests;
tbe.NumPendingAcks := out_msg.Destination.count();
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
DPRINTF(RubySlicc, "%s\n", out_msg);
APPEND_TRANSITION_COMMENT(" dc: Acks remaining: ");
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
@@ -858,8 +842,6 @@
out_msg.ReturnData := true;
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Destination := probe_dests;
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
tbe.NumPendingAcks := out_msg.Destination.count();
DPRINTF(RubySlicc, "%s\n", (out_msg));
APPEND_TRANSITION_COMMENT(" sc: Acks remaining: ");
@@ -915,8 +897,6 @@
out_msg.ReturnData := false;
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Destination := probe_dests;
- out_msg.isGLCSet := in_msg.isGLCSet;
- out_msg.isSLCSet := in_msg.isSLCSet;
tbe.NumPendingAcks := out_msg.Destination.count();
APPEND_TRANSITION_COMMENT(" ic: Acks remaining: ");
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
@@ -943,8 +923,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := in_msg.DataBlk;
-out_msg.isGLCSet := in_msg.isGLCSet;
-out_msg.isSLCSet := in_msg.isSLCSet;
}
if (tbe.Dirty == false) {
// have to update the TBE, too, because of how this
@@ -1007,8 +985,6 @@
tbe.NumPendingAcks := 0;
tbe.Cached := in_msg.ForceShared;
tbe.InitialRequestTime := in_msg.InitialRequestTime;
- tbe.isGLCSet := in_msg.isGLCSet;
- tbe.isSLCSet := in_msg.isSLCSet;
}
}
@@ -1028,8 +1004,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := tbe.DataBlk;
-out_msg.isGLCSet := tbe.isGLCSet;
-out_msg.isSLCSet := tbe.isSLCSet;
DPRINTF(ProtocolTrace, "%s\n", out_msg);
}
}
@@ -1130,8 +1104,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := victim_entry.DataBlk;
-out_msg.isGLCSet := in_msg.isGLCSet;
-out_msg.isSLCSet := in_msg.isSLCSet;
}
L3CacheMemory.deallocate(victim);
}
@@ -1164,8 +1136,6 @@
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := victim_entry.DataBlk;
-out_msg.isGLCSet := tbe.isGLCSet;
-out_msg.isSLCSet := tbe.isSLCSet;
}
L3CacheMemory.deallocate(victim);
}
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
index 6ff19e9..bb3a013 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
@@ -168,8 +168,6 @@
MachineID Requestor, desc="Requestor id for 3-hop requests";
bool NoAckNeeded, default="false", desc="For short circuting acks";
int ProgramCounter, desc="PC that accesses to this block";
- bool isGLCSet,desc="Bypass L1 Cache";
- bool isSLCSet,desc="Bypass L1 and L2 Caches";
bool functionalRead(Packet *pkt) {
return false;
--
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Gerrit-Change-Number: 67191
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Gerrit-Owner: VISHNU RAMADAS
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[gem5-dev] [S] Change in gem5/gem5[develop]: ext-testlib: Support str-convertible args in gem5_verify_config
Gabriel B. has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66893?usp=email )
Change subject: ext-testlib: Support str-convertible args in
gem5_verify_config
..
ext-testlib: Support str-convertible args in gem5_verify_config
gem5_verify_config dit not support string-convertible args due to log_call()
not trying to call str() on them. This patch maps str() on the command
paramters.
It is now possible to pass native integers or even string-like types like
pathlib.Path as arguments without manually converting them to string.
Change-Id: Ifa987f5f1a20f17c8710e1a36d99d424e4c9ce6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66893
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M ext/testlib/helper.py
1 file changed, 28 insertions(+), 1 deletion(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/testlib/helper.py b/ext/testlib/helper.py
index ed6e325..ea102f2 100644
--- a/ext/testlib/helper.py
+++ b/ext/testlib/helper.py
@@ -149,7 +149,14 @@
if isinstance(command, str):
cmdstr = command
else:
-cmdstr = ' '.join(command)
+try:
+command = list(map(str, command))
+cmdstr = " ".join(command)
+except TypeError as e:
+logger.trace(
+"Argument must be an iterable of
string-convertible types"
+)
+raise e
logger_callback = logger.trace
logger.trace('Logging call to command: %s' % cmdstr)
--
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Gerrit-Change-Id: Ifa987f5f1a20f17c8710e1a36d99d424e4c9ce6c
Gerrit-Change-Number: 66893
Gerrit-PatchSet: 2
Gerrit-Owner: Gabriel B.
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabriel B.
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: ext-testlib: Improve error reporting when test definition fails
Gabriel B. has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66892?usp=email )
Change subject: ext-testlib: Improve error reporting when test definition
fails
..
ext-testlib: Improve error reporting when test definition fails
The error reason is now reported as an element in the XML testing result
summary.
Change-Id: I18b84422bb9580709cf1c5f2a14a5cbb0caf1876
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66892
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M ext/testlib/result.py
1 file changed, 37 insertions(+), 10 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/testlib/result.py b/ext/testlib/result.py
index 5c60342..786febd 100644
--- a/ext/testlib/result.py
+++ b/ext/testlib/result.py
@@ -191,17 +191,23 @@
def begin(self, file_):
file_.write('<')
file_.write(self.name)
-for attr in self.attributes:
-file_.write(' ')
-attr.write(file_)
+if hasattr(self, 'attributes'):
+for attr in self.attributes:
+file_.write(' ')
+attr.write(file_)
file_.write('>')
self.body(file_)
def body(self, file_):
-for elem in self.elements:
-file_.write('\n')
-elem.write(file_)
+if hasattr(self, 'elements'):
+for elem in self.elements:
+file_.write('\n')
+elem.write(file_)
+if hasattr(self, 'content'):
+file_.write('\n')
+file_.write(
+xml.sax.saxutils.escape(self.content))
file_.write('\n')
def end(self, file_):
@@ -286,17 +292,22 @@
]
if str(test_result.result) == 'Failed':
-self.elements.append(JUnitFailure('Test failed', 'ERROR'))
+self.elements.append(JUnitFailure(
+'Test failed',
+str(test_result.result.reason))
+)
class JUnitFailure(XMLElement):
name = 'failure'
-def __init__(self, message, fail_type):
+def __init__(self, message, cause):
self.attributes = [
XMLAttribute('message', message),
-XMLAttribute('type', fail_type),
]
-self.elements = []
+cause_element = XMLElement()
+cause_element.name = 'cause'
+cause_element.content = cause
+self.elements = [cause_element]
class LargeFileElement(XMLElement):
--
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Gerrit-Change-Id: I18b84422bb9580709cf1c5f2a14a5cbb0caf1876
Gerrit-Change-Number: 66892
Gerrit-PatchSet: 2
Gerrit-Owner: Gabriel B.
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabriel B.
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy
erminology.
@@ -86,9 +86,14 @@
self.to_l2_latency = 1
self.version = self.versionCount()
-self._cache_line_size = cache_line_size
self.connectQueues(network)
+def getBlockSizeBits(self, cache_line_size):
+bits = int(math.log(cache_line_size, 2))
+if 2**bits != cache_line_size:
+raise Exception("Cache line size is not a power of 2!")
+return bits
+
def connectQueues(self, network):
self.mandatoryQueue = MessageBuffer()
self.optionalQueue = MessageBuffer()
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
index 6d46d1f..0a93d9b 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
@@ -54,7 +54,7 @@
self.L2cache = RubyCache(
size=l3_size,
assoc=l3_assoc,
-start_index_bit=self.getIndexBit(num_l3Caches),
+start_index_bit=self.getIndexBit(num_l3Caches,
cache_line_size),
)
self.transitions_per_cycle = 4
@@ -64,12 +64,11 @@
self.to_l1_latency = 1
self.version = self.versionCount()
-self._cache_line_size = cache_line_size
self.connectQueues(network)
-def getIndexBit(self, num_l3caches):
-l3_bits = int(math.log(num_l3caches, 2))
-bits = int(math.log(self._cache_line_size, 2)) + l3_bits
+def getIndexBit(self, num_l3Caches, cache_line_size):
+l3_bits = int(math.log(num_l3Caches, 2))
+bits = int(math.log(cache_line_size, 2)) + l3_bits
return bits
def connectQueues(self, network):
--
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Gerrit-PatchSet: 5
Gerrit-Owner: Hoa Nguyen
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Fix signed BFE instructions
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66751?usp=email )
Change subject: arch-vega: Fix signed BFE instructions
..
arch-vega: Fix signed BFE instructions
The bitfield extract instructions come in unsigned and signed variants.
The documentation on this is not correct, however the GCN3 documentation
gives some clues. The instruction should extract an N-bit integer where
N is defined in a source operand starting at some bit also defined by a
source operand. For signed variants of this instruction, the N-bit
integer should be sign extended but is currently not.
This changeset does sign extension using the runtime value of N by ORing
the upper bits with ones if the most significant bit is one. This was
verified by writing these instructions in assembly and running on a real
GPU. Changes are made to v_bfe_i32, s_bfe_i32, and s_bfe_i64.
Change-Id: Ia192f5940200c6de48867b02f709a7f1b2daa974
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66751
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
1 file changed, 55 insertions(+), 0 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index f5b08b7..c9e57bc 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -1302,6 +1302,21 @@
sdst = (src0.rawData() >> bits(src1.rawData(), 4, 0))
& ((1 << bits(src1.rawData(), 22, 16)) - 1);
+
+// Above extracted a signed int of size src1[22:16] bits which
needs
+// to be signed-extended. Check if the MSB of our src1[22:16]-bit
+// integer is 1, and sign extend it is.
+//
+// Note: The description in the Vega ISA manual does not mention to
+// sign-extend the result. An update description can be found in
the
+// more recent RDNA3 manual here:
+// https://developer.amd.com/wp-content/resources/
+// RDNA3_Shader_ISA_December2022.pdf
+if (sdst.rawData() >> (bits(src1.rawData(), 22, 16) - 1)) {
+sdst = sdst.rawData()
+ | (0x << bits(src1.rawData(), 22, 16));
+}
+
scc = sdst.rawData() ? 1 : 0;
sdst.write();
@@ -1373,6 +1388,14 @@
sdst = (src0.rawData() >> bits(src1.rawData(), 5, 0))
& ((1 << bits(src1.rawData(), 22, 16)) - 1);
+
+// Above extracted a signed int of size src1[22:16] bits which
needs
+// to be signed-extended. Check if the MSB of our src1[22:16]-bit
+// integer is 1, and sign extend it is.
+if (sdst.rawData() >> (bits(src1.rawData(), 22, 16) - 1)) {
+sdst = sdst.rawData()
+ | 0x << bits(src1.rawData(), 22, 16);
+}
scc = sdst.rawData() ? 1 : 0;
sdst.write();
@@ -30544,6 +30567,13 @@
if (wf->execMask(lane)) {
vdst[lane] = (src0[lane] >> bits(src1[lane], 4, 0))
& ((1 << bits(src2[lane], 4, 0)) - 1);
+
+// Above extracted a signed int of size src2 bits which
needs
+// to be signed-extended. Check if the MSB of our src2-bit
+// integer is 1, and sign extend it is.
+if (vdst[lane] >> (bits(src2[lane], 4, 0) - 1)) {
+vdst[lane] |= 0x << bits(src2[lane], 4, 0);
+}
}
}
--
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Gerrit-Change-Id: Ia192f5940200c6de48867b02f709a7f1b2daa974
Gerrit-Change-Number: 66751
Gerrit-PatchSet: 4
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Fix several issues with DPP
&& (currVal < NumVecElemPerVecReg)) {
-newLane += count;
+newLane -= 1;
} else {
outOfBounds = true;
}
} else if (dppCtrl == SQ_DPP_WF_RR1) { // DPP_WF_RR1
-count = -1;
-newLane = (currLane + count + NumVecElemPerVecReg) %
+newLane = (currLane - 1 + NumVecElemPerVecReg) %
NumVecElemPerVecReg;
} else if (dppCtrl == SQ_DPP_ROW_MIRROR) { // DPP_ROW_MIRROR
localRowOffset = (15 - localRowOffset);
@@ -392,12 +389,22 @@
} else if (dppCtrl == SQ_DPP_ROW_BCAST15) { // DPP_ROW_BCAST15
count = 15;
if (currLane > count) {
-newLane = (currLane & ~count) - 1;
+// 0x30 selects which set of 16 lanes to use. We broadcast
the
+// last lane of one set to all lanes of the next set (e.g.,
+// lane 15 is written to 16-31, 31 to 32-47, 47 to 48-63).
+newLane = (currLane & 0x30) - 1;
+} else {
+outOfBounds = true;
}
} else if (dppCtrl == SQ_DPP_ROW_BCAST31) { // DPP_ROW_BCAST31
count = 31;
if (currLane > count) {
-newLane = (currLane & ~count) - 1;
+// 0x20 selects either the upper 32 or lower 32 lanes and
+// broadcasts the last lane of one set to all lanes of the
+// next set (e.g., lane 31 is written to 32-63).
+newLane = (currLane & 0x20) - 1;
+} else {
+outOfBounds = true;
}
} else {
panic("Unimplemented DPP control operation: %d\n", dppCtrl);
@@ -443,6 +450,9 @@
src0.absModifier();
}
+// Need a copy of the original data since we update one lane at a
time
+T src0_copy = src0;
+
// iterate over all register lanes, performing steps 2-4
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
threadValid = (0x1LL << lane);
@@ -458,7 +468,6 @@
if (((rowMask & (0x1 << rowNum)) == 0) /* row mask */ ||
((bankMask & (0x1 << bankNum)) == 0) /* bank mask */) {
laneDisabled = true;
-continue;
}
/**
@@ -495,7 +504,7 @@
} else {
threadValid = 0;
}
-} else if (!gpuDynInst->exec_mask[lane]) {
+} else if (!gpuDynInst->wavefront()->execMask(lane)) {
if (boundCtrl == 1) {
zeroSrc = true;
} else {
@@ -505,13 +514,15 @@
if (threadValid != 0 && !outOfBounds && !zeroSrc) {
assert(!laneDisabled);
-src0[outLane] = src0[lane];
+src0[lane] = src0_copy[outLane];
} else if (zeroSrc) {
src0[lane] = 0;
}
// reset for next iteration
laneDisabled = false;
+outOfBounds = false;
+zeroSrc = false;
}
}
--
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Gerrit-Change-Number: 66752
Gerrit-PatchSet: 5
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-vega: Add missing operand size for ds_write2st64_b64
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67071?usp=email )
Change subject: arch-vega: Add missing operand size for ds_write2st64_b64
..
arch-vega: Add missing operand size for ds_write2st64_b64
This instruction takes three operands (address, and two datas) but there
were only operand sizes for two operands tripping assert in default
case.
Change-Id: I3f505b6432aee5f3f265acac46b83c0c7daff3e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67071
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.hh
1 file changed, 20 insertions(+), 1 deletion(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 0671df8..1c42248 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33553,7 +33553,9 @@
switch (opIdx) {
case 0: //vgpr_a
return 4;
- case 1: //vgpr_d1
+ case 1: //vgpr_d0
+return 8;
+ case 2: //vgpr_d1
return 8;
default:
fatal("op idx %i out of bounds\n", opIdx);
--
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Gerrit-PatchSet: 3
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Gerrit-Reviewer: Matthew Poremba
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_u32 atomic
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67072?usp=email )
Change subject: arch-vega: Implement ds_add_u32 atomic
..
arch-vega: Implement ds_add_u32 atomic
This instruction does an atomic add of unsigned 32-bit data with a VGPR
and value in LDS atomically, without return.
Change-Id: I87579a94f6200a9a066f8f7390e57fb5fb6eff8e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67072
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 64 insertions(+), 3 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 1f37ff1..afdfde3 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34071,6 +34071,10 @@
Inst_DS__DS_ADD_U32::Inst_DS__DS_ADD_U32(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u32")
{
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U32
Inst_DS__DS_ADD_U32::~Inst_DS__DS_ADD_U32()
@@ -34079,14 +34083,53 @@
// --- description from .arch file ---
// 32b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA;
-// RETURN_DATA = tmp.
void
Inst_DS__DS_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU32 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_U32::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_U32::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_SUB_U32 class methods ---
Inst_DS__DS_SUB_U32::Inst_DS__DS_SUB_U32(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 1c42248..33be33e 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31211,6 +31211,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U32
--
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Gerrit-Change-Id: I87579a94f6200a9a066f8f7390e57fb5fb6eff8e
Gerrit-Change-Number: 67072
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
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Gerrit-Reviewer: kokoro
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Add DPP support for V_AND_B32
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66753?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-vega: Add DPP support for V_AND_B32
..
arch-vega: Add DPP support for V_AND_B32
A DPP variant of V_AND_B32 was found in rocPRIM. With this changeset the
unit tests for rocPRIM scan_inclusive are passing.
Change-Id: I5a65f2cf6b56ac13609b191e3b3dfeb55e630942
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66753
Tested-by: kokoro
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
1 file changed, 46 insertions(+), 4 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index c9e57bc..1f37ff1 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -6844,15 +6844,41 @@
{
Wavefront *wf = gpuDynInst->wavefront();
ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
-ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+VecOperandU32 src1(gpuDynInst, instData.VSRC1);
VecOperandU32 vdst(gpuDynInst, instData.VDST);
src0.readSrc();
src1.read();
-for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
-if (wf->execMask(lane)) {
-vdst[lane] = src0[lane] & src1[lane];
+if (isDPPInst()) {
+VecOperandU32 src0_dpp(gpuDynInst, extData.iFmt_VOP_DPP.SRC0);
+src0_dpp.read();
+
+DPRINTF(VEGA, "Handling V_AND_B32 SRC DPP. SRC0: register
v[%d], "
+"DPP_CTRL: 0x%#x, SRC0_ABS: %d, SRC0_NEG: %d, "
+"SRC1_ABS: %d, SRC1_NEG: %d, BC: %d, "
+"BANK_MASK: %d, ROW_MASK: %d\n",
extData.iFmt_VOP_DPP.SRC0,
+extData.iFmt_VOP_DPP.DPP_CTRL,
+extData.iFmt_VOP_DPP.SRC0_ABS,
+extData.iFmt_VOP_DPP.SRC0_NEG,
+extData.iFmt_VOP_DPP.SRC1_ABS,
+extData.iFmt_VOP_DPP.SRC1_NEG,
+extData.iFmt_VOP_DPP.BC,
+extData.iFmt_VOP_DPP.BANK_MASK,
+extData.iFmt_VOP_DPP.ROW_MASK);
+
+processDPP(gpuDynInst, extData.iFmt_VOP_DPP, src0_dpp, src1);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = src0_dpp[lane] & src1[lane];
+}
+}
+} else {
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = src0[lane] & src1[lane];
+}
}
}
--
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Gerrit-Change-Id: I5a65f2cf6b56ac13609b191e3b3dfeb55e630942
Gerrit-Change-Number: 66753
Gerrit-PatchSet: 5
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Re-add -Werror for gem5 develop branch
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67052?usp=email )
Change subject: scons: Re-add -Werror for gem5 develop branch
..
scons: Re-add -Werror for gem5 develop branch
This is removed from the stable branch to avoid build errors but should
included on the develop branch to aid developers.
This reverts commit 7dd61c865975862b099e1af5e867083ac9307d9b.
Change-Id: I1fe249ce87aa8d70c1f092fc7db1554e6aee7355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67052
Tested-by: kokoro
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
---
M SConstruct
1 file changed, 26 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index e8107ea..bd26e45 100755
--- a/SConstruct
+++ b/SConstruct
@@ -420,6 +420,14 @@
conf.CheckLinkFlag('-Wl,--threads')
conf.CheckLinkFlag(
'-Wl,--thread-count=%d' %
GetOption('num_jobs'))
+
+# Treat warnings as errors but white list some warnings that we
+# want to allow (e.g., deprecation warnings).
+env.Append(CCFLAGS=['-Werror',
+ '-Wno-error=deprecated-declarations',
+ '-Wno-error=deprecated',
+])
+
else:
error('\n'.join((
"Don't know what compiler options to use for your compiler.",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1fe249ce87aa8d70c1f092fc7db1554e6aee7355
Gerrit-Change-Number: 67052
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Update version info for develop branch
context: ubuntu-18.04_clang-version dockerfile: Dockerfile args: - version=9 -image: gcr.io/gem5-test/clang-version-9:v22-1 +image: gcr.io/gem5-test/clang-version-9:latest clang-10: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=10 -image: gcr.io/gem5-test/clang-version-10:v22-1 +image: gcr.io/gem5-test/clang-version-10:latest clang-11: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=11 -image: gcr.io/gem5-test/clang-version-11:v22-1 +image: gcr.io/gem5-test/clang-version-11:latest clang-12: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=12 -image: gcr.io/gem5-test/clang-version-12:v22-1 +image: gcr.io/gem5-test/clang-version-12:latest clang-13: build: context: ubuntu-22.04_clang-version dockerfile: Dockerfile args: - version=13 -image: gcr.io/gem5-test/clang-version-13:v22-1 +image: gcr.io/gem5-test/clang-version-13:latest clang-14: build: context: ubuntu-22.04_clang-version dockerfile: Dockerfile args: - version=14 -image: gcr.io/gem5-test/clang-version-14:v22-1 +image: gcr.io/gem5-test/clang-version-14:latest llvm-gnu-cross-compiler-riscv64: build: context: llvm-gnu-cross-compiler-riscv64 dockerfile: Dockerfile -image: gcr.io/gem5-test/llvm-gnu-cross-compiler-riscv64:v22-1 +image: gcr.io/gem5-test/llvm-gnu-cross-compiler-riscv64:latest gem5-all-min-dependencies: build: context: gem5-all-min-dependencies dockerfile: Dockerfile -image: gcr.io/gem5-test/gem5-all-min-dependencies:v22-1 +image: gcr.io/gem5-test/gem5-all-min-dependencies:latest diff --git a/util/dockerfiles/gcn-gpu/Dockerfile b/util/dockerfiles/gcn-gpu/Dockerfile index dfff455..c5db896 100644 --- a/util/dockerfiles/gcn-gpu/Dockerfile +++ b/util/dockerfiles/gcn-gpu/Dockerfile @@ -69,7 +69,7 @@ WORKDIR /ROCclr # The patch allows us to avoid building blit kernels on-the-fly in gem5 -RUN wget -q -O - dist.gem5.org/dist/v22-1/rocm_patches/ROCclr.patch | git apply -v +RUN wget -q -O - dist.gem5.org/dist/develop/rocm_patches/ROCclr.patch | git apply -v WORKDIR /ROCclr/build RUN cmake -DOPENCL_DIR="/ROCm-OpenCL-Runtime" \ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67053?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icd409acda0e88852938b2af9f170e2a410e91f8c Gerrit-Change-Number: 67053 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby Bruce Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Merge branch stable into develop branch
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67051?usp=email )
Change subject: misc: Merge branch stable into develop branch
..
misc: Merge branch stable into develop branch
This ensures both branches are in-sync and have not diverged.
Change-Id: Ib487d8596037017b9ec03d7e8a76229373c153db
---
M src/dev/amdgpu/pm4_packet_processor.cc
M src/dev/amdgpu/sdma_engine.cc
M src/dev/amdgpu/sdma_engine.hh
4 files changed, 60 insertions(+), 34 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/amdgpu/pm4_packet_processor.cc
b/src/dev/amdgpu/pm4_packet_processor.cc
index 3c832c5..152fd4d 100644
--- a/src/dev/amdgpu/pm4_packet_processor.cc
+++ b/src/dev/amdgpu/pm4_packet_processor.cc
@@ -458,13 +458,7 @@
SDMAEngine *sdma_eng = gpuDevice->getSDMAById(pkt->engineSel - 2);
// Register RLC queue with SDMA
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2, addr, mqd);
-===
-sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2,
- mqd->rb_base << 8, rlc_size,
- rptr_wb_addr);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
// Register doorbell with GPU device
gpuDevice->setSDMAEngine(pkt->doorbellOffset << 2, sdma_eng);
diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc
index 0a167bf..4c03bf5 100644
--- a/src/dev/amdgpu/sdma_engine.cc
+++ b/src/dev/amdgpu/sdma_engine.cc
@@ -165,12 +165,7 @@
}
void
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
SDMAEngine::registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc
*mqd)
-===
-SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size,
- Addr rptr_wb_addr)
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
{
uint32_t rlc_size = 4UL << bits(mqd->sdmax_rlcx_rb_cntl, 6, 1);
Addr rptr_wb_addr = mqd->sdmax_rlcx_rb_rptr_addr_hi;
@@ -185,43 +180,25 @@
rlc0.base(mqd->rb_base << 8);
rlc0.size(rlc_size);
rlc0.rptr(0);
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc0.incRptr(mqd->rptr);
rlc0.setWptr(mqd->wptr);
-===
-rlc0.wptr(0);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
rlc0.rptrWbAddr(rptr_wb_addr);
rlc0.processing(false);
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc0.setMQD(mqd);
rlc0.setMQDAddr(mqdAddr);
-===
-rlc0.size(size);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
} else if (!rlc1.valid()) {
DPRINTF(SDMAEngine, "Doorbell %lx mapped to RLC1\n", doorbell);
rlcInfo[1] = doorbell;
rlc1.valid(true);
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc1.base(mqd->rb_base << 8);
rlc1.size(rlc_size);
rlc1.rptr(0);
rlc1.incRptr(mqd->rptr);
rlc1.setWptr(mqd->wptr);
-===
-rlc1.base(rb_base);
-rlc1.rptr(0);
-rlc1.wptr(0);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
rlc1.rptrWbAddr(rptr_wb_addr);
rlc1.processing(false);
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc1.setMQD(mqd);
rlc1.setMQDAddr(mqdAddr);
-===
-rlc1.size(size);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
} else {
panic("No free RLCs. Check they are properly unmapped.");
}
diff --git a/src/dev/amdgpu/sdma_engine.hh b/src/dev/amdgpu/sdma_engine.hh
index 6a12f97..27c1691 100644
--- a/src/dev/amdgpu/sdma_engine.hh
+++ b/src/dev/amdgpu/sdma_engine.hh
@@ -287,12 +287,7 @@
/**
* Methods for RLC queues
*/
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
void registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc *mqd);
-===
-void registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size,
- Addr rptr_wb_addr);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release
[gem5-dev] [L] Change in gem5/gem5[develop]: gpu-compute,mem-ruby: Add support for GPU cache bypassing
;Bypass L1 Cache";
+ bool isSLCSet,desc="Bypass L1 and L2 Caches";
bool functionalRead(Packet *pkt) {
if ((MessageSize == MessageSizeType:Response_Data) ||
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 8d76f78..8ba9d93 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -177,6 +177,8 @@
int htmTransactionUid, desc="Used to identify the unique HTM
transaction that produced this request";
bool isTlbi, desc="Memory request is a TLB shootdown
(invalidation) operation";
Addr tlbiTransactionUid, desc="Unique identifier of the TLB shootdown
operation that produced this request";
+ bool isGLCSet, default="false",desc="If flag is set, bypass
GPU L1 cache";
+ bool isSLCSet, default="false",desc="If flag is set, bypass
GPU L1 and L2 caches";
RequestPtr getRequestPtr();
}
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh
b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 2345c22..89ce834 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -79,6 +79,11 @@
bool m_isTlbi;
// Should be uint64, but SLICC complains about casts
Addr m_tlbiTransactionUid;
+// GPU cache bypass flags. GLC bypasses L1 while SLC bypasses both L1
and
+// L2 if set to true. They are set to false by default and they must be
+// explicitly set to true in the program in order to bypass caches
+bool m_isGLCSet;
+bool m_isSLCSet;
RubyRequest(Tick curTime, uint64_t _paddr, int _len,
uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode,
@@ -99,6 +104,13 @@
m_tlbiTransactionUid(0)
{
m_LineAddress = makeLineAddress(m_PhysicalAddress);
+if (_pkt) {
+m_isGLCSet = m_pkt->req->isGLCSet();
+m_isSLCSet = m_pkt->req->isSLCSet();
+} else {
+m_isGLCSet = 0;
+m_isSLCSet = 0;
+}
}
/** RubyRequest for memory management commands */
@@ -120,6 +132,13 @@
m_tlbiTransactionUid(0)
{
assert(m_pkt->req->isMemMgmt());
+if (_pkt) {
+m_isGLCSet = m_pkt->req->isGLCSet();
+m_isSLCSet = m_pkt->req->isSLCSet();
+} else {
+m_isGLCSet = 0;
+m_isSLCSet = 0;
+}
}
RubyRequest(Tick curTime, uint64_t _paddr, int _len,
@@ -148,6 +167,13 @@
m_tlbiTransactionUid(0)
{
m_LineAddress = makeLineAddress(m_PhysicalAddress);
+if (_pkt) {
+m_isGLCSet = m_pkt->req->isGLCSet();
+ m_isSLCSet = m_pkt->req->isSLCSet();
+} else {
+ m_isGLCSet = 0;
+ m_isSLCSet = 0;
+ }
}
RubyRequest(Tick curTime, uint64_t _paddr, int _len,
@@ -177,6 +203,14 @@
m_tlbiTransactionUid(0)
{
m_LineAddress = makeLineAddress(m_PhysicalAddress);
+if (_pkt) {
+m_isGLCSet = m_pkt->req->isGLCSet();
+m_isSLCSet = m_pkt->req->isSLCSet();
+
+} else {
+m_isGLCSet = 0;
+m_isSLCSet = 0;
+}
}
RubyRequest(Tick curTime) : Message(curTime) {}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id29a47b0fa7e16a21a7718949db802f85e9897c3
Gerrit-Change-Number: 66991
Gerrit-PatchSet: 9
Gerrit-Owner: VISHNU RAMADAS
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: VISHNU RAMADAS
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: ext-testlib: Improve error reporting when test definition fails
Gabriel B. has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66892?usp=email )
Change subject: ext-testlib: Improve error reporting when test definition
fails
..
ext-testlib: Improve error reporting when test definition fails
The error reason is now reported as an element in the XML testing result
summary.
Change-Id: I18b84422bb9580709cf1c5f2a14a5cbb0caf1876
---
M ext/testlib/result.py
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/ext/testlib/result.py b/ext/testlib/result.py
index 5c60342..786febd 100644
--- a/ext/testlib/result.py
+++ b/ext/testlib/result.py
@@ -191,17 +191,23 @@
def begin(self, file_):
file_.write('<')
file_.write(self.name)
-for attr in self.attributes:
-file_.write(' ')
-attr.write(file_)
+if hasattr(self, 'attributes'):
+for attr in self.attributes:
+file_.write(' ')
+attr.write(file_)
file_.write('>')
self.body(file_)
def body(self, file_):
-for elem in self.elements:
-file_.write('\n')
-elem.write(file_)
+if hasattr(self, 'elements'):
+for elem in self.elements:
+file_.write('\n')
+elem.write(file_)
+if hasattr(self, 'content'):
+file_.write('\n')
+file_.write(
+xml.sax.saxutils.escape(self.content))
file_.write('\n')
def end(self, file_):
@@ -286,17 +292,22 @@
]
if str(test_result.result) == 'Failed':
-self.elements.append(JUnitFailure('Test failed', 'ERROR'))
+self.elements.append(JUnitFailure(
+'Test failed',
+str(test_result.result.reason))
+)
class JUnitFailure(XMLElement):
name = 'failure'
-def __init__(self, message, fail_type):
+def __init__(self, message, cause):
self.attributes = [
XMLAttribute('message', message),
-XMLAttribute('type', fail_type),
]
-self.elements = []
+cause_element = XMLElement()
+cause_element.name = 'cause'
+cause_element.content = cause
+self.elements = [cause_element]
class LargeFileElement(XMLElement):
--
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Gerrit-Owner: Gabriel B.
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[gem5-dev] [S] Change in gem5/gem5[develop]: ext-testlib: Support str-convertible args in gem5_verify_config
Gabriel B. has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66893?usp=email )
Change subject: ext-testlib: Support str-convertible args in
gem5_verify_config
..
ext-testlib: Support str-convertible args in gem5_verify_config
gem5_verify_config dit not support string-convertible args due to log_call()
not trying to call str() on them. This patch maps str() on the command
paramters.
It is now possible to pass native integers or even string-like types like
pathlib.Path as arguments without manually converting them to string.
Change-Id: Ifa987f5f1a20f17c8710e1a36d99d424e4c9ce6c
---
M ext/testlib/helper.py
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/ext/testlib/helper.py b/ext/testlib/helper.py
index ed6e325..ea102f2 100644
--- a/ext/testlib/helper.py
+++ b/ext/testlib/helper.py
@@ -149,7 +149,14 @@
if isinstance(command, str):
cmdstr = command
else:
-cmdstr = ' '.join(command)
+try:
+command = list(map(str, command))
+cmdstr = " ".join(command)
+except TypeError as e:
+logger.trace(
+"Argument must be an iterable of
string-convertible types"
+)
+raise e
logger_callback = logger.trace
logger.trace('Logging call to command: %s' % cmdstr)
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: base: Remove unused output.hh dependency from trace.cc
Rocky Tatiefo has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67011?usp=email ) Change subject: base: Remove unused output.hh dependency from trace.cc .. base: Remove unused output.hh dependency from trace.cc Change-Id: Ie80ad5f3fb9fc7ee1e35f0624317e0e58cbf152d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67011 Maintainer: Bobby Bruce Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M src/base/trace.cc 1 file changed, 13 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass Bobby Bruce: Looks good to me, approved diff --git a/src/base/trace.cc b/src/base/trace.cc index 52faa8d..272b035 100644 --- a/src/base/trace.cc +++ b/src/base/trace.cc @@ -38,7 +38,6 @@ #include "base/atomicio.hh" #include "base/logging.hh" -#include "base/output.hh" #include "base/str.hh" #include "debug/FmtFlag.hh" #include "debug/FmtStackTrace.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67011?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie80ad5f3fb9fc7ee1e35f0624317e0e58cbf152d Gerrit-Change-Number: 67011 Gerrit-PatchSet: 2 Gerrit-Owner: Rocky Tatiefo Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Rocky Tatiefo Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: add RV32 ADFIMU_Zfh instruction tests
),
+("rv{}ui-ps-lhu", (32, 64)),
+("rv{}ui-ps-lui", (32, 64)),
+("rv{}ui-ps-lw", (32, 64)),
+("rv{}ui-ps-lwu", (64,)),
+("rv{}ui-ps-or", (32, 64)),
+("rv{}ui-ps-ori", (32, 64)),
+("rv{}ui-ps-sb", (32, 64)),
+("rv{}ui-ps-sd", (64,)),
+("rv{}ui-ps-sh", (32, 64)),
+("rv{}ui-ps-simple", (32, 64)),
+("rv{}ui-ps-sll", (32, 64)),
+("rv{}ui-ps-slli", (32, 64)),
+("rv{}ui-ps-slliw", (64,)),
+("rv{}ui-ps-sllw", (64,)),
+("rv{}ui-ps-slt", (32, 64)),
+("rv{}ui-ps-slti", (32, 64)),
+("rv{}ui-ps-sltiu", (32, 64)),
+("rv{}ui-ps-sltu", (32, 64)),
+("rv{}ui-ps-sra", (32, 64)),
+("rv{}ui-ps-srai", (32, 64)),
+("rv{}ui-ps-sraiw", (64,)),
+("rv{}ui-ps-sraw", (64,)),
+("rv{}ui-ps-srl", (32, 64)),
+("rv{}ui-ps-srli", (32, 64)),
+("rv{}ui-ps-srliw", (64,)),
+("rv{}ui-ps-srlw", (64,)),
+("rv{}ui-ps-sub", (32, 64)),
+("rv{}ui-ps-subw", (64,)),
+("rv{}ui-ps-sw", (32, 64)),
+("rv{}ui-ps-xor", (32, 64)),
+("rv{}ui-ps-xori", (32, 64)),
+("rv{}um-ps-div", (32, 64)),
+("rv{}um-ps-divu", (32, 64)),
+("rv{}um-ps-divuw", (64,)),
+("rv{}um-ps-divw", (64,)),
+("rv{}um-ps-mul", (32, 64)),
+("rv{}um-ps-mulh", (32, 64)),
+("rv{}um-ps-mulhsu", (32, 64)),
+("rv{}um-ps-mulhu", (32, 64)),
+("rv{}um-ps-mulw", (64,)),
+("rv{}um-ps-rem", (32, 64)),
+("rv{}um-ps-remu", (32, 64)),
+("rv{}um-ps-remuw", (64,)),
+("rv{}um-ps-remw", (64,)),
+("rv{}uzfh-ps-fadd", (32, 64)),
+("rv{}uzfh-ps-fclass", (32, 64)),
+("rv{}uzfh-ps-fcmp", (32, 64)),
+("rv{}uzfh-ps-fcvt", (32, 64)),
+("rv{}uzfh-ps-fcvt_w", (32, 64)),
+("rv{}uzfh-ps-fdiv", (32, 64)),
+("rv{}uzfh-ps-fmadd", (32, 64)),
+("rv{}uzfh-ps-fmin", (32, 64)),
+("rv{}uzfh-ps-ldst", (32, 64)),
+("rv{}uzfh-ps-move", (32, 64)),
+("rv{}uzfh-ps-recoding", (32, 64)),
)
cpu_types = ("atomic", "timing", "minor", "o3")
for cpu_type in cpu_types:
-for binary in binaries:
-gem5_verify_config(
-name=f"asm-riscv-{binary}-{cpu_type}",
-verifiers=(),
-config=joinpath(
-config.base_dir,
-"tests",
-"gem5",
-"configs",
-"simple_binary_run.py",
-),
-config_args=[
+for cfg in binary_configs:
+template_bin, all_bits = cfg
+for bits in all_bits:
+binary = template_bin.format(bits)
+config_args = [
binary,
cpu_type,
"riscv",
@@ -191,7 +194,20 @@
"4",
"--resource-directory",
resource_path,
-],
-valid_isas=(constants.all_compiled_tag,),
-valid_hosts=constants.supported_hosts,
-)
+]
+if bits == 32:
+config_args.extend(["-b", "--riscv-32bits"])
+gem5_verify_config(
+name=f"asm-riscv-{binary}-{cpu_type}",
+verifiers=(),
+config=joinpath(
+config.base_dir,
+"tests",
+"gem5",
+"configs",
+"simple_binary_run.py",
+),
+config_args=config_args,
+valid_isas=(constants.all_compiled_tag,),
+valid_hosts=constants.supported_hosts,
+)
diff --git a/tests/gem5/configs/simple_binary_run.py
b/tests/gem5/configs/simple_binary_run.py
index d69e1a1..fbb0313 100644
--- a/tests/gem5/configs/simple_binary_run.py
+++ b/tests/gem5/configs/simple_binary_run.py
@@ -1,4 +1,5 @@
# Copyright (c) 2021 The Regents of the University of California
+# Copyright (c) 2022 Google Inc
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -44,12 +45,23 @@
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
-from gem5.isas import get_isa_from_str, get_isas_str_set
+from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
+
+from m5.util import fatal
import ar
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_write2st64_b64
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67078?usp=email )
Change subject: arch-vega: Implement ds_write2st64_b64
..
arch-vega: Implement ds_write2st64_b64
Write two qwords at offsets multiplied by 8 * 64 bytes.
Change-Id: I0d0e05f3e848c2fd02d32095e32b7f023bd8803b
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 58 insertions(+), 1 deletion(-)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 7594f9c..3ef11c4 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -36589,8 +36589,52 @@
void
Inst_DS__DS_WRITE2ST64_B64::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU64 data0(gpuDynInst, extData.DATA0);
+ConstVecOperandU64 data1(gpuDynInst, extData.DATA1);
+
+addr.read();
+data0.read();
+data1.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(
+gpuDynInst->d_data))[lane * 2] = data0[lane];
+(reinterpret_cast(
+gpuDynInst->d_data))[lane * 2 + 1] = data1[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_WRITE2ST64_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0 * 8 * 64;
+Addr offset1 = instData.OFFSET1 * 8 * 64;
+
+initDualMemWrite(gpuDynInst, offset0, offset1);
+}
+
+void
+Inst_DS__DS_WRITE2ST64_B64::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+}
// --- Inst_DS__DS_CMPST_B64 class methods ---
Inst_DS__DS_CMPST_B64::Inst_DS__DS_CMPST_B64(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 9f017f9..2896732 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33572,6 +33572,8 @@
} // getOperandSize
void execute(GPUDynInstPtr) override;
+void initiateAcc(GPUDynInstPtr) override;
+void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_WRITE2ST64_B64
class Inst_DS__DS_CMPST_B64 : public Inst_DS
--
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Gerrit-Change-Number: 67078
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Gerrit-Owner: Matthew Poremba
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Read one dword for SGPR base global insts
instData;
// second instruction DWORD
@@ -987,7 +999,7 @@
void generateGlobalDisassembly();
void
-calcAddrSgpr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 ,
+calcAddrSgpr(GPUDynInstPtr gpuDynInst, ConstVecOperandU32 ,
ConstScalarOperandU64 , ScalarRegI32 offset)
{
// Use SGPR pair as a base address and add VGPR-offset and
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-vega: Add missing operand size for ds_write2st64_b64
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67071?usp=email )
Change subject: arch-vega: Add missing operand size for ds_write2st64_b64
..
arch-vega: Add missing operand size for ds_write2st64_b64
This instruction takes three operands (address, and two datas) but there
were only operand sizes for two operands tripping assert in default
case.
Change-Id: I3f505b6432aee5f3f265acac46b83c0c7daff3e7
---
M src/arch/amdgpu/vega/insts/instructions.hh
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 0671df8..1c42248 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33553,7 +33553,9 @@
switch (opIdx) {
case 0: //vgpr_a
return 4;
- case 1: //vgpr_d1
+ case 1: //vgpr_d0
+return 8;
+ case 2: //vgpr_d1
return 8;
default:
fatal("op idx %i out of bounds\n", opIdx);
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: base: Specialize bitwise atomics so FP types can be used
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67073?usp=email )
Change subject: base: Specialize bitwise atomics so FP types can be used
..
base: Specialize bitwise atomics so FP types can be used
The current atomic memory operations are templated so any type can be
used. However floating point types can not perform bitwise operations.
The GPU model contains some instructions which do atomics on floating
point types, so they need to be supported. To allow this, template
specialization is added to atomic AND, OR, and XOR which does nothing
if the type is floating point and operates as normal for integral
types.
Change-Id: I60f935756355462e99c59a9da032c5bf5afa246c
---
M src/base/amo.hh
1 file changed, 47 insertions(+), 3 deletions(-)
diff --git a/src/base/amo.hh b/src/base/amo.hh
index 81bf069..c990d15 100644
--- a/src/base/amo.hh
+++ b/src/base/amo.hh
@@ -129,30 +129,57 @@
template
class AtomicOpAnd : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b &= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpAnd(T _a) : a(_a) { }
-void execute(T *b) { *b &= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpAnd(a); }
};
template
class AtomicOpOr : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b |= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpOr(T _a) : a(_a) { }
-void execute(T *b) { *b |= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpOr(a); }
};
template
class AtomicOpXor : public TypedAtomicOpFunctor
{
+// Bitwise operations are only legal on integral types
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { *b ^= a; }
+
+template
+typename std::enable_if::value, void>::type
+executeImpl(B *b) { }
+
public:
T a;
AtomicOpXor(T _a) : a(_a) {}
-void execute(T *b) { *b ^= a; }
+void execute(T *b) { executeImpl(b); }
AtomicOpFunctor* clone () { return new AtomicOpXor(a); }
};
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_u64
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67075?usp=email )
Change subject: arch-vega: Implement ds_add_u64
..
arch-vega: Implement ds_add_u64
This instruction does an atomic add of an unsigned 64-bit data with a
VGPR and value in LDS atomically without return.
Change-Id: I6a7d6713b256607c4e69ddbdef5c83172493c077
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index a0308c8..511a767 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -36082,6 +36082,10 @@
Inst_DS__DS_ADD_U64::Inst_DS__DS_ADD_U64(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u64")
{
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U64
Inst_DS__DS_ADD_U64::~Inst_DS__DS_ADD_U64()
@@ -36090,14 +36094,53 @@
// --- description from .arch file ---
// 64b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA[0:1];
-// RETURN_DATA[0:1] = tmp.
void
Inst_DS__DS_ADD_U64::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU64 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_U64::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_U64::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_SUB_U64 class methods ---
Inst_DS__DS_SUB_U64::Inst_DS__DS_SUB_U64(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 05a0002..f8fc98b 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33079,6 +33079,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U64
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_f32 atomic
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67074?usp=email )
Change subject: arch-vega: Implement ds_add_f32 atomic
..
arch-vega: Implement ds_add_f32 atomic
This instruction does an atomic add of a 32-bit float with a VGPR and
value in LDS atomically without return.
Change-Id: Id4f23a1ab587a23edfd1d88ede1cbcc5bdedc0cb
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 5332687..a0308c8 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34749,6 +34749,10 @@
: Inst_DS(iFmt, "ds_add_f32")
{
setFlag(F32);
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_F32
Inst_DS__DS_ADD_F32::~Inst_DS__DS_ADD_F32()
@@ -34757,15 +34761,54 @@
// --- description from .arch file ---
// 32b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA;
-// RETURN_DATA = tmp.
// Floating point add that handles NaN/INF/denormal values.
void
Inst_DS__DS_ADD_F32::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandF32 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_F32::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_F32::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_WRITE_B8 class methods ---
Inst_DS__DS_WRITE_B8::Inst_DS__DS_WRITE_B8(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 33be33e..05a0002 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31895,6 +31895,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_F32
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_u32 atomic
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67072?usp=email )
Change subject: arch-vega: Implement ds_add_u32 atomic
..
arch-vega: Implement ds_add_u32 atomic
This instruction does an atomic add of unsigned 32-bit data with a VGPR
and value in LDS atomically, without return.
Change-Id: I87579a94f6200a9a066f8f7390e57fb5fb6eff8e
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 3570e32..5332687 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34065,6 +34065,10 @@
Inst_DS__DS_ADD_U32::Inst_DS__DS_ADD_U32(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u32")
{
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U32
Inst_DS__DS_ADD_U32::~Inst_DS__DS_ADD_U32()
@@ -34073,14 +34077,53 @@
// --- description from .arch file ---
// 32b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA;
-// RETURN_DATA = tmp.
void
Inst_DS__DS_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU32 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_U32::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_U32::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_SUB_U32 class methods ---
Inst_DS__DS_SUB_U32::Inst_DS__DS_SUB_U32(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 1c42248..33be33e 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31211,6 +31211,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U32
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_read_i8
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67076?usp=email )
Change subject: arch-vega: Implement ds_read_i8
..
arch-vega: Implement ds_read_i8
Read one byte with sign extended from LDS.
Change-Id: I9cb9b4033c6f834241cba944bc7e6a7ebc5401be
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 511a767..f0fb1aa 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -35630,8 +35630,50 @@
void
Inst_DS__DS_READ_I8::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+addr.read();
+
+calcAddr(gpuDynInst, addr);
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_READ_I8::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initMemRead(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_READ_I8::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+vdst[lane] =
(VecElemU32)sext<8>((reinterpret_cast(
+gpuDynInst->d_data))[lane]);
+}
+}
+
+vdst.write();
+} // completeAcc
// --- Inst_DS__DS_READ_U8 class methods ---
Inst_DS__DS_READ_U8::Inst_DS__DS_READ_U8(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index f8fc98b..b2cf2b9 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -32848,6 +32848,8 @@
} // getOperandSize
void execute(GPUDynInstPtr) override;
+void initiateAcc(GPUDynInstPtr) override;
+void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_READ_I8
class Inst_DS__DS_READ_U8 : public Inst_DS
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Update version info for develop branch
st clang-10: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=10 -image: gcr.io/gem5-test/clang-version-10:v22-1 +image: gcr.io/gem5-test/clang-version-10:latest clang-11: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=11 -image: gcr.io/gem5-test/clang-version-11:v22-1 +image: gcr.io/gem5-test/clang-version-11:latest clang-12: build: context: ubuntu-20.04_clang-version dockerfile: Dockerfile args: - version=12 -image: gcr.io/gem5-test/clang-version-12:v22-1 +image: gcr.io/gem5-test/clang-version-12:latest clang-13: build: context: ubuntu-22.04_clang-version dockerfile: Dockerfile args: - version=13 -image: gcr.io/gem5-test/clang-version-13:v22-1 +image: gcr.io/gem5-test/clang-version-13:latest clang-14: build: context: ubuntu-22.04_clang-version dockerfile: Dockerfile args: - version=14 -image: gcr.io/gem5-test/clang-version-14:v22-1 +image: gcr.io/gem5-test/clang-version-14:latest llvm-gnu-cross-compiler-riscv64: build: context: llvm-gnu-cross-compiler-riscv64 dockerfile: Dockerfile -image: gcr.io/gem5-test/llvm-gnu-cross-compiler-riscv64:v22-1 +image: gcr.io/gem5-test/llvm-gnu-cross-compiler-riscv64:latest gem5-all-min-dependencies: build: context: gem5-all-min-dependencies dockerfile: Dockerfile -image: gcr.io/gem5-test/gem5-all-min-dependencies:v22-1 +image: gcr.io/gem5-test/gem5-all-min-dependencies:latest diff --git a/util/dockerfiles/gcn-gpu/Dockerfile b/util/dockerfiles/gcn-gpu/Dockerfile index dfff455..c5db896 100644 --- a/util/dockerfiles/gcn-gpu/Dockerfile +++ b/util/dockerfiles/gcn-gpu/Dockerfile @@ -69,7 +69,7 @@ WORKDIR /ROCclr # The patch allows us to avoid building blit kernels on-the-fly in gem5 -RUN wget -q -O - dist.gem5.org/dist/v22-1/rocm_patches/ROCclr.patch | git apply -v +RUN wget -q -O - dist.gem5.org/dist/develop/rocm_patches/ROCclr.patch | git apply -v WORKDIR /ROCclr/build RUN cmake -DOPENCL_DIR="/ROCm-OpenCL-Runtime" \ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67053?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icd409acda0e88852938b2af9f170e2a410e91f8c Gerrit-Change-Number: 67053 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Merge branch stable into develop branch
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67051?usp=email )
Change subject: misc: Merge branch stable into develop branch
..
misc: Merge branch stable into develop branch
This ensures both branches are in-sync and have not diverged.
Change-Id: Ib487d8596037017b9ec03d7e8a76229373c153db
---
M src/dev/amdgpu/pm4_packet_processor.cc
M src/dev/amdgpu/sdma_engine.cc
M src/dev/amdgpu/sdma_engine.hh
4 files changed, 60 insertions(+), 34 deletions(-)
diff --git a/src/dev/amdgpu/pm4_packet_processor.cc
b/src/dev/amdgpu/pm4_packet_processor.cc
index 3c832c5..152fd4d 100644
--- a/src/dev/amdgpu/pm4_packet_processor.cc
+++ b/src/dev/amdgpu/pm4_packet_processor.cc
@@ -458,13 +458,7 @@
SDMAEngine *sdma_eng = gpuDevice->getSDMAById(pkt->engineSel - 2);
// Register RLC queue with SDMA
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2, addr, mqd);
-===
-sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2,
- mqd->rb_base << 8, rlc_size,
- rptr_wb_addr);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
// Register doorbell with GPU device
gpuDevice->setSDMAEngine(pkt->doorbellOffset << 2, sdma_eng);
diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc
index 0a167bf..4c03bf5 100644
--- a/src/dev/amdgpu/sdma_engine.cc
+++ b/src/dev/amdgpu/sdma_engine.cc
@@ -165,12 +165,7 @@
}
void
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
SDMAEngine::registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc
*mqd)
-===
-SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size,
- Addr rptr_wb_addr)
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
{
uint32_t rlc_size = 4UL << bits(mqd->sdmax_rlcx_rb_cntl, 6, 1);
Addr rptr_wb_addr = mqd->sdmax_rlcx_rb_rptr_addr_hi;
@@ -185,43 +180,25 @@
rlc0.base(mqd->rb_base << 8);
rlc0.size(rlc_size);
rlc0.rptr(0);
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc0.incRptr(mqd->rptr);
rlc0.setWptr(mqd->wptr);
-===
-rlc0.wptr(0);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
rlc0.rptrWbAddr(rptr_wb_addr);
rlc0.processing(false);
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc0.setMQD(mqd);
rlc0.setMQDAddr(mqdAddr);
-===
-rlc0.size(size);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
} else if (!rlc1.valid()) {
DPRINTF(SDMAEngine, "Doorbell %lx mapped to RLC1\n", doorbell);
rlcInfo[1] = doorbell;
rlc1.valid(true);
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc1.base(mqd->rb_base << 8);
rlc1.size(rlc_size);
rlc1.rptr(0);
rlc1.incRptr(mqd->rptr);
rlc1.setWptr(mqd->wptr);
-===
-rlc1.base(rb_base);
-rlc1.rptr(0);
-rlc1.wptr(0);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
rlc1.rptrWbAddr(rptr_wb_addr);
rlc1.processing(false);
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc1.setMQD(mqd);
rlc1.setMQDAddr(mqdAddr);
-===
-rlc1.size(size);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
} else {
panic("No free RLCs. Check they are properly unmapped.");
}
diff --git a/src/dev/amdgpu/sdma_engine.hh b/src/dev/amdgpu/sdma_engine.hh
index 6a12f97..27c1691 100644
--- a/src/dev/amdgpu/sdma_engine.hh
+++ b/src/dev/amdgpu/sdma_engine.hh
@@ -287,12 +287,7 @@
/**
* Methods for RLC queues
*/
-<<<<<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
void registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc *mqd);
-===
-void registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size,
- Addr rptr_wb_addr);
->>>>>>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
void unregisterRLCQueue(Addr doorbell);
void deallocateRLCQueues();
--
[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Re-add -Werror for gem5 develop branch
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67052?usp=email )
Change subject: scons: Re-add -Werror for gem5 develop branch
..
scons: Re-add -Werror for gem5 develop branch
This is removed from the stable branch to avoid build errors but should
included on the develop branch to aid developers.
This reverts commit 7dd61c865975862b099e1af5e867083ac9307d9b.
Change-Id: I1fe249ce87aa8d70c1f092fc7db1554e6aee7355
---
M SConstruct
1 file changed, 22 insertions(+), 0 deletions(-)
diff --git a/SConstruct b/SConstruct
index e8107ea..bd26e45 100755
--- a/SConstruct
+++ b/SConstruct
@@ -420,6 +420,14 @@
conf.CheckLinkFlag('-Wl,--threads')
conf.CheckLinkFlag(
'-Wl,--thread-count=%d' %
GetOption('num_jobs'))
+
+# Treat warnings as errors but white list some warnings that we
+# want to allow (e.g., deprecation warnings).
+env.Append(CCFLAGS=['-Werror',
+ '-Wno-error=deprecated-declarations',
+ '-Wno-error=deprecated',
+])
+
else:
error('\n'.join((
"Don't know what compiler options to use for your compiler.",
--
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Gerrit-Owner: Bobby Bruce
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[gem5-dev] [M] Change in gem5/gem5[release-staging-v22-1]: misc: Update RELEASE-NOTES.md for v22.1.0.0
`m5 workend`. +- A `PrivateL1SharedL2CacheHierarchy` has been added to the Standard Library. +- A `GEM5_USE_PROXY` environment variable has been added. +This allows users to specify a socks5 proxy server to use when obtaining gem5 resources and the resources.json file. +It uses the format `:`. +- The fastmodel support has been improved to function with Linux Kernel 5.x. +- The `set_se_binary_workload` function now allows for the passing of input parameters to a binary workload. +- A functional CHI cache hierarchy has been added to the gem5 Standard Library: "src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py". +- The RISC-V K extension has been added. +It includes the following instructions: + - Zbkx: xperm8, xperm4 + - Zknd: aes64ds, aes64dsm, aes64im, aes64ks1i, aes64ks2 + - Zkne: aes64es, aes64esm, aes64ks1i, aes64ks2 + - Zknh: sha256sig0, sha256sig1, sha256sum0, sha256sum1, sha512sig0, sha512sig1, sha512sum0, sha512sum1 + - Zksed: sm4ed, sm4ks + - Zksh: sm3p0, sm3p1 + # Version 22.0.0.1 **[HOTFIX]** Fixes relative import in "src/python/gem5/components/processors/simple_core.py". -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66391?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v22-1 Gerrit-Change-Id: I28753f24742ca156e19ac2af4fb302f9de20e852 Gerrit-Change-Number: 66391 Gerrit-PatchSet: 6 Gerrit-Owner: Bobby Bruce Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: base: Remove unused output.hh dependency from trace.cc
Rocky Tatiefo has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67011?usp=email ) Change subject: base: Remove unused output.hh dependency from trace.cc .. base: Remove unused output.hh dependency from trace.cc Change-Id: Ie80ad5f3fb9fc7ee1e35f0624317e0e58cbf152d --- M src/base/trace.cc 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/base/trace.cc b/src/base/trace.cc index 52faa8d..272b035 100644 --- a/src/base/trace.cc +++ b/src/base/trace.cc @@ -38,7 +38,6 @@ #include "base/atomicio.hh" #include "base/logging.hh" -#include "base/output.hh" #include "base/str.hh" #include "debug/FmtFlag.hh" #include "debug/FmtStackTrace.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/67011?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie80ad5f3fb9fc7ee1e35f0624317e0e58cbf152d Gerrit-Change-Number: 67011 Gerrit-PatchSet: 1 Gerrit-Owner: Rocky Tatiefo Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [L] Change in gem5/gem5[develop]: gpu-compute,mem-ruby: Add support for GPU cache bypassing
emControl.sm
+++ b/src/mem/ruby/protocol/RubySlicc_MemControl.sm
@@ -74,6 +74,8 @@
PrefetchBit Prefetch, desc="Is this a prefetch request";
bool ReadX, desc="Exclusive";
int Acks, desc="How many acks to expect";
+ bool isGLCSet,desc="Bypass L1 Cache";
+ bool isSLCSet,desc="Bypass L1 and L2 Caches";
bool functionalRead(Packet *pkt) {
if ((MessageSize == MessageSizeType:Response_Data) ||
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 8d76f78..7d51f80 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -177,6 +177,8 @@
int htmTransactionUid, desc="Used to identify the unique HTM
transaction that produced this request";
bool isTlbi, desc="Memory request is a TLB shootdown
(invalidation) operation";
Addr tlbiTransactionUid, desc="Unique identifier of the TLB shootdown
operation that produced this request";
+ bool isGLCSet, default="false",desc="Flag that determines if
request bypasses L1 or not";
+ bool isSLCSet, default="false",desc="Flag that determines if
request bypasses both L1 and L2 or not";
RequestPtr getRequestPtr();
}
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh
b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 2345c22..9bba146 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -43,7 +43,6 @@
#include
#include
-
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/WriteMask.hh"
@@ -79,6 +78,8 @@
bool m_isTlbi;
// Should be uint64, but SLICC complains about casts
Addr m_tlbiTransactionUid;
+bool m_isGLCSet;
+bool m_isSLCSet;
RubyRequest(Tick curTime, uint64_t _paddr, int _len,
uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode,
@@ -99,6 +100,13 @@
m_tlbiTransactionUid(0)
{
m_LineAddress = makeLineAddress(m_PhysicalAddress);
+if (_pkt) {
+m_isGLCSet = m_pkt->req->isGLCSet();
+m_isSLCSet = m_pkt->req->isSLCSet();
+} else {
+m_isGLCSet = 0;
+m_isSLCSet = 0;
+}
}
/** RubyRequest for memory management commands */
@@ -120,6 +128,13 @@
m_tlbiTransactionUid(0)
{
assert(m_pkt->req->isMemMgmt());
+if (_pkt) {
+m_isGLCSet = m_pkt->req->isGLCSet();
+m_isSLCSet = m_pkt->req->isSLCSet();
+} else {
+m_isGLCSet = 0;
+m_isSLCSet = 0;
+}
}
RubyRequest(Tick curTime, uint64_t _paddr, int _len,
@@ -148,6 +163,13 @@
m_tlbiTransactionUid(0)
{
m_LineAddress = makeLineAddress(m_PhysicalAddress);
+if (_pkt) {
+m_isGLCSet = m_pkt->req->isGLCSet();
+m_isSLCSet = m_pkt->req->isSLCSet();
+} else {
+ m_isGLCSet = 0;
+m_isSLCSet = 0;
+}
}
RubyRequest(Tick curTime, uint64_t _paddr, int _len,
@@ -177,6 +199,14 @@
m_tlbiTransactionUid(0)
{
m_LineAddress = makeLineAddress(m_PhysicalAddress);
+if (_pkt) {
+m_isGLCSet = m_pkt->req->isGLCSet();
+m_isSLCSet = m_pkt->req->isSLCSet();
+
+} else {
+m_isGLCSet = 0;
+m_isSLCSet = 0;
+}
}
RubyRequest(Tick curTime) : Message(curTime) {}
--
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Gerrit-Change-Number: 66991
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Gerrit-Owner: VISHNU RAMADAS
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update util-tlm to require C++17
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66853?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util: Update util-tlm to require C++17 .. util: Update util-tlm to require C++17 It's the version we currently use to compile gem5 Change-Id: I5d2d26e5ba32191d65a4a5ae58d29a16970d062d Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66853 Maintainer: Daniel Carvalho Reviewed-by: Daniel Carvalho Tested-by: kokoro --- M util/tlm/SConstruct 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: Daniel Carvalho: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/tlm/SConstruct b/util/tlm/SConstruct index f1e057d..1a9a79f 100644 --- a/util/tlm/SConstruct +++ b/util/tlm/SConstruct @@ -51,11 +51,12 @@ env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch, gem5_root + '/util/systemc/gem5_within_systemc', gem5_root + '/ext/systemc/src', +gem5_root + '/ext', '#src', '#examples/common', ]) -env.Append(CXXFLAGS=['-std=c++14', +env.Append(CXXFLAGS=['-std=c++17', '-DSC_INCLUDE_DYNAMIC_PROCESSES', '-DTRACING_ON', ]) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66853?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5d2d26e5ba32191d65a4a5ae58d29a16970d062d Gerrit-Change-Number: 66853 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: util: Fix missing include of sim/core.hh in util-tlm
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66852?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util: Fix missing include of sim/core.hh in util-tlm .. util: Fix missing include of sim/core.hh in util-tlm Change-Id: I6dbf71dac903a660369bf8b33ae0c88d28d07457 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66852 Reviewed-by: Matthias Jung Tested-by: kokoro Reviewed-by: Daniel Carvalho Maintainer: Daniel Carvalho --- M util/tlm/src/sc_master_port.cc 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: kokoro: Regressions pass Matthias Jung: Looks good to me, approved Daniel Carvalho: Looks good to me, approved; Looks good to me, approved diff --git a/util/tlm/src/sc_master_port.cc b/util/tlm/src/sc_master_port.cc index 2e10828..c0bb6d5 100644 --- a/util/tlm/src/sc_master_port.cc +++ b/util/tlm/src/sc_master_port.cc @@ -36,6 +36,7 @@ #include "params/ExternalMaster.hh" #include "sc_ext.hh" #include "sc_master_port.hh" +#include "sim/core.hh" #include "sim/system.hh" namespace Gem5SystemC -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66852?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6dbf71dac903a660369bf8b33ae0c88d28d07457 Gerrit-Change-Number: 66852 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Matthias Jung Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: util: ext/systemc is importing env Environment instead of main
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66854?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: util: ext/systemc is importing env Environment instead of
main
..
util: ext/systemc is importing env Environment instead of main
This got changed by [1]
With this patch we export env instead of main. There is no risk of
ext/systemc polluting the environment as its SConscript is cloning env
to the systemc variable anyway, so this double copy was redundant anyway
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/56750
Change-Id: Ib6648e9b38416cac0bc7f06d90a337f32bdca6ca
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66854
Maintainer: Daniel Carvalho
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M util/tlm/SConstruct
1 file changed, 23 insertions(+), 3 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/tlm/SConstruct b/util/tlm/SConstruct
index 1a9a79f..7fe09d4 100644
--- a/util/tlm/SConstruct
+++ b/util/tlm/SConstruct
@@ -74,15 +74,14 @@
# the SystemC SConscript makes certain assumptions, we need to fulfill
these
# assumptions before calling the SConscript.
-main = env
sys.path.append(gem5_root + '/src/python')
AddOption('--no-colors', dest='use_colors', action='store_false',
help="Don't add color to abbreviated scons output")
-main.SConsignFile('build/systemc/sconsign')
+env.SConsignFile('build/systemc/sconsign')
SConscript(gem5_root + '/ext/systemc/SConscript',
variant_dir='build/systemc',
- exports='main')
+ exports='env')
# By adding libraries as dependencies instead of using LIBS, we avoid that
# the user needs to set the LD_LIBRARY_PATH
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib6648e9b38416cac0bc7f06d90a337f32bdca6ca
Gerrit-Change-Number: 66854
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-CC: Bobby Bruce
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: cxxConfigInit has been removed by gem5
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66851?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: util: cxxConfigInit has been removed by gem5
..
util: cxxConfigInit has been removed by gem5
This was merged in [1]
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/49455
Change-Id: Iba558dd01d5c8fbc05e4d3a106a3e3ff6b696333
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66851
Reviewed-by: Daniel Carvalho
Maintainer: Daniel Carvalho
Tested-by: kokoro
Reviewed-by: Matthias Jung
---
M util/tlm/src/sim_control.cc
1 file changed, 19 insertions(+), 2 deletions(-)
Approvals:
Matthias Jung: Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve; Looks
good to me, approved
kokoro: Regressions pass
diff --git a/util/tlm/src/sim_control.cc b/util/tlm/src/sim_control.cc
index a8a3da4..834cfe0 100644
--- a/util/tlm/src/sim_control.cc
+++ b/util/tlm/src/sim_control.cc
@@ -72,8 +72,6 @@
}
instance = this;
-gem5::cxxConfigInit();
-
// register the systemc slave and master port handler
gem5::ExternalSlave::registerHandler("tlm_slave",
new SCSlavePortHandler(*this));
--
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Gerrit-Change-Id: Iba558dd01d5c8fbc05e4d3a106a3e3ff6b696333
Gerrit-Change-Number: 66851
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Matthias Jung
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct the IllegalInstFault messege of instruction c.add...
Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66931?usp=email )
Change subject: arch-riscv: Correct the IllegalInstFault messege of
instruction c.addi4spn
..
arch-riscv: Correct the IllegalInstFault messege of instruction
c.addi4spn
In Riscv Manual Volumn I: Unpriviledged ISA section 18.5, c.addi4spn
will not working if imm == 0, not machInst == 0. It is changed in the
https://gem5-review.git.corp.google.com/c/public/gem5/+/66732, and here is
the additional patch to the CL.
Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66931
Reviewed-by: Yu-hsin Wang
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 20 insertions(+), 1 deletion(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c070392..53d4a4d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -48,7 +48,7 @@
CIMM8<5:2> << 6;
}}, {{
if (imm == 0)
-return std::make_shared("zero
instruction",
+return std::make_shared("immediate = 0",
machInst);
Rp2 = rvSext(sp + imm);
}}, uint64_t);
--
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Gerrit-Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
Gerrit-Change-Number: 66931
Gerrit-PatchSet: 3
Gerrit-Owner: Roger Chang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jui-min Lee
Gerrit-Reviewer: Roger Chang
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Earl Ou
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct the IllegalInstFault messege of instruction c.add...
Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66931?usp=email )
Change subject: arch-riscv: Correct the IllegalInstFault messege of
instruction c.addi4spn
..
arch-riscv: Correct the IllegalInstFault messege of instruction
c.addi4spn
In Riscv Manual Volumn I: Unpriviledged ISA section 18.5, c.addi4spn
will not working if imm == 0, not machInst == 0. It is changed in the
[CL](https://gem5-review.git.corp.google.com/c/public/gem5/+/66732), and
here is the additional patch to the CL.
Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c070392..53d4a4d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -48,7 +48,7 @@
CIMM8<5:2> << 6;
}}, {{
if (imm == 0)
-return std::make_shared("zero
instruction",
+return std::make_shared("immediate = 0",
machInst);
Rp2 = rvSext(sp + imm);
}}, uint64_t);
--
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Gerrit-Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
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Gerrit-Owner: Roger Chang
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Refactor compressed instructions
5<4:4> << 4) |
+ (CIMM5<0:0> << 5) |
+ (CIMM5<3:3> << 6) |
+ (CIMM5<2:1> << 7) |
+ (CIMM1 << 9));
+}}, {{
+if (imm == 0) {
+return std::make_shared(
+"immediate = 0", machInst);
+}
+sp_sd = rvSext(sp_sd + imm);
+}});
+default: CIOp::c_lui({{
+imm = sext<6>(CIMM5 | (CIMM1 << 5)) << 12;
+}}, {{
+if (RC1 == 0 || RC1 == 2) {
+return std::make_shared(
+"source reg x0", machInst);
+}
+if (imm == 0) {
+return std::make_shared(
+"immediate = 0", machInst);
+}
Rc1_sd = imm;
}});
-0x3: decode RC1 {
-0x2: c_addi16sp({{
-imm = CIMM5<4:4> << 4 |
- CIMM5<0:0> << 5 |
- CIMM5<3:3> << 6 |
- CIMM5<2:1> << 7;
-if (CIMM1 > 0)
-imm |= ~((int64_t)0x1FF);
-}}, {{
-if (imm == 0) {
-return std::make_shared(
-"immediate = 0", machInst);
-}
-sp_sd = rvSext(sp_sd + imm);
-}});
-default: c_lui({{
-imm = CIMM5 << 12;
-if (CIMM1 > 0)
-imm |= ~((uint64_t)0x1);
-}}, {{
-if (RC1 == 0 || RC1 == 2) {
-return std::make_shared(
-"source reg x0", machInst);
-}
-if (imm == 0) {
-return std::make_shared(
-"immediate = 0", machInst);
-}
-Rc1_sd = imm;
-}});
-}
}
0x4: decode CFUNCT2HIGH {
format CIOp {
@@ -418,7 +398,7 @@
}
ra = rvSext(NPC);
NPC = rvZext(Rc1);
-}}, IsIndirectControl, IsUncondControl);
+}}, IsIndirectControl, IsUncondControl, IsCall);
default: CompressedROp::c_add({{
Rc1_sd = rvSext(Rc1_sd + Rc2_sd);
}});
diff --git a/src/arch/riscv/isa/formats/compressed.isa
b/src/arch/riscv/isa/formats/compressed.isa
index d098658..3d89ec3 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -61,33 +61,31 @@
def format CJOp(code, *opt_flags) {{
imm_code = """
- imm = CJUMPIMM3TO1 << 1 |
- CJUMPIMM4TO4 << 4 |
- CJUMPIMM5TO5 << 5 |
- CJUMPIMM6TO6 << 6 |
- CJUMPIMM7TO7 << 7 |
- CJUMPIMM9TO8 << 8 |
- CJUMPIMM10TO10 << 10;
-if (CJUMPIMMSIGN)
-imm |= ~((int64_t)0x7FF);
+imm = sext<12>((CJUMPIMM3TO1 << 1) |
+ (CJUMPIMM4TO4 << 4) |
+ (CJUMPIMM5TO5 << 5) |
+ (CJUMPIMM6TO6 << 6) |
+ (CJUMPIMM7TO7 << 7) |
+ (CJUMPIMM9TO8 << 8) |
+ (CJUMPIMM10TO10 << 10) |
+ (CJUMPIMMSIGN << 11));
"""
iop = InstObjParams(name, Name, 'ImmOp',
{'code': code, 'imm_code': imm_code,
'regs': ''}, opt_flags)
header_output = BranchDeclare.subst(iop)
-decoder_output = ImmConstructor.subst(iop)
+decoder_output = JumpConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BranchExecute.subst(iop)
}};
def format CBOp(code, *opt_flags) {{
imm_code = """
-imm = CIMM5<2:1> << 1 |
- CIMM3<1:0> << 3 |
- CIMM5<0:0> << 5 |
- CIMM5<4:3> << 6;
-if (CIMM3<2:2> > 0)
- imm |= ~((int64_t)0xFF);
+ imm = sext<9>((CIMM5<2:1> << 1) |
+ (CIMM3<1:0> << 3) |
+
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor template JumpConstructor
Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66811?usp=email )
Change subject: arch-riscv: Refactor template JumpConstructor
..
arch-riscv: Refactor template JumpConstructor
Add COPCODE == 4 condition to ensure the available instruction is either
c_jr or c_jalr and the flag IsReturn should set for instruction c_jalr if
RC1 == t0
Change-Id: I1b39a6c1dc52c8035f16cc64a1b4c494b14879c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66811
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Yu-hsin Wang
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 23 insertions(+), 3 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 6be281f..bb500f5 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -250,9 +250,14 @@
%(constructor)s;
%(imm_code)s;
if (QUADRANT != 0x3) {
-// Handle "c_jr" instruction, set "IsReturn" flag if RC1 is 1
or 5
-if (CFUNCT1 == 0 && (RC1 == 1 || RC1 == 5))
-flags[IsReturn] = true;
+if (COPCODE == 4) {
+// Handle "c_jr" instruction, set "IsReturn" flag if RC1
is 1 or 5
+if (CFUNCT1 == 0 && (RC1 == 1 || RC1 == 5))
+flags[IsReturn] = true;
+// Handle "c_jalr" instruction, set IsReturn if RC1 != ra
+if (CFUNCT1 == 1 && RC1 == 5)
+flags[IsReturn] = true;
+}
} else {
bool rd_link = (RD == 1 || RD == 5);
bool rs1_link = (RS1 == 1 || RS1 == 5);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1b39a6c1dc52c8035f16cc64a1b4c494b14879c0
Gerrit-Change-Number: 66811
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Roger Chang
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Earl Ou
Gerrit-CC: Jui-min Lee
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev: Fix -Wunused-variable in structured binding
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66891?usp=email )
Change subject: dev: Fix -Wunused-variable in structured binding
..
dev: Fix -Wunused-variable in structured binding
Change-Id: Ia244767dd9d1dd7b72c320fb78e48f206694f5a2
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66891
Tested-by: kokoro
Reviewed-by: Yu-hsin Wang
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/dev/reg_bank.hh
1 file changed, 17 insertions(+), 2 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/reg_bank.hh b/src/dev/reg_bank.hh
index 66d668b..32d9058 100644
--- a/src/dev/reg_bank.hh
+++ b/src/dev/reg_bank.hh
@@ -1018,8 +1018,8 @@
virtual void
reset()
{
-for (auto &[offset, reg]: _offsetMap)
-reg.get().reset();
+for (auto : _offsetMap)
+it.second.get().reset();
}
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia244767dd9d1dd7b72c320fb78e48f206694f5a2
Gerrit-Change-Number: 66891
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev: Fix -Wunused-variable in structured binding
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66891?usp=email )
Change subject: dev: Fix -Wunused-variable in structured binding
..
dev: Fix -Wunused-variable in structured binding
Change-Id: Ia244767dd9d1dd7b72c320fb78e48f206694f5a2
Signed-off-by: Giacomo Travaglini
---
M src/dev/reg_bank.hh
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/dev/reg_bank.hh b/src/dev/reg_bank.hh
index 66d668b..32d9058 100644
--- a/src/dev/reg_bank.hh
+++ b/src/dev/reg_bank.hh
@@ -1018,8 +1018,8 @@
virtual void
reset()
{
-for (auto &[offset, reg]: _offsetMap)
-reg.get().reset();
+for (auto : _offsetMap)
+it.second.get().reset();
}
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia244767dd9d1dd7b72c320fb78e48f206694f5a2
Gerrit-Change-Number: 66891
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: ext/systemc is importing env Environment instead of main
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66854?usp=email )
Change subject: util: ext/systemc is importing env Environment instead of
main
..
util: ext/systemc is importing env Environment instead of main
This got changed by [1]
With this patch we export env instead of main. There is no risk of
ext/systemc polluting the environment as its SConscript is cloning env
to the systemc variable anyway, so this double copy was redundant anyway
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/56750
Change-Id: Ib6648e9b38416cac0bc7f06d90a337f32bdca6ca
Signed-off-by: Giacomo Travaglini
---
M util/tlm/SConstruct
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/util/tlm/SConstruct b/util/tlm/SConstruct
index 1a9a79f..7fe09d4 100644
--- a/util/tlm/SConstruct
+++ b/util/tlm/SConstruct
@@ -74,15 +74,14 @@
# the SystemC SConscript makes certain assumptions, we need to fulfill
these
# assumptions before calling the SConscript.
-main = env
sys.path.append(gem5_root + '/src/python')
AddOption('--no-colors', dest='use_colors', action='store_false',
help="Don't add color to abbreviated scons output")
-main.SConsignFile('build/systemc/sconsign')
+env.SConsignFile('build/systemc/sconsign')
SConscript(gem5_root + '/ext/systemc/SConscript',
variant_dir='build/systemc',
- exports='main')
+ exports='env')
# By adding libraries as dependencies instead of using LIBS, we avoid that
# the user needs to set the LD_LIBRARY_PATH
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib6648e9b38416cac0bc7f06d90a337f32bdca6ca
Gerrit-Change-Number: 66854
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update util-tlm to require C++17
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66853?usp=email ) Change subject: util: Update util-tlm to require C++17 .. util: Update util-tlm to require C++17 It's the version we currently use to compile gem5 Change-Id: I5d2d26e5ba32191d65a4a5ae58d29a16970d062d Signed-off-by: Giacomo Travaglini --- M util/tlm/SConstruct 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/util/tlm/SConstruct b/util/tlm/SConstruct index f1e057d..1a9a79f 100644 --- a/util/tlm/SConstruct +++ b/util/tlm/SConstruct @@ -51,11 +51,12 @@ env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch, gem5_root + '/util/systemc/gem5_within_systemc', gem5_root + '/ext/systemc/src', +gem5_root + '/ext', '#src', '#examples/common', ]) -env.Append(CXXFLAGS=['-std=c++14', +env.Append(CXXFLAGS=['-std=c++17', '-DSC_INCLUDE_DYNAMIC_PROCESSES', '-DTRACING_ON', ]) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66853?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5d2d26e5ba32191d65a4a5ae58d29a16970d062d Gerrit-Change-Number: 66853 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: util: Fix missing include of sim/core.hh in util-tlm
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66852?usp=email ) Change subject: util: Fix missing include of sim/core.hh in util-tlm .. util: Fix missing include of sim/core.hh in util-tlm Change-Id: I6dbf71dac903a660369bf8b33ae0c88d28d07457 Signed-off-by: Giacomo Travaglini --- M util/tlm/src/sc_master_port.cc 1 file changed, 11 insertions(+), 0 deletions(-) diff --git a/util/tlm/src/sc_master_port.cc b/util/tlm/src/sc_master_port.cc index 2e10828..c0bb6d5 100644 --- a/util/tlm/src/sc_master_port.cc +++ b/util/tlm/src/sc_master_port.cc @@ -36,6 +36,7 @@ #include "params/ExternalMaster.hh" #include "sc_ext.hh" #include "sc_master_port.hh" +#include "sim/core.hh" #include "sim/system.hh" namespace Gem5SystemC -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66852?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6dbf71dac903a660369bf8b33ae0c88d28d07457 Gerrit-Change-Number: 66852 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update run_gem5_fs.sh script with AArch64 platform
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66856?usp=email )
Change subject: util: Update run_gem5_fs.sh script with AArch64 platform
..
util: Update run_gem5_fs.sh script with AArch64 platform
The example script is using VExpress_EMM, which is a deprecated platform
and it is referring to an AArch32 kernel. With this patch we
use the VExpress_GEM5_Foundation platform instead and point
to a AArch64 kernel
Change-Id: I961d5d5de71bc284c7492ee7b04088148909ca1b
Signed-off-by: Giacomo Travaglini
---
M util/tlm/run_gem5_fs.sh
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/util/tlm/run_gem5_fs.sh b/util/tlm/run_gem5_fs.sh
index 9065cbf..2316194 100755
--- a/util/tlm/run_gem5_fs.sh
+++ b/util/tlm/run_gem5_fs.sh
@@ -42,9 +42,8 @@
--mem-size=512MB\
--mem-channels=1\
--caches --l2cache \
---machine-type=VExpress_EMM \
---dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
---kernel=vmlinux.aarch32.ll_20131205.0-gem5
+--machine-type=VExpress_GEM5_Foundation \
+--kernel=vmlinux.arm64
echo -e "\n${BGre}Run gem5 ${RCol}\n"
--
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Gerrit-Change-Id: I961d5d5de71bc284c7492ee7b04088148909ca1b
Gerrit-Change-Number: 66856
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Include libraries when building gem5 as a shared object
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66855?usp=email ) Change subject: scons: Include libraries when building gem5 as a shared object .. scons: Include libraries when building gem5 as a shared object While we include shared libraries in the Executable class, we are not doing it when linking the SharedLib. This means the resulting Shared library won't have the library as a dependency (it won't appear in ldd) and the symbols will remain undefined. Any executable will fail to link with the shared library as the executable will contain undefined references. This bug was exposed when I tried to link util/tlm sources with libgem5.so. As I have libpng/libpng-dev installed in my machine, the shared library included libpng headers, but didn't link to the library as scons didn't append "-lpng" to the linking CL. Those png functions thus remained ubdefined symbols. Change-Id: Id9c4a65607a7177f71659f1ac400a67edf7080fd Signed-off-by: Giacomo Travaglini --- M src/SConscript 1 file changed, 30 insertions(+), 0 deletions(-) diff --git a/src/SConscript b/src/SConscript index 4e7139c..51b4bd9 100644 --- a/src/SConscript +++ b/src/SConscript @@ -376,6 +376,12 @@ def declare(self, env): objs = self.srcs_to_objs(env, self.sources(env)) +libs = self.libs(env) +# Higher priority libraries should be earlier in the list. +libs.sort(key=lambda l: l.priority, reverse=True) +if libs: +env.Append(LIBS=list(lib.source for lib in libs)) + date_obj = env.SharedObject(date_source) env.Depends(date_obj, objs) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66855?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id9c4a65607a7177f71659f1ac400a67edf7080fd Gerrit-Change-Number: 66855 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
