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Should this perhaps be a probe rather?
- Andreas Hansson
On March 4,
Hi Marcus,
I’d also say this would be a great topic for the User Workshop at ISCA:
http://www.gem5.org/User_workshop_2015
Andreas
On 03/03/2015 15:14, Ali Saidi via gem5-dev gem5-dev@gem5.org wrote:
Hi Marcus,
Option 1 is probably the most preferred route as the code is much more
likely to
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Some minor formatting issues, but overall it looks good.
On Feb. 10, 2015, 5:37 p.m., Stephan Diestelhorst wrote:
I have had a similar impulse, when inspecting this code. However, the
prefetch hitting a write-back in an upper cache is actually already handled
in CacheTagStore::getTimingPacket():
// Check if the prefetch hit
changeset 9ba5e70964a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9ba5e70964a4
description:
mem: Tidy up the cache debug messages
Avoid redundant inclusion of the name in the DPRINTF string.
diffstat:
src/mem/cache/base.cc | 10 +-
changeset d1387fcd94b8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1387fcd94b8
description:
mem: Unify all cache DPRINTF address formatting
This patch changes all the DPRINTF messages in the cache to use
'%#llx' every time a packet address is
changeset 8a20e2a1562d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8a20e2a1562d
description:
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing,
changeset 4f8c1bd6fdb8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4f8c1bd6fdb8
description:
arm: Share a port for the two table walker objects
This patch changes how the MMU and table walkers are created such that
a single port is used to connect
changeset 67b3e74de9ae in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=67b3e74de9ae
description:
mem: Move crossbar default latencies to subclasses
This patch introduces a few subclasses to the CoherentXBar and
NoncoherentXBar to distinguish the
changeset 1072b1381560 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1072b1381560
description:
mem: Fix cache MSHR conflict determination
This patch fixes a rather subtle issue in the sending of MSHR requests
in the cache, where the logic previously
changeset 9b71309d29f9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9b71309d29f9
description:
tests: Run regression timeout as foreground
Allow the user to send signals such as Ctrl C to the gem5 runs. Note
that this assumes coreutils = 8.13, which
changeset b1d90d88420e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b1d90d88420e
description:
mem: Add byte mask to Packet::checkFunctional
This patch changes the valid-bytes start/end to a proper byte
mask. With the changes in timing introduced in
On Feb. 19, 2015, 10:50 p.m., Andreas Hansson wrote:
Ship It!
Could someone be kind enough to push this?
- Andreas
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Great. Let us know if there are still any remaining issues.
We’ve got some additional cache fixes that should be on RB before the end of
the week.
Andreas
From: Steve Reinhardt ste...@gmail.commailto:ste...@gmail.com
Date: Monday, 2 March 2015 16:47
To: Andreas Hansson
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- Andreas Hansson
On Feb. 28, 2015, 10:34 p.m.,
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- Andreas Hansson
On Feb. 28, 2015, 10:37 p.m.,
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- Andreas Hansson
On Feb. 28, 2015, 10:39 p.m.,
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Ship It!
- Andreas Hansson
On Feb. 28, 2015, 10:41 p.m.,
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- Andreas Hansson
On Feb. 28, 2015, 10:40 p.m.,
Could it not be as simple as back pressure?
The traffic generator can only send requests as fast as the port (crossbar
in this case), can accept them.
I suspect if you set the max time to some larger value it is all fine.
Andreas
On 26/02/2015 08:04, Sensen Hu - EWI via gem5-dev
As the error message suggest you seem to have a packet that spans a cache
line boundary. Have you checked the address and/or size to make sure they
all are within a cache line?
Andreas
On 26/02/2015 21:15, Sensen Hu - EWI via gem5-dev gem5-dev@gem5.org
wrote:
hi, Andreas.
I've tried to set
Hi all,
As you may have seen, we have posted a number of patches that improve the
fidelity of the classic interconnect models, along with quite some fixes for
the caches and CPUs. Unsurprisingly these patches shake up the regression stats
quite a bit, and I encourage anyone interested in
Hi all,
The patches are all on RB for the C++/Python stats revamp, including json
and database output. The problem is speed. Due to the C++/Python swig
interface the impact on performance is quite substantial (even ignoring
the actual output). We have been playing around with ‘swig —builtin’ but
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Hi,
I would suggest to rather make a self-contained script and not rely on
test.py. That way it is easier to get a global picture of what you are
actually doing.
I suspect something is going wrong in how you are launching the simulator.
Andreas
On 23/02/2015 16:47, Sensen Hu - EWI via gem5-dev
Hi Gregory,
The traffic generators should work just fine with Ruby, and they already
have trace players. There is nothing precluding you from using the
non-Ruby memory system. Ruby gives you the option of having a more
elaborate network topology, but if you are fine with crossbars the
non-Ruby
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- Andreas Hansson
On Feb. 19, 2015, 10:46 p.m.,
changeset 417ba77dedb4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=417ba77dedb4
description:
mem: mmap the backing store with MAP_NORESERVE
This patch ensures we can run simulations with very large simulated
memories (at least 64 TB based on some
changeset 829adc48e175 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=829adc48e175
description:
arch: Make readMiscRegNoEffect const throughout
Finally took the plunge and made this apply to all ISAs, not just ARM.
diffstat:
src/arch/alpha/isa.cc
changeset d0004c12d024 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d0004c12d024
description:
mem: Use the range cache for lookup as well as access
This patch changes the range cache used in the global physical memory
to be an iterator so that we
changeset c6cb94a14fea in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c6cb94a14fea
description:
config: Add memcheck stress test
This is a rather unfortunate copy of the memtest.py example script,
that actually stresses the system with true sharing
changeset ac3236a0873b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ac3236a0873b
description:
dev: Fix undefined behaviuor in i8254xGBe
This patch fixes a rather unfortunate oversight where the annotation
pointer was used even though it is null.
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configs/common/FSConfig.py
http://reviews.gem5.org/r/2655/#comment5173
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Hi everyone,
The following patches are ready to go, and I intend to push them early next
week. If you need more time to review please let me know.
Thanks,
Andreas
# CPU tracing
http://reviews.gem5.org/r/2563/
# Miscellaneous cleanups and fixes
http://reviews.gem5.org/r/2567/
On Feb. 10, 2015, 5:37 p.m., Stephan Diestelhorst wrote:
I have had a similar impulse, when inspecting this code. However, the
prefetch hitting a write-back in an upper cache is actually already handled
in CacheTagStore::getTimingPacket():
// Check if the prefetch hit
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Hi Raul,
gem5.perf and gem5.prof are targets used to profile gem5, not what is
running as a guest in gem5. gem5.perf is using google perftools, and
gem5.prof is using gprof. Thus, if you are optimising gem5 itself these
build targets are very helpful. Note that the stats.txt has nothing to do
changeset 12632859858a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=12632859858a
description:
stats: Bump the MemTest regression stats
Reflect changes in the tester behaviour.
diffstat:
changeset 4972ada74310 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4972ada74310
description:
config: Revamp memtest to allow testers on any level
This patch revamps the memtest example script and allows for the
insertion of testers at any level in
changeset a24286e33318 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a24286e33318
description:
base: Do not dereference NULL in CompoundFlag creation
This patch fixes the CompoundFlag constructor, ensuring that it does
not dereference NULL. Doing so
changeset 22452667fd5c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=22452667fd5c
description:
cpu: Tidy up the MemTest and make false sharing more obvious
The MemTest class really only tests false sharing, and as such there
was a lot of old cruft
Hi everyone,
At ISCA-42 this year we are organising the second gem5 user workshop,
bringing together groups and individuals across the gem5
community. The goal of the workshop is to provide a forum to
discuss what is going on in the community, how we can best
leverage each other's contributions,
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(Updated Feb. 10, 2015, 5:43 p.m.)
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Hi all,
To me it sounds like the whole ruby philosophy of “two, or even three
views of the same data” might need an overhaul.
Andreas
On 10/02/2015 04:44, Beckmann, Brad via gem5-dev gem5-dev@gem5.org
wrote:
Thanks Jason. I didn't notice your patch until after I sent out my
email. It looks
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- Andreas Hansson
On Feb. 8, 2015, 10:34 p.m.,
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- Andreas Hansson
On Feb. 9, 2015, 6:05 a.m.,
On Feb. 9, 2015, 8:28 a.m., Andreas Hansson wrote:
Ship It!
I guess mem: Add local var in Cache::recvTimingResp
- Andreas
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mem:
- Andreas Hansson
On Feb. 9, 2015, 6:05 a.m., Steve
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Hi Giorgos,
The default behaviour in gem5 is to interleave the memory channels on a
128-byte granularity and use an XOR-based hash to avoid skewing the
channel usage.
That said, you can do what ever you please :-). The basic functionality is
controlled by configs/common/MemConfig.py, and you can
On Feb. 3, 2015, 9:37 p.m., Brandon Potter wrote:
The patch seems like a landmine for an unsuspecting user as it would be
difficult to diagnose if swap space is exhausted. It will probably be
evident that memory exhaustion caused the runtime error (segmentation
fault), but tracking
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On Feb. 7, 2015, 6:14 p.m., Steve Reinhardt wrote:
Awesome! This lack of separate channels for requests responses has
bugged me for years, I'm really glad to see it addressed.
One minor suggestion: to me, terms like recvRetryReq and recvRetryResp seem
backward, since 'retry' is
On Jan. 30, 2015, 9:47 p.m., Nilay Vaish wrote:
src/cpu/testers/memtest/MemTest.py, line 55
http://reviews.gem5.org/r/2611/diff/1/?file=43345#file43345line55
Are you sure this should be dropped? I think the coherence protocols
that provide a dma controller need this for testing.
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On Feb. 3, 2015, 9:37 p.m., Brandon Potter wrote:
The patch seems like a landmine for an unsuspecting user as it would be
difficult to diagnose if swap space is exhausted. It will probably be
evident that memory exhaustion caused the runtime error (segmentation
fault), but tracking
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It think there are more (and bigger issues) at play here. I'd suggest to
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- Andreas Hansson
On Feb. 6, 2015, 12:38 a.m.,
On Feb. 6, 2015, 8:18 a.m., Andreas Hansson wrote:
It think there are more (and bigger issues) at play here. I'd suggest to
try this out with: http://reviews.gem5.org/r/2626/
If you run it with -p, prefetches enabled, it doesn't take many seconds
before it hits an assert. We're
On Feb. 6, 2015, 8:16 a.m., Andreas Hansson wrote:
Ship It!
Andreas Hansson wrote:
Here it would be good to test with the new memtest:
http://reviews.gem5.org/r/2612/
Note that the caches suffer from message deadlock at the moment, and the
test dies very quickly. I
On Feb. 6, 2015, 5:10 p.m., Steve Reinhardt wrote:
So would this replace memtest.py? If so, then factoring out the common
code would not be an issue. If not, why not?
The two are complementary:
memtest.py uses MemTest and only tests false sharing, with some progress
detection built in
On Feb. 6, 2015, 5:10 p.m., Steve Reinhardt wrote:
So would this replace memtest.py? If so, then factoring out the common
code would not be an issue. If not, why not?
Andreas Hansson wrote:
The two are complementary:
memtest.py uses MemTest and only tests false
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On Feb. 5, 2015, 8:25 a.m., Andreas Hansson wrote:
src/mem/ruby/system/DMASequencer.hh, line 76
http://reviews.gem5.org/r/2627/diff/1/?file=43428#file43428line76
Can we not get this through the sequencer rather?
Jason Power wrote:
I can make this change, if you want. But I
On Feb. 3, 2015, 6:40 p.m., Stephan Diestelhorst wrote:
Looks fine to me, too. However, when following the logic here, I found
that this is a generally messy part of the O3 core. I think it would make
sense to (1) restructure similar to the Minor CPU core (where there is a
state
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On Feb. 5, 2015, 8:25 a.m., Andreas Hansson wrote:
src/mem/ruby/system/RubySystem.py, line 51
http://reviews.gem5.org/r/2627/diff/1/?file=43431#file43431line51
I find the description rather misleading.
In essence it is not the case of bypassing the interconnect, it is
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LGTM
- Andreas Hansson
On Feb. 5, 2015, 4:02 p.m., Jason
On Feb. 5, 2015, 4:16 p.m., Joel Hestness wrote:
LGTM, also.
I don't think it should be addressed in this patch, but I'm making notes
here as a vision for how I think we should proceed with these backing store
and protocol developments:
Really what we're capturing with the
On Jan. 30, 2015, 9:47 p.m., Nilay Vaish wrote:
src/cpu/testers/memtest/MemTest.py, line 55
http://reviews.gem5.org/r/2611/diff/1/?file=43345#file43345line55
Are you sure this should be dropped? I think the coherence protocols
that provide a dma controller need this for testing.
Hi Nilay,
It did not do anything sensible. The MemTest fundamentally only tests
false sharing since it has no notion of a memory consistency model. Thus,
the “non DMA” transactions access a specific byte in the cache line.
The DMA transactions were multi-byte transactions, that had no tests
changeset aae98c1cf4a0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aae98c1cf4a0
description:
cpu: Ensure timing CPU sinks response before sending new request
This patch changes how the timing CPU deals with processing responses,
always scheduling
changeset f6c168692b20 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f6c168692b20
description:
base: Add XOR-based hashed address interleaving
This patch extends the current address interleaving with basic hashing
support. Instead of directly
changeset bb7cd7193edc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bb7cd7193edc
description:
config: Adjust DRAM channel interleaving defaults
This patch changes the DRAM channel interleaving default behaviour to
be more representative. The
changeset d59e40b074c6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d59e40b074c6
description:
scons: Avoid implicit command dependencies
Work around a bug in scons that causes the param wrappers being
compiled twice. The easiest way for us to do so
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changeset 204a0f53035e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=204a0f53035e
description:
mem: Clarify cache behaviour for pending dirty responses
This patch adds a bit of clarification around the assumptions made in
the cache when packets are
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