* build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
passed.
*
changeset 78d25904f66a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=78d25904f66a
description:
X86: Fix how the parity flag is computed.
It's only for the lowest order byte, and I had the polarity wrong.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
changeset 801f1fc07a58 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=801f1fc07a58
description:
X86: Fix the carry flag for shl.
diffstat:
1 file changed, 3 insertions(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |4 +++-
diffs (15 lines):
diff -r
changeset 580a6fbc7585 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=580a6fbc7585
description:
X86: Fix the carry flag for shr.
diffstat:
1 file changed, 4 insertions(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |5 -
diffs (16 lines):
diff -r
changeset fa4e81c993d0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fa4e81c993d0
description:
X86: Fix sign extension when doing an arithmetic shift right by 0.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |2 +-
changeset 8e72cf8196cc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8e72cf8196cc
description:
X86: Fix the sar carry flag.
diffstat:
1 file changed, 5 insertions(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |6 +-
diffs (17 lines):
diff -r
changeset 647111272094 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=647111272094
description:
X86: Actually set the flags on a rotate left instruction.
diffstat:
1 file changed, 9 insertions(+), 9 deletions(-)
changeset cc8568cfce8f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cc8568cfce8f
description:
X86: Handle left rotations that go all the way around or more.
diffstat:
1 file changed, 4 insertions(+), 3 deletions(-)
src/arch/x86/isa/microops/regop.isa |7 ---
changeset eebbe9f1bf10 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=eebbe9f1bf10
description:
X86: Make shifts/rotations that write to 32 bits of a register zero
extend.
diffstat:
1 file changed, 4 insertions(+), 4 deletions(-)
src/arch/x86/isa/microops/regop.isa |
changeset a32abe4e17e1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a32abe4e17e1
description:
X86: Set the flags on a rotate right instruction.
diffstat:
1 file changed, 9 insertions(+), 9 deletions(-)
changeset a7a428f403da in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a7a428f403da
description:
X86: Handle rotating right all the way around or more.
diffstat:
1 file changed, 4 insertions(+), 3 deletions(-)
src/arch/x86/isa/microops/regop.isa |7 ---
diffs
changeset b9aa6a397b57 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b9aa6a397b57
description:
X86: Set the flags for rotate right with carry instructions.
diffstat:
1 file changed, 9 insertions(+), 9 deletions(-)
changeset 755cf9b6185f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=755cf9b6185f
description:
X86: Handle rotate right with carry instructions that go all the way
around or more.
diffstat:
1 file changed, 10 insertions(+), 6 deletions(-)
changeset 709527fb7250 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=709527fb7250
description:
X86: Set the flags on rotate left with carry instructions.
diffstat:
1 file changed, 9 insertions(+), 9 deletions(-)
changeset f964c623723c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f964c623723c
description:
X86: Let microops force folding an index into the high byte of a
register.
diffstat:
1 file changed, 4 insertions(+)
src/arch/x86/isa/microasm.isa |4
diffs (14
changeset d959f578ae42 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d959f578ae42
description:
X86: Fix the indexing for ah in byte multiply instructions.
diffstat:
1 file changed, 6 insertions(+), 12 deletions(-)
changeset f7f0d361d6fc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f7f0d361d6fc
description:
X86: Fix the indexing for ah in byte division instructions.
diffstat:
1 file changed, 27 insertions(+), 27 deletions(-)
changeset 59108c231208 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=59108c231208
description:
X86: Use the new forced folding mechanism for the SAHF and LAHF
instructions.
diffstat:
2 files changed, 4 insertions(+), 26 deletions(-)
changeset 57e6d35dde10 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=57e6d35dde10
description:
X86: Handle rotate left with carry instructions that go all the way
around or more.
diffstat:
1 file changed, 9 insertions(+), 6 deletions(-)
changeset 418145f4d7a6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=418145f4d7a6
description:
X86: Make sure immediate values are truncated properly.
Register values will be picked which will assure they don't have junk
beyond
the part we're using.
changeset 209c3818a863 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=209c3818a863
description:
X86: Make the check for negative operands for sign multiply more direct.
diffstat:
1 file changed, 2 insertions(+), 3 deletions(-)
src/arch/x86/isa/microops/regop.isa |
changeset 2529aeaf1a1c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2529aeaf1a1c
description:
X86: Make conditional moves zero extend their 32 bit destinations
always.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |
changeset 62caded62b27 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=62caded62b27
description:
Merge with head.
diffstat:
1 file changed, 11 insertions(+), 4 deletions(-)
src/mem/slicc/parser/parser.py | 15 +++
diffs (39 lines):
diff -r 2529aeaf1a1c
nathan binkert wrote:
I finally fixed the bug that was making the init scripts segfault. Now
fsck is segfaulting, I believe because it's using a bunch of
unimplemented SIMD/SSE/3dnow/mmx instructions. These are ~ movss,
ucomiss, xorps, cvtsi2ss divss, mulss, addss, cvtss2sd, cvttss2si, and
qemu has a tests directory and in it, there seems to be a pretty
substantial tester for opcodes at least half of those opcodes are
listed.
Yes, thank you. That's been very helpful in general. I think someone
actually recommended it before, but I'd misinterpreted the description
of what was
I tried this with the command:
scons -j 12 DEFAULT=ALPHA_SE
build/LIBRUBY_MOESI_CMP_directory/libm5_opt.so
PROTOCOL=MOESI_CMP_directory RUBY=True USE_MYSQL=No
but it fails with the following:
Error: cannot find variables file
Scons arguments are case-sensitive, and default should be lower case.
I don't know that it's an official convention, but loosely speaking
the all-uppercase arguments are m5 configuration switches, while the
lowercase ones control scons (or the build process) itself (the only
other one I can think
Great, thanks Steve.
On Wed, Aug 5, 2009 at 12:20 PM, Steve Reinhardtste...@gmail.com wrote:
Scons arguments are case-sensitive, and default should be lower case.
I don't know that it's an official convention, but loosely speaking
the all-uppercase arguments are m5 configuration switches,
nathan binkert wrote:
qemu has a tests directory and in it, there seems to be a pretty
substantial tester for opcodes at least half of those opcodes are
listed.
Yes, thank you. That's been very helpful in general. I think someone
actually recommended it before, but I'd misinterpreted
changeset 4e66dd2decd7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4e66dd2decd7
description:
slicc: generate html by default
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/mem/protocol/SConscript |2 +-
diffs (12 lines):
diff -r a790c9501c9f -r
changeset 5670eee2a866 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5670eee2a866
description:
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized
controllers
This changeset contains a lot of different changes that are too
mingled to
changeset 26abdfe2d980 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=26abdfe2d980
description:
ruby: made mapAddressToRange based off a bit count
diffstat:
3 files changed, 20 insertions(+), 19 deletions(-)
src/mem/protocol/MOESI_CMP_directory-L1cache.sm|
changeset e983bc0f31a0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e983bc0f31a0
description:
protocol: made MI_example dma mapping generic
diffstat:
1 file changed, 9 insertions(+), 50 deletions(-)
src/mem/protocol/MI_example-dir.sm | 59
changeset e76348cb11de in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e76348cb11de
description:
ruby: configuration supports multiple runs in same session
These changes allow to run Ruby-gems multiple times from the same
ruby-lang script with different
Quoting nathan binkert n...@binkert.org:
Yes and yes. All the bugs I fixed last night I found with a massaged
version of the main test program from there and more will be coming. I'm
definitely planning on using it as a regression in SE, and also as the
program to run in FS once the kernel is
The changes I pushed already mostly fix condition codes on existing
instructions, plus rotates by more than the width of the target, plus
a few minor fixes to multiply related microops. Moving forward in the
short term, division instructions aren't getting the answers they
should, and the
Quoting nathan binkert n...@binkert.org:
The changes I pushed already mostly fix condition codes on existing
instructions, plus rotates by more than the width of the target, plus
a few minor fixes to multiply related microops. Moving forward in the
short term, division instructions aren't
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