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This patch has all the functionality we need. Also I really like the
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Ship it!
This looks fine to me. I assume that if a controller doesn't
, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
garnet: added network ptr to links to be used by orion
Diffs
-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 3f37cc5d25bc
src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
orion: bug fix in link power, and some reorg
Diffs
-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 3f37cc5d25bc
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh 3f37cc5d25bc
:
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(Updated 2011-05-16 15:06:16)
Review request for Default, Nathan Binkert, Korey Sewell, and Brad Beckmann
/
---
(Updated 2011-05-08 23:08:23)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
garnet: rename and rearrange config parameters
Renamed (message
On 2011-05-03 17:45:41, Brad Beckmann wrote:
Can we change the name of Time in base/time.hh instead of Time in Ruby?
Right now this patch touches 50+ Ruby files and a bunch of lines within
those files just to change Time to RTime. It seems that far fewer changes
would be required
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Ship it!
I'm surprised this wasn't fixed earlier. Thanks for do this
On 2011-05-03 17:45:41, Brad Beckmann wrote:
Can we change the name of Time in base/time.hh instead of Time in Ruby?
Right now this patch touches 50+ Ruby files and a bunch of lines within
those files just to change Time to RTime. It seems that far fewer changes
would be required
/
---
(Updated 2011-04-29 15:58:51)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
network: added Torus and Pt2Pt topologies
Diffs
-
src/mem/ruby/network/topologies/Pt2Pt.py PRE-CREATION
src/mem/ruby
request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
NetworkTest: added sim_cycles parameter to the network tester.
The network tester terminates after injecting for sim_cycles
(default=1000), instead of having to explicitly
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Can we change the name of Time in base/time.hh instead of Time in Ruby?
changeset 7c377f5162f8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7c377f5162f8
description:
network: basic link bw for garnet and simple networks
This patch ensures that both Garnet and the simple networks use the bw
value
specified in the
changeset f113f73dd494 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f113f73dd494
description:
network: removed the unused network-wide latency param
diffstat:
src/mem/ruby/network/Network.cc | 1 -
src/mem/ruby/network/Network.hh | 2 --
changeset 39e42ccddd63 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=39e42ccddd63
description:
network: adjusted default endpoint bandwidth
The simple network's endpoint bandwidth value is used to adjust the
overall
bandwidth of the network.
changeset 89d0e7c17d1e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=89d0e7c17d1e
description:
garnet: removed flit_width from Routers
diffstat:
src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py | 1 -
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---
(Updated 2011-04-27 10:32:08.616217)
Review request for Default, Ali Saidi, Gabe
---
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http://reviews.m5sim.org/r/661/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
---
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http://reviews.m5sim.org/r/662/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
---
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---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
---
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---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
10:38:47, Brad Beckmann wrote:
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---
(Updated 2011-04-27 10:38:47)
Review
e-mail. To reply, visit:
http://reviews.m5sim.org/r/660/
---
(Updated 2011-04-25 16:18:04)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
NetworkTest
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
On 2011-04-13 10:28:08, Brad Beckmann wrote:
src/mem/protocol/MESI_CMP_directory-L1cache.sm, line 141
http://reviews.m5sim.org/r/611/diff/6/?file=11548#file11548line141
Why are you adding this function? SLICC already generates a similar
function: getPermission
On 2011-04-13 10:28:08, Brad Beckmann wrote:
src/mem/protocol/MESI_CMP_directory-L1cache.sm, line 141
http://reviews.m5sim.org/r/611/diff/6/?file=11548#file11548line141
Why are you adding this function? SLICC already generates a similar
function: getPermission
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Ship it!
Just a few minor alignment requests. Other than that, it
On 2011-04-13 10:28:08, Brad Beckmann wrote:
src/mem/protocol/MESI_CMP_directory-L1cache.sm, line 141
http://reviews.m5sim.org/r/611/diff/6/?file=11548#file11548line141
Why are you adding this function? SLICC already generates a similar
function: getPermission
. To reply, visit:
http://reviews.m5sim.org/r/637/
---
(Updated 2011-04-11 12:06:10)
Review request for Default and Brad Beckmann.
Summary
---
Cache warmup: fixed compile errors in Brad's cache warmup patches
Diffs
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Overall, this seems pretty straightforward. However I'm confused by the
changeset 02cb69e5cfeb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=02cb69e5cfeb
description:
ruby: fixes to support more types of RubyRequests
diffstat:
src/mem/ruby/system/Sequencer.cc | 9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diffs (40
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src/mem/ruby/system/DirectoryMemory.py
On 2011-03-31 22:08:21, Brad Beckmann wrote:
This looks great, I just have a few minor suggestions below.
It seems like the next step is to figure out how to deal with functional
accesses not succeeding in the CPUs and devices.
Nilay Vaish wrote:
Brad, I would make the changes
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Hi Nilay,
Comments below. I might be missing something, but the
On 2011-03-31 11:11:03, Brad Beckmann wrote:
src/mem/ruby/system/RubyPort.cc, line 321
http://reviews.m5sim.org/r/611/diff/2/?file=11382#file11382line321
This loop is probably the most complicated and important part of this
patch. It might be easiest if we move
changeset aeec9e157d06 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aeec9e157d06
description:
hammer: fixed dma uniproc error
Fixed an error reguarding DMA for uninprocessor systems. Basically
removed an
overly agressive optimization that lead to
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---
Hi Nilay,
First, thanks for your patience. Sorry I wasn't able to
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Ship it!
- Brad
On 2011-03-31 12:16:27, Lisa Hsu wrote:
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---
src/mem/slicc/symbols/StateMachine.py
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Ship it!
- Brad
On 2011-03-31 12:20:59, Lisa Hsu wrote:
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---
Ship it!
Other than Nilay's comments, this looks good to me.
- Brad
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Ship it!
- Brad
On 2011-03-31 14:26:33, Lisa Hsu wrote:
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---
This is more of a question, then a suggestion. Is there a way to use
On 2011-03-31 11:11:03, Brad Beckmann wrote:
src/mem/ruby/system/RubyPort.cc, line 321
http://reviews.m5sim.org/r/611/diff/2/?file=11382#file11382line321
This loop is probably the most complicated and important part of this
patch. It might be easiest if we move
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This looks great, I just have a few minor suggestions below.
It seems
changeset d8587c913ccf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d8587c913ccf
description:
ruby: fixed cache index setting
diffstat:
configs/ruby/MESI_CMP_directory.py | 17 +++--
configs/ruby/MI_example.py | 4 +++-
/
---
(Updated 2011-03-23 22:28:01)
Review request for Default and Brad Beckmann.
Summary
---
my initial implementation of cache flushing
Diffs
-
configs/example/ruby_random_test.py baf4b5f6782e
src/cpu/testers/rubytest/Check.hh baf4b5f6782e
src/cpu/testers
On 2011-03-24 08:58:15, Brad Beckmann wrote:
src/mem/ruby/system/Sequencer.cc, line 541
http://reviews.m5sim.org/r/552/diff/6/?file=11209#file11209line541
I thought we concluded that Flush requests can callback the RubyPort?
As long as needsResponse is set to false, the cpu
. To reply, visit:
http://reviews.m5sim.org/r/552/
---
(Updated 2011-03-24 17:17:59)
Review request for Default and Brad Beckmann.
Summary
---
my initial implementation of cache flushing
Diffs
-
configs/example
/
---
(Updated 2011-03-22 19:33:58)
Review request for Default and Brad Beckmann.
Summary
---
my initial implementation of cache flushing
Diffs
-
src/cpu/testers/rubytest/Check.hh baf4b5f6782e
src/cpu/testers/rubytest/Check.cc baf4b5f6782e
, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called
---
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---
Ship it!
- Brad
On 2011-03-20 10:53:10, Nilay Vaish wrote:
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---
Ship it!
- Brad
On 2011-03-18 21:55:58, Nilay Vaish wrote:
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---
Ship it!
- Brad
On 2011-03-18 21:55:08, Nilay Vaish wrote:
changeset d2cf4b19e8ad in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d2cf4b19e8ad
description:
MOESI_CMP_directory: significant dma bug fixes
diffstat:
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 67 -
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
changeset 519fba665871 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=519fba665871
description:
MOESI_hammer: fixed dma bug with shared data
diffstat:
src/mem/protocol/MOESI_hammer-cache.sm | 35 +
src/mem/protocol/MOESI_hammer-dir.sm
changeset de9e34de70ff in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=de9e34de70ff
description:
slicc: improved invalid transition message
diffstat:
src/mem/slicc/symbols/StateMachine.py | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diffs (14 lines):
changeset 0b3252d3b400 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0b3252d3b400
description:
ruby: added useful dma progress dprintf
diffstat:
src/mem/ruby/system/DMASequencer.cc | 5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diffs (15 lines):
diff
changeset ebb373fcb206 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ebb373fcb206
description:
RubyPort: minor fixes to trace flag and dprintfs
diffstat:
src/mem/SConscript | 4 ++--
src/mem/ruby/system/RubyPort.cc | 30 +++---
changeset 5f69f1b0039e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5f69f1b0039e
description:
Ruby: dma retry fix
This patch fixes the problem where Ruby would fail to call sendRetry on
ports
after it nacked the port. This patch is particularly
changeset 19a654839a04 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19a654839a04
description:
MOESI_hammer: minor fixes to full-bit dir
diffstat:
src/mem/protocol/MOESI_hammer-dir.sm | 8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diffs (39 lines):
---
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Ship it!
- Brad
On 2011-03-16 10:58:50, Steve Reinhardt wrote:
, Nathan
Binkert, and Brad Beckmann.
Summary
---
This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also
, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
This patch makes garnet use the info about active and inactive vnets during
allocation and power estimations etc
Diffs
-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 6c9b532da0a6
src
/r/552/
---
(Updated 2011-03-13 19:50:32)
Review request for Default and Brad Beckmann.
Summary
---
my initial implementation of cache flushing
Diffs
-
src/cpu/testers/rubytest/Check.hh baf4b5f6782e
src
/
---
(Updated 2011-03-11 09:33:50)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
This patch adds the network tester for simple and garnet networks
for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan
Binkert, and Brad Beckmann.
Summary
---
MOESI_hammer: adding cache flushing
This patch adds cache flushing to MOESI_hammer. In order to flush a
cache line, a FLUSH request is issued. Flushing is basically a store to
a line
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Do you have to always call wakeUpAllDependents? Initially it atleast was
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Ship it!
- Brad
On 2011-03-01 13:31:45, Nilay Vaish wrote:
---
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---
Ship it!
- Brad
On 2011-02-25 08:33:43, Nilay Vaish wrote:
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---
Ship it!
- Brad
On 2011-02-25 08:32:18, Nilay Vaish wrote:
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---
Ship it!
- Brad
On 2011-02-25 10:51:09, Nilay Vaish wrote:
---
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---
Ship it!
- Brad
On 2011-02-25 10:51:51, Nilay Vaish wrote:
changeset bba14984f2ce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bba14984f2ce
description:
ruby: removed unsupported protocol files
diffstat:
src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm | 894 ---
src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
changeset d1bb88080be4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d1bb88080be4
description:
ruby: cleaned up access permission enum
diffstat:
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 2 +-
src/mem/protocol/RubySlicc_Exports.sm | 20
changeset d1eb504fd302 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d1eb504fd302
description:
MOESI_hammer: cache probe address clean up
diffstat:
src/mem/protocol/MOESI_hammer-cache.sm | 46 +++--
src/mem/slicc/ast/LocalVariableAST.py
changeset bf0335d98250 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bf0335d98250
description:
ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the
changeset 3be28ebdb07f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3be28ebdb07f
description:
regress: MOESI_hammer memtest updates
diffstat:
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats |
990 +-
changeset c7f591ccf3a1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c7f591ccf3a1
description:
MOESI_hammer: fixed wakeup for SS-S transistion
diffstat:
src/mem/protocol/MOESI_hammer-cache.sm | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diffs (19
---
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---
Ship it!
- Brad
On 2011-02-22 13:11:15, Korey Sewell wrote:
---
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http://reviews.m5sim.org/r/496/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/495/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/494/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
---
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---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
---
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---
Ship it!
- Brad
On 2011-02-18 14:55:40, Korey Sewell wrote:
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Overall, this looks great. A pretty simple change that offers
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Overall, this patch looks good to me as well. I just have a couple minor
changeset d6294150a32e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d6294150a32e
description:
ruby: removed duplicate make response call
diffstat:
src/mem/ruby/system/RubyPort.cc | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diffs (11 lines):
diff -r
changeset bb6411d45356 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bb6411d45356
description:
config: fixed minor bug connecting dma devices to ruby
diffstat:
configs/common/FSConfig.py | 3 +++
configs/example/ruby_fs.py | 12 +---
2 files changed, 8
changeset 685719afafe6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=685719afafe6
description:
memtest: due to contention increase, increased deadlock threshold
diffstat:
configs/example/ruby_mem_test.py | 6 ++
tests/configs/memtest-ruby.py| 6 ++
2
changeset 48d31b577847 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=48d31b577847
description:
x86: set IsCondControl flag for the appropriate microops
diffstat:
src/arch/x86/isa/microops/regop.isa | 28 +++-
changeset 6f5299ff8260 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6f5299ff8260
description:
MOESI_hammer: Added full-bit directory support
diffstat:
configs/ruby/MOESI_hammer.py |7 +-
src/mem/protocol/MOESI_hammer-cache.sm | 20 ++-
changeset 5ccd97218ca0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5ccd97218ca0
description:
ruby: Assert for x86 misaligned access
This patch ensures only aligned access are passed to ruby and includes
a fix
to the DPRINTF address print.
diffstat:
changeset 00ad807ed2ca in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=00ad807ed2ca
description:
ruby: x86 fs config support
diffstat:
configs/common/FSConfig.py | 52 +
configs/example/ruby_fs.py | 26
changeset 8a92b39be50e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8a92b39be50e
description:
ruby: Fix RubyPort to properly handle retrys
diffstat:
src/mem/ruby/system/RubyPort.cc | 29 +
src/mem/ruby/system/RubyPort.hh | 25
changeset 70b56a9ac1b2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=70b56a9ac1b2
description:
dev: fixed bugs to extend interrupt capability beyond 15 cores
diffstat:
src/arch/x86/interrupts.cc | 7 +++
src/dev/x86/i82094aa.cc| 22 ++
changeset eee5bb0fb8ea in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=eee5bb0fb8ea
description:
m5: added work completed monitoring support
diffstat:
configs/common/FSConfig.py| 19 -
configs/common/Options.py | 14 +++
changeset bc39c93a5519 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bc39c93a5519
description:
mem: Added support for Null data packet
The packet now identifies whether static or dynamic data has been
allocated and
is used by Ruby to determine whehter
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