This is a classic Spice error!
I often run into this if I don't have a DC path to a node, to allow
initial conditions to stablise. My first approach to solving this
issue is to add a 100megohm or larger resistor across the capacitor
(which is usually the cause of the error).
Hope this helps.
Jo
Hi Tim,
I don't use the Protel simulator (yet?), but do use Electronic Workbench
(Multisim), and have found their website>>free technical support, to be
helpful with finding ways to eliminate errors during simulation.
Maybe there are some tips there that could apply to the spice models in the
Mark E Witherite wrote:
> That's a bad assumption. This last year
> I learned that a board house is only as good as it's production
> employees. a company that was once a NASA's top ten list, sent me batch of
> boards with two nets shorted. And yes they were ordered with bed of nails
> testi
Bill,
my guess would be that a couple of members of the server list got
hit by a virus over the weekend. These emails look like the result a that
virus indiscriminately mailing itself out to previously received email
sources.
Sincerely,
Brad Velander.
Lead PCB Designer
Norsat Internation
What is this? a new form of SPAM?
- Bill
-Original Message-
From: Bob Jones [mailto:[EMAIL PROTECTED]]
Sent: Monday, April 15, 2002 9:12 AM
To: Protel EDA Forum
Subject: [PEDA] send info.
- Original Message -
From: "Carl Schattke" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[E
Seems like you need to go into youe "mouse properties" and adjust the
parameters for the speed of the "mouse click" (sometimes called "double
click")
Different types of software call it different things, but you should be
able to adjust it.
It appears that you need to slow it down.
There are so
- Original Message -
From: "Carl Schattke" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Sunday, April 14, 2002 8:25 PM
Subject: Re: [PEDA] Protel and Windows XP
> Greetings!
>
> You are receiving this letter because you have expressed an interest in
> receiving i
The circuit I am simulating simulates fine with a ua741 sim device but when
I attempt to sim with the subckt model from the TI website for the OPA548, I
get the "timestep too small" error. My recollection is that this is caused
by too high a transient on startup (fails in the GMIN stepping) for t
Well, I had decided to "kill the job", and get on with life. So I started
pruning out processes with the TM to see if I could jump start it (something
blocking, maybe?) but nothing would liven up Protel again. So I decided the
next must reliable way to get a clean exit from a hung app was the "S
On 06:55 AM 15/04/2002 -0500, Tim Hutcheson said:
>Thanks, Ian, but I can't even see the toolbar anymore because Protel never
>regains the focus again and other windows which are no longer repainted
>correctly partially obliterate the remnants of the original window.
>Eventually (by this morning)
Thanks, Ian, but I can't even see the toolbar anymore because Protel never
regains the focus again and other windows which are no longer repainted
correctly partially obliterate the remnants of the original window.
Eventually (by this morning) even all evidence of the original window have
disappea
The only problem I've had on top overlay is when a feature (e.g. horizontal
line) comes out narrower than the silkscreen will cope with. This was using
3x magnification to generate the Protel file, resulting in 3mil tracks. In
this case, increasing the offending tracks to 6mil produced a printab
My current design has the following rule
clearance (Board) to (Board) Different Nets Gap 7mil
but for manufacturing purpose i need an additional rule
clearance (Smd Pad) to (Smd Pad, Via) Any Net Gap 10mil
both rules are marked as Rule Followed by Router in P99SE SP6 but in fact
the router ign
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