Re: [PEDA] spacebar doesn't rotate components anymore
At 02/06/2003 10:19, I wrote: Hi folks, leave it to Leo to crash into weird stuff: the PCB editor refuses to rotate components when I press the spacebar. snippety-snip I am convinced I messed something up, but what? To somewhat answer my own question: I renamed the AdvPCB99SE.INI and restarted Protel. It works again! Those INI files are magical files!! I tried looking at the file in detail, but could not find obvious faults. Most of it is fairly straightforward though, that enabled me to recover some of the settings (colours mostly). Oh well. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] spacebar doesn't rotate components anymore
At 02/06/2003 11:00, Mattias wrote: I believe that the component drag setting may influence this behavior too if I remember correctly. Try to change that setting under preferences. BINGO. That was the culprit. Thanks! Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] spacebar doesn't rotate components anymore
They are, and they aren't They are, because a whole lot of inexplicable problems beyond the standard plethora of inexplicable problems with Protel EDA can be traced right back to the often inexplicable and all too common corruption of the file(s) They aren't because they are often corrupted and result in inexplicable problems AND because they don't contain a host of elements which other programs use to allow the user control over default program behaviors. aj - When in doubt, delete the ini files and then, iffn and after the app comes back, just rebuild your entire customization scheme. Just like magic, with only five timez the work! From: Leo Potjewijd [mailto:[EMAIL PROTECTED] At 02/06/2003 10:19, I wrote: Hi folks, leave it to Leo to crash into weird stuff: the PCB editor refuses to rotate components when I press the spacebar. snippety-snip I am convinced I messed something up, but what? To somewhat answer my own question: I renamed the AdvPCB99SE.INI and restarted Protel. It works again! Those INI files are magical files!! I tried looking at the file in detail, but could not find obvious faults. Most of it is fairly straightforward though, that enabled me to recover some of the settings (colours mostly). Oh well. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] eight-layer stackup
Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
oops I mean four internal planes, two being power and two being ground planes.. sorry -Original Message- From: Michael Biggs [mailto:[EMAIL PROTECTED] Sent: Monday, June 02, 2003 3:21 PM To: 'Protel EDA Forum' Subject: [PEDA] eight-layer stackup Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
I'd probably do it this way (top to bottom): sig gnd1 pwr1 sig sig gnd2 pwr2 sig Assumptions: your highest-speed parts are on the top side. gnd1 and pwr1 are your main power rails for the highest-speed parts. Whatever you do, keep each gnd plane and it's matching pwr plane adjacent to each other - the distributed capacitance of this arrangement helps in decoupling the supply rails. This is in addition to your decoupling caps, not to replace them. I don't have anything to say about the dogbones. I'm still using cat treats... Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Michael Biggs [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Monday, June 02, 2003 4:20 PM Subject: [PEDA] eight-layer stackup Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Mechanical symbol?
Natalie, While some prefer to do something like that in another package, such as AutoCad, there are those that like to do it here in Protel 99 SE I know a number of people wo use one of the mechanical Layers as a PWB Detail (Fab Dwg), by putting on a Border and Title Block and Standard Notes, and just using that as the startup template for any new board. When you use the PCB Wizard in Protel 99 SE to create a new job (after creating a new file, rightclick on the background in your main window of your new .ddb and select New . . . and then select the Wizards Tab and then doubleclick on Printed Circuit Board Wizard), the Wizard itself uses templates to generate a new PCB document for you. These templates are stored in a database called templates.ddb located in your Program Files\Design Explorer 99 SE\System directory. You can modify an existing template to suit your needs, or make a new one of your own. I can't remember all of the details involved in setting up your own template, but possibly others in the forum can help you there. The only thing you I would say that you have to watch out for here is the size of the negatives since your board shop might generate film the size of your complete drawing and charge you for it if you have that layer turned on when you generate your Gerbers. Hope that this is of some help. JaMi * * * * * * * * * - Original Message - From: Natalie DeGennaro [EMAIL PROTECTED] Cc: [EMAIL PROTECTED] Sent: Thursday, May 29, 2003 10:16 AM Subject: [PEDA] Mechanical symbol? Hi, I am a newbie to this group, having just started learning Protel DXP. But I am a senior designer having used other software. I would like to make my fabrication notes (and possibly my fab drawing title block) into a symbol I can call in on every board. Is this possible on this software? From what I read in the Help section, all components have to have a pin definition in them. I don't want pins, I just want dummy text and lines in the shape of a Titleblock and notes. Is this possible? I can make a DXF file to do this but I would rather have a symbol to call in. Thanks for all help, Natalie [EMAIL PROTECTED] 04/22/03 06:36 AM To: [EMAIL PROTECTED]@Internet cc: (bcc: Natalie DeGennaro/Americas/NSC) Subject:Re: [PEDA] Import PCB Leo- May be that the Gerbers are RS274 rather than RS274X. For RS274, Protel needs to have the Aperture file loaded before importing the Gerbers themselvesotherwise, you get a black screen after the Gerber load. Aperture list must be in the bundle if Camtastic is finding it, tho the file extension may not be .apt. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
MichaelB, While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real net it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. Myself, I have had the very same problem with the identical requirements (needing to take each BGA contact to the back of the board with a via), and I just live with the errors. I have accepted the fact that even if I were to do a perfect board in Protel 99 SE, that there would still be some little DRC error somewhere. Protel DRC just doesn't map to reality in all cases, as there is always some need for some special requirement that Protel just can't handle, so you look at the DRC error, and accept it as is, and live with the error in the report file and that little iridescent glow here and there on the on the screen. I find that the trick for me is to reset the errors once I have examined them, and that way they are not just sitting there staring me in the face as I continue working on the design. Respecting the layer stack up, I myself would prefer to go with 2 outer routing layers, 2 planes under that on each side, and then another 2 routing layers in the middle. But before you even get that far, I think that you need to ask whether any of the signals may have any special requirements, such as controlled impedance, or matched lengths, or isolation, or the necessity to be routed over a specific plane. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. It may well be that due to the type of signals you are dealing with (LVDS / high speed / controlled impedance / susceptible to crosstalk), you might have to go with isolating the internal signal routing layers as layers 3 and 6 with the two power layers as 4 and 5. What type and size of BGA are you dealing with? Any special routing requirements? JaMi * * * * * * * * * - Original Message - From: Michael Biggs [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Monday, June 02, 2003 1:20 PM Subject: [PEDA] eight-layer stackup Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Michael The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal thou never actually using 8 layers this is all i can give you. Hope it helps. Nathan BTW the reference is PCB design techniques for emc compliance by mark montrose. 2nd Edition Michael Biggs wrote: Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB -- Nathan Horsfield Inspiration Technology P/L Ph: +61 8 8211 9668 Fax: +61 8 8211 9658 www.instech.com.au * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Earth to PEDA
Earth to PEDA . . . Earth to PEDA . . . What's the story on the lightning fast turnaround on the Forum distribution . . . JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
From: JaMi Smith [mailto:[EMAIL PROTECTED] While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real net it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. yeah there is a way: Don't use synchronisation in the ddb, use NETLIST GENERATION and NETLIST LOADING. In the netlist generation in schematic, you can tell it to include unnamed single pin nets. You will then get nets assigned to all your unused pins on your BGA. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. Jeez. How many layers does he have spare for power planes?? my BGA needed 3 of the buggers. Split planes are the only way to go. Just be really careful not to bridge them with a through hole pin like I did... Julian (who got his BGA board not reporting errors, and the BGA part of it is fine) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] metric footprint
Is there no footprint given in a manufacturers datasheet ? It just a minute or two to make this footprint, much faster than a websearch. Rene Tim Fifield wrote: Does anybody have a footprint for a SSOP24-P-300-1.00B? The part is a Toshiba TPD7203F gate driver IC. Pin pitch is 1mm and body with pin width is 8mm. IPC-SM-782 book doesn't have anything and I can't quickly find anything else on the web. I'm going to keep searching but I thought I'd ask here too. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
At 10:57 AM 6/3/2003 +0930, you wrote: Michael The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal thou never actually using 8 layers this is all i can give you. Hope it helps. Out of curiosity, what is the typical textbook stackup for a six-layer board? Do you typically have two signal, two power, two ground planes, or can you have, say, three signals layers and two power and one ground plane? i.e. 1. signal 2. gnd 3. pwr 4. signal 5. pwr 6. signal I would imagine this should be fine if there are no plane splits, save for possibly some on 3, since all signal layers would be directly adjacent to at least one unbroken plane... Or is my thinking flawed on this? Four layer is easy, and eight makes sense... But how do you typically work up the more oddball ones like six or ten or (shudder) even twenty two? I am looking at a design now that I think will probably require at least three signal layers to route, but I think an eight-layer board would be something of an overkill and would like to stick to six. How do folks typically deal with distributing power to parts that require separate core and I/O, maybe different cores for different parts on the board? For instance, multiple FPGAs that require a 2.5v core and 3.3v IO, and a DSP which requires a 1.8v core and 3.3v IO? Obviously 3.3v should probably have it's own power plane across the board, but can you take an inner power layer (like #3 in the above example) and split it between 1.8v and 2.5v as needed to source the core voltages as and where needed? I've done four layer boards fine this far; my approach (under QFP FPGAs that required 2.5v core and 3.3v IO) was to pour a polygon-plane on the top signal layer under the chip, and to connect this to all of the necessary pins, decouple the living daylights out of it, and then run a very fat trace on the back of the board over to the 2.5v regulator. It seems to have worked just fine on the latest run of boards - very clean power being supplied to all of the core pins - but I'm always interested in other's approaches that may be better suited to these kinds of situations. Someone really needs to write a modern 'style guide' to multilayer PCB layout, y'know? Not just the math and theory covered in several of the better books out there, but one also covering component layout techniques, approaches to signal and bus routing, shapes and patterns of via layout for moving busses from one layer to the other nicely, how to route *special* signals (differential, controlled impedance, matched length, etc), how to efficiently break out BGAs, and so forth. Certainly would make life a little easier for us newbies! :D Regards, -- Matt * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] metric footprint
Try: http://tsc.jeita.or.jp/eds/DATA/PACKAGE/ED731120.PDF John Haddy -Original Message- From: Rene Tschaggelar [mailto:[EMAIL PROTECTED] Sent: Tuesday, 3 June 2003 6:51 PM To: Protel EDA Forum Subject: Re: [PEDA] metric footprint Is there no footprint given in a manufacturers datasheet ? It just a minute or two to make this footprint, much faster than a websearch. Rene Tim Fifield wrote: Does anybody have a footprint for a SSOP24-P-300-1.00B? The part is a Toshiba TPD7203F gate driver IC. Pin pitch is 1mm and body with pin width is 8mm. IPC-SM-782 book doesn't have anything and I can't quickly find anything else on the web. I'm going to keep searching but I thought I'd ask here too. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
If you used the construction you suggest you'd encounter a problem with copper balance. It would appear either during board manufacture or reflow, or both. The mass of copper on 2/3 is different to 4/5 so the board will be badly bent or twisted. (The coefficient of expansion of copper is different to prepreg and FR4). The forces generated on a layer during heating depend on the density of copper in any given area. If you want a guide to PCB lay-up, I suggest you talk to your board house. Ours publishes a really useful guide, see www.graphic.plc.uk Each houses capabilities differ depending on their techniques and equipment, though there are general industry and practical rules too. Jason. -Original Message- From: Matt Polak [mailto:[EMAIL PROTECTED] Sent: 03 June 2003 10:12 To: Protel EDA Forum Subject: Re: [PEDA] six or eight-layer (or more?) stackups At 10:57 AM 6/3/2003 +0930, you wrote: Michael The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal thou never actually using 8 layers this is all i can give you. Hope it helps. Out of curiosity, what is the typical textbook stackup for a six-layer board? Do you typically have two signal, two power, two ground planes, or can you have, say, three signals layers and two power and one ground plane? i.e. 1. signal 2. gnd 3. pwr 4. signal 5. pwr 6. signal I would imagine this should be fine if there are no plane splits, save for possibly some on 3, since all signal layers would be directly adjacent to at least one unbroken plane... Or is my thinking flawed on this? Four layer is easy, and eight makes sense... But how do you typically work up the more oddball ones like six or ten or (shudder) even twenty two? I am looking at a design now that I think will probably require at least three signal layers to route, but I think an eight-layer board would be something of an overkill and would like to stick to six. How do folks typically deal with distributing power to parts that require separate core and I/O, maybe different cores for different parts on the board? For instance, multiple FPGAs that require a 2.5v core and 3.3v IO, and a DSP which requires a 1.8v core and 3.3v IO? Obviously 3.3v should probably have it's own power plane across the board, but can you take an inner power layer (like #3 in the above example) and split it between 1.8v and 2.5v as needed to source the core voltages as and where needed? I've done four layer boards fine this far; my approach (under QFP FPGAs that required 2.5v core and 3.3v IO) was to pour a polygon-plane on the top signal layer under the chip, and to connect this to all of the necessary pins, decouple the living daylights out of it, and then run a very fat trace on the back of the board over to the 2.5v regulator. It seems to have worked just fine on the latest run of boards - very clean power being supplied to all of the core pins - but I'm always interested in other's approaches that may be better suited to these kinds of situations. Someone really needs to write a modern 'style guide' to multilayer PCB layout, y'know? Not just the math and theory covered in several of the better books out there, but one also covering component layout techniques, approaches to signal and bus routing, shapes and patterns of via layout for moving busses from one layer to the other nicely, how to route *special* signals (differential, controlled impedance, matched length, etc), how to efficiently break out BGAs, and so forth. Certainly would make life a little easier for us newbies! :D Regards, -- Matt * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Mechanical symbol?
Natalie, Wasn't till I got a copy of my own post back that I realized you were talking about Protel DXP as opposed to Protel 99 SE. I am asleep at the switch today, and assumed that because you posted to the Protel List instead of the DXP List that you were talking about Protel 99 SE, and read the DXP in your post as DXF. Sorry about that. Notwithstanding my blunder, I believe that everything I said below is also applicable to Protel DXP, with the exception that the templates.ddb file will now be located in the \Program Files\Altium\System directory. If you are not aware of the DXP Technical Forum, you can find it at: == http://forums.altium.com . JaMi - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Monday, June 02, 2003 5:58 PM Subject: Re: [PEDA] Mechanical symbol? Natalie, While some prefer to do something like that in another package, such as AutoCad, there are those that like to do it here in Protel 99 SE I know a number of people wo use one of the mechanical Layers as a PWB Detail (Fab Dwg), by putting on a Border and Title Block and Standard Notes, and just using that as the startup template for any new board. When you use the PCB Wizard in Protel 99 SE to create a new job (after creating a new file, rightclick on the background in your main window of your new .ddb and select New . . . and then select the Wizards Tab and then doubleclick on Printed Circuit Board Wizard), the Wizard itself uses templates to generate a new PCB document for you. These templates are stored in a database called templates.ddb located in your Program Files\Design Explorer 99 SE\System directory. You can modify an existing template to suit your needs, or make a new one of your own. I can't remember all of the details involved in setting up your own template, but possibly others in the forum can help you there. The only thing you I would say that you have to watch out for here is the size of the negatives since your board shop might generate film the size of your complete drawing and charge you for it if you have that layer turned on when you generate your Gerbers. Hope that this is of some help. JaMi * * * * * * * * * - Original Message - From: Natalie DeGennaro [EMAIL PROTECTED] Cc: [EMAIL PROTECTED] Sent: Thursday, May 29, 2003 10:16 AM Subject: [PEDA] Mechanical symbol? Hi, I am a newbie to this group, having just started learning Protel DXP. But I am a senior designer having used other software. I would like to make my fabrication notes (and possibly my fab drawing title block) into a symbol I can call in on every board. Is this possible on this software? From what I read in the Help section, all components have to have a pin definition in them. I don't want pins, I just want dummy text and lines in the shape of a Titleblock and notes. Is this possible? I can make a DXF file to do this but I would rather have a symbol to call in. Thanks for all help, Natalie * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups
Matt Polak wrote: At 10:57 AM 6/3/2003 +0930, you wrote: Michael The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal thou never actually using 8 layers this is all i can give you. Hope it helps. Out of curiosity, what is the typical textbook stackup for a six-layer board? Do you typically have two signal, two power, two ground planes, or can you have, say, three signals layers and two power and one ground plane? i.e. 1. signal 2. gnd 3. pwr 4. signal 5. pwr 6. signal I would imagine this should be fine if there are no plane splits, save for possibly some on 3, since all signal layers would be directly adjacent to at least one unbroken plane... Or is my thinking flawed on this? Four layer is easy, and eight makes sense... But how do you typically work up the more oddball ones like six or ten or (shudder) even twenty two? I am looking at a design now that I think will probably require at least three signal layers to route, but I think an eight-layer board would be something of an overkill and would like to stick to six. How do folks typically deal with distributing power to parts that require separate core and I/O, maybe different cores for different parts on the board? For instance, multiple FPGAs that require a 2.5v core and 3.3v IO, and a DSP which requires a 1.8v core and 3.3v IO? Obviously 3.3v should probably have it's own power plane across the board, but can you take an inner power layer (like #3 in the above example) and split it between 1.8v and 2.5v as needed to source the core voltages as and where needed? I've done four layer boards fine this far; my approach (under QFP FPGAs that required 2.5v core and 3.3v IO) was to pour a polygon-plane on the top signal layer under the chip, and to connect this to all of the necessary pins, decouple the living daylights out of it, and then run a very fat trace on the back of the board over to the 2.5v regulator. It seems to have worked just fine on the latest run of boards - very clean power being supplied to all of the core pins - but I'm always interested in other's approaches that may be better suited to these kinds of situations. Someone really needs to write a modern 'style guide' to multilayer PCB layout, y'know? Not just the math and theory covered in several of the better books out there, but one also covering component layout techniques, approaches to signal and bus routing, shapes and patterns of via layout for moving busses from one layer to the other nicely, how to route *special* signals (differential, controlled impedance, matched length, etc), how to efficiently break out BGAs, and so forth. Certainly would make life a little easier for us newbies! :D Regards, -- Matt the main issue with an odd number of plane is the PCB becomes unbalenced and so is more likely to warp. with the 6 layer setup suggested this should not be to bad but could cause issues, particularly if the middle sugnal layer is lightly used. If you are using a layup where you have an od number of planes then it can often be worth adding some ground flods to the appropriate signal layer to help with the copper balence * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
