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One colour variation I use a lot is, set classic colours, set all layer
colours to half brighness and transparent mode on.
The when you select a net (or connected copper) its route across all layers
can be easily seen.
> -Original Message-
> From: Geoff Harland [mailto:[EMAIL PROTECTED]
>Here it is!
>
>The QFP & TSOP footprint generator which works with the actual measurements
provided
>by you IC manufactures data sheets.
I have tried your QFP footprint generator and I think I found a bug. Sorry!
I used it to create a footprint for a 144 pin TQFP and in metric mode the
pads are
Hi
Can anyone tell me how to place a component on to a schematic without being
on a pcb and vica versa? (using syncronizer on Protel 99SESP6)
ie. on a scematic I have symbols in the library for safety critical
information etc by certain components. info only, no footprint. however
(D)esign/Up
In message <[EMAIL PROTECTED]>, Emanuel Zimmermann
<[EMAIL PROTECTED]> writes
>David,
>
>Let your board house do it for you! I also have toyed with this and, if you
>really want to do it yourself, can recommend to use Camtastic for it rather
>than Protel. But keep in mind, that it is hard work to
On 10:17 AM 22/08/2001 +0100, Richard Thompson said:
>Hi
>Can anyone tell me how to place a component on to a schematic without being
>on a pcb and vica versa? (using syncronizer on Protel 99SESP6)
>
>ie. on a scematic I have symbols in the library for safety critical
>information etc by certain
To verify the error:
Yikes, you are correct...
This is not a bug with the Script in general, but a bug with the Dialog Box.
Try:
36, 22.0, 0, 36, 22.0, 0.5, 0.27, 0.75, 1, 2, 0.04, 0 -> metric
All I changed was the 22 -> 22.0
This will work fine, but I am not sure why the dialog box converts
Here it is, Version 1.1.
New in version 1.1: Fixed numeric entry in the dialog boxes. Some integers were
being multiplied by 10.
The QFP & TSOP footprint generator which works with the actual measurements provided
by you IC manufactures data sheets.
Just copy this link location into your inter
> Beside the gerber-files, the manufacturer wants us to deliver a netlist
in
> the IPC-356 or Mentor-Neutral format.
This was talked about a month or two ago. In the Cam manager create a
testpoint output and then select IPC-D-356A. Now set the options you want
(I select all of them) and when y
> > Beside the gerber-files, the manufacturer wants us to deliver a netlist
> in
> > the IPC-356 or Mentor-Neutral format.
>
>
> This was talked about a month or two ago. In the Cam manager create a
> testpoint output and then select IPC-D-356A. Now set the options you want
> (I select all of the
> Rob,
> Has your board houses had any problems with the IPC-D-356A netlist
generated
> in Protel? I thought there were some problems with Protel's netlist
> generator. I am also getting alot of request for IPC-D-356A netlist
I haven't actually sent them anything since I found it would genera
Protel EDA forum members,
In a P99SE design currently being wrapped up, we have a DRC error that is
something we want to do that generates an error we would like to not get
flagged. It would be good to set a very specific design rule to remove this
DRC
error, but I want to keep from having this n
>
I looked at the files and it is a simple format that they should
> not have problems with (I Hope).
>
> Rob
>
>
I think it was reported that there was a problem with it Rob. I was going
to try a simple design, the next time I have one ( and does not require a
quick turn). While I appreciate
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I would add those pins to the netlist. IOW, add some
wires to those pins on the schematic and bring them
out to either some man made test points (i.e. a part with
one pad); or a header somewhere. Name 'em spare1,
spare2, spare3, etc.
Problem solved.
Jeff Stout
- Original Message -
> everything associated with the unused pads is flagged as a DRC error. My
> desire
> would be to set a design rule where anything associated with these unused
> pads
> is not flagged, but everything else is to prevent missing any real DRC
> errors in
> this design.
>
Ken
Under tools,design r
Has anyone any experience building small (4x7 inch) 7-layer .063" boards? I
would like to have a certain stack up impedance that is best met with
4,9,9,9,9,4 for the 5-mil trace widths I am using but I know from what I
have read that warping can be a problem. On the other hand, a conventional
a
Hello, all:
I am designing a board with a 388 BGA chip. I have questions about vias:
1) Should I tent the vias under the BGA?
2) If (1) is yes, should I tent other vias on the board?
3) If (1) is yes, what substance/method is used to tent vias?
4) If (1) is yes, what do I tell the PCB fab h
Try putting a no-erc directive marker on each unconnected pin. The no-erc
marker looks like a red X.
Best regards,
Ivan Baggett
Bagotronix Inc.
website: www.bagotronix.com
- Original Message -
From: "Ken Pelic" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Cc: "KerryA
Tim,
you have an even/balanced board stack-up as long as the laminate
materials are all the same (i.e. not some bizarre hybrid laminate stackup).
It would seem you are counting copper layers rather then laminate layers,
there is always one additional copper layer because you have copper on
Tim,
Take a look athttp://www.merix.com/resourcecntr/apps/balanced_pcbs.htmlit is an article on
Balanced board stackup... it will explain it best...
Sam Cox...
>
>> -Original Message-
>> From: Tim Hutcheson [mailto:[EMAIL PROTECTED]]
>> Sent: Wednesday, August 22, 2001 10:53
Richard Thompson wrote:
> Hi
> Can anyone tell me how to place a component on to a schematic without being
> on a pcb and vica versa? (using syncronizer on Protel 99SESP6)
>
> ie. on a scematic I have symbols in the library for safety critical
> information etc by certain components. info onl
Ken Pelic wrote:
>
> Here's the scenario:
>
> In BGAs we have in this design, several pads are not used and therefore
> don't
> have any assigned netnames. We want access to them due to this being an
> initial
> prototype design and so we have vias associated with the pads to provide
> access
>
Brad, thanks. Now I know how to count them. :o) And yes the thinner layer
thickness was wrong. I just calculated that if I use
4,13.5,13.5,13.5,13.5,4 and can squeeze 8-mil traces onto the two inner
layers with 5-mil on the outer, everything should match up for a .063 board
with about 55 ohms
Tim,
on your total thickness you seem to be forgetting the copper
thickness. Calculate copper thickness at 1.4mils(36microns)/1oz,
0.7mils(18microns)/0.5oz. The new stackup you refer to would have a total
thickness of 72mils (71.8mils precisely) using 1oz Cu weight.
Laminate: (4x2)
4) If (1) is yes, what do I tell the PCB fab house to get them to tent the
vias? Is it as simple as "tent the vias"?
You select the vias, and check the box marked tenting in their property
page. The Protel won't remove solder mask in the gerber.
Rob
* * * * * * * * * * * * * * * * *
Tim Hutcheson wrote:
> Has anyone any experience building small (4x7 inch) 7-layer .063" boards? I
> would like to have a certain stack up impedance that is best met with
> 4,9,9,9,9,4 for the 5-mil trace widths I am using but I know from what I
> have read that warping can be a problem.
I ha
I'm learning, thanks. I have only just gotten to the point of trying to
understand how the layers are put together. And it is real easy to miss the
practical details.
Tim Hutcheson
Institute for Human and Machine Cognition
40 S. Alcaniz St.
Pensacola, FL. 32503
* * * * * * * * * * * * * * * *
Third try: Using 8-layer board, 4 cores, 4 prepreg and a foil.
Laminate: (4x2) + (8x6) = 56 mils
Copper: 2x(.7+.3) = 2 mils 1/2 oz copper plated to 1.0 for outer layers
Copper: (7x.7) = 4.9 mils inner layer 1/oz copper
Total: 56 + 2 + 4.9 = 62.9mils
Impedance: about 52-54 ohms for FR4, all
Did you try a footprint that is empty ? Could be a mech line only ?
I have schematic components such as M3 because I want to connect
the plated hole to earth.
I also do have heatsinks on the schematic, as component, and
can connect it to whatever
Rene
--
Ing.Buero R.Tschaggelar - http://www.
Tim Hutcheson wrote:
> I'm learning, thanks. I have only just gotten to the point of trying to
> understand how the layers are put together. And it is real easy to miss the
> practical details.
This is somewhat of a problem. Unless you read the trade journals
of the PCB industry, or have do
This is yet another case where the availability of "No-Net" in the design
rule net drop lists would help. At the moment it is not possible to set a
design rule saying that it is OK for a no-net primitive to connect to
another no-net primitive. Hopefully this will be fixed soon as it does
aff
Yes, I understand that problem. As I get closer being certain of the design
issues and the design itself, I will start working with a board vendor
closely to be sure I am specifying something they can build at a reasonable
cost. I am trying to stay in the mainstream of the high end PCB fabricati
On Wed, 22 Aug 2001 16:24:37 -0500, Tim Hutcheson wrote:
>Since my source resistance is 53 ohms, I have less than 2% mismatch.
Just to inject a little reality here. Board houses can not control layer
thickness to anything like 2%. The can mic up the cores and maybe get close
to what you want bu
I can only comment on what I do (with microBGAs: 0.8mm pitch).
I tent everything that's not used as a testpoint. Most particularly,
at the pitch of BGA I'm using, all vias under the BGA are tented.
With the fine pitch BGA, an untented via results in a soldermask
opening that intersects with that
Indeed. But we can only do the calculations for what we have control of, so
that we are in the center of the remaining variance window that we don't
have any/much control of unless we go to expensive processes. Just getting
in the center has been enough challenge for me. :o)
regards,
Tim Hutc
Mr. Baggett,
some answers for your questions 3 and 4.
My experience is either to tent the vias only half or tenting them with
selkscreen (if this is the right word for the lacquer used to show the
component-positions).
1) The first Idea means to use a soldermask covering the pad b
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