Where's the catch in it?
I just went through the online registration process and didn't find
anything fishy (such as an adhesion contract).
I'm curious what will happen...
.
ô ô )
-oOOo--(_)---oOOo--
Ralf Guetlein
Biotest Medizintechnik GmbH
Industriestrasse 1
On 11:59 PM 29/11/2001 -0500, Abd ul-Rahman Lomax said:
>At 11:27 AM 11/30/01 +1100, Michael Beavis wrote:
>>Free pads allow for more powerful design rules to be employed but it is
>>possible to lose them when synchronising from SCH if care is not taken.
>>If the 'Delete component' option is selec
Hi,
I have a problem with vias on a 6 layer board with a stack up like:
T
--P--
1
--C--
2
--P--
3
--C--
4
--P--
B
Among others a via type, from layer 1 to layer 4, witch is depending on the layer
stack, were used. But some of the vias were only connected on layer 1 and layer 3. Our
Matthias,
If you plot the Gerbers with the option "plot holes" checked you will
rub out a 0 mil annular ring as well as a i.e. 0.001 mil (which
satisfies your DRC rule).
So never plot the holes in Gerbers!
Hope this helps,
Emanuel
[EMAIL PROTECTED] wrote:
>
> Hi,
>
> I have a problem with vi
Steve,
We have designed a number of boards with controlled depth holes.
Does your vendor do a quality on this type of hole? If so,
would you mind giving me their name?
Thank you,
Richard
Why would I want to keep extra copper where it's not wanted? Electrically I
might want the copper to separate sensitive areas of a board where a gnd net
was missing. For my purposes I like to keep as much copper on board as
possible. One because it makes my etchant last longer and two because if
Hi,
I am using some logic gates that require a different Vcc value in different
areas of my circuit. For example, a fairchild 74VHC00 that I need 5V at one
location and 3.3V elsewhere.
Since Vcc is a hidden pin it is showing up on the same net. Any way to get
around this in schematic or do I n
If you are using 99SE, place a part and then left click on it. Up pops a
menu. Click on Properties. Then check the Hidden Pins checkbox. This will
make the power pins show on the schematic. Then you can explicity tie them
to any power port you want.
Be careful that when annotation occurs, al
Schematics with hidden powerpins are non-complete documentation and should
be abandoned, - therefore: use only components with visible powerpins !!!
Med venlig hilsen / Best regards from
Peder Hellegaard
Mediatronic
Kisumvej 9
7800 Skive
Denmark
E-mail: [EMAIL PROTECTED]
This was discussed a lot of times here. The best way is, forget the 'hidden'
stuff, change all your parts with the power- pins displayed.
For multiple part components, delete all the hidden power pins on all parts,
draw visible power pins on the first item.
>From now on, you have total control on
On Thu, 29 Nov 2001, Frank Gilley wrote:
> While there surely must be more shapes, sizes, and mountings for LEDs than
> almost any other component, there are quite a few SMT LEDs available in a
> variety of standard footprints like 0603, 0805, 1206, 1210, and SOT-23 just
> to name the more comm
> since they will tend to mount them backwards more often than not, and
Must be a Murphy's Law thing. You would think they would mount them
backwards 50% of the time, not more often. But that's if Murphy isn't
looking ;-)
No matter how many security guards you hire, you can't always keep Murph
Again you are most observant Abd... The problem I encountered was the
removal of the net from the pad used for mounting. And if it was a
component, as many of our older designs were, the macros marked it for
deletion. I believe I was using service pack 5 at the time... I am now using
SP6 and your
Not just 'can' you MUST!
Then you can explicity tie them to any power port you want.
Cheesecote Mountain CAMAC
24 Halley Drive; Pomona, NY 10970
845 364 0211, www.cmcamac.com
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* To post a message: mailto:[EMAIL PROTECTED]
*
* To le
At 10:47 AM 11/30/01 +0100, [EMAIL PROTECTED] wrote:
>I have a problem with vias on a 6 layer board with a stack up like:
[ T p 1 c 2 p 3 c 4 p B ]
>Among others a via type, from layer 1 to layer 4, witch is depending on
>the layer stack, were used. But some of the vias were only connected on
At 09:03 AM 11/30/01 -0500, Jenkins, Charlie wrote:
>Why would I want to keep extra copper where it's not wanted? Electrically I
>might want the copper to separate sensitive areas of a board where a gnd net
>was missing. For my purposes I like to keep as much copper on board as
>possible. One bec
Every time I do something in 99SE PCB editor I get a little window that says
"Access violation at address 0E347E2A in module 'ADVPCB.DLL' Read ...
Exception Information:
Exception Occurred in
PCB: (What ever the last command was)
Note: After any system crash it is good practice to save your w
Tim,
my first guess is that something has corrupted your "ADVPCB.DLL"
file. Others would probably know better if I am wrong. First thing that I
would do is to save and protect any files that you have customized (ie. INI
files, libraries, etc.).
If this error is only occuring in on
I agree with all the previous posts, it is best to show the power pins. I
mostly use the Protel supplied library symbols only for caps, resistors,
etc. For most ICs, I make my own symbols. For discrete logic, I create a
separate part for the component that is a power block (a square with the
po
Brad, I'll try that. FYI, it doesn't even occur when I'm working with
another pcb in the SAME .ddb file. Very frustrating. It's happened in the
past but just seems to go away or only happens with a few commands, now it's
everything.
Tim
-Original Message-
From: Brad Velander [mailto:[EMA
This might be a clue, I tried repairing the ddb file and it says it can't
because it's being used by another user. I have NO ddb file open at all
Tim
-Original Message-
From: Brad Velander [mailto:[EMAIL PROTECTED]]
Sent: Friday, November 30, 2001 3:09 PM
To: 'Protel EDA Forum'
Subje
Never mind with the repair, some one else had the ddb file open even though
it didn't on my active design stations in the design explorer.
Tim
-Original Message-
From: Brad Velander [mailto:[EMAIL PROTECTED]]
Sent: Friday, November 30, 2001 3:09 PM
To: 'Protel EDA Forum'
Subject: Re: [PE
- Original Message -
From: "Jenkins, Charlie" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Friday, November 30, 2001 9:03 AM
Subject: Re: [PEDA] SV: Phatom polygons another tip
| Why would I want to keep extra copper where it's not wanted? Electrically I
| migh
>FYI, it doesn't even occur when I'm working with
>another pcb in the SAME .ddb file.
Perhaps not a corrupted ddb, but corrupted pcb file? Try exporting the
offensive PCB, creating a new, empty ddb, then importing the pcb.
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* To post a
Your right Brian. Things change for a production house that must comply
with regulations and can afford to reclaim copper and other waste products.
My very low volume prototypes don't use enough chemicals to qualify for
reclamation equipment. In fact it costs me to properly dispose of used
echan
At 09:03 AM 11/30/01 -0500, Jenkins, Charlie wrote:
>Why would I want to keep extra copper where it's not wanted? Electrically I
>might want the copper to separate sensitive areas of a board where a gnd net
>was missing.
From my understanding, this will increase crosstalk by increasing the
cap
Hello all,
I have a quick question. Has anyone written a Client Basic program to
print multiple schematic sheets? I have not seen a feature in Protel for
printing multiple files unless I overlooked it.
Thanks for the help
Afshin
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WOW, guess I just had to ask the question to receive the answer. I opened
up the print setup menu for the heck of it and saw a "Batch Type" drop down
menu. I selected "All Documents" and guess what it printed... :) Its
amazing how some answers will come so quickly at times and take forever at
At 11:07 AM 11/30/01 -0800, Cliff Gerhard wrote:
>When I get a clean DRC, I can be confident that nothing was overlooked. I
>have worked the other way, ending up with DRC errors and checking them off
>to make sure they are all were there for a reason. Inevitably, one will
>slip thru and bite you
Simple, If enough people sign up on the Tasking Compiler then Prottle feel
justified in charging us all for ATS. Kind of a 'baubles for the natives'
deal.
Too bad if you are a specialist PCB designer or just an Engineering firm who
moved on past the 8051in the late 80's to one of the far better
> At the schematic end, I always check for all unconnected pins and then pop
> a No-ERC directive on the ones that are truly intended to be unconnected.
> (The Error matrix default does not do this)
Yeah, I do this too. The no-ERC directive on unconnected pins is more to
remind me that I hav
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