Re: [PEDA] Protel default Vcc hidden power pins
> Of course. Every company must have standards. But any engineer who is > confused by hidden pins is either new or has not been paying attention. Newbies and Out-To-Lunch'ies are very common in our industry. We were all newbies once. Hopefully we were never OTL's. Do you get a kick out of watching newbies make "obvious" mistakes? I don't. The less time they have to spend learning arbitrary rules of the trade, the more time they have to learn real engineering principles. And the less company money and time they waste making mistakes. As for OTL's, well, nothing can help them... Best regards, Ivan Baggett Bagotronix Inc. website: http://www.bagotronix.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
>> I would suggest to drop >>this feature completely. It is a relic from the times when a chip had a >>power supply of 5V, and that was it. Abd ul-Rahman wrote: >The feature remains almost as useful as it ever was. Further, it should be >considered that there is a huge base of legacy designs which would be >wrecked if Protel no longer supported hidden pins. In addition, the ability >to load OrCAD schematics would be trashed. > >*But* it would not be difficult to provide tools that would make the use of >hidden pins less hazardous, or the elimination of hidden pins in a design >easier. On second thoughts, I agree. We tend to look at things under a point of view which is mainly influenced by personal experience, and so do I. The fact of not being able to use the standard library parts (mainly TTL) without having to rework the power pins (unhide them and replace them to some place where they can be wired manually a n d still result in a readable schematic) is not really important for my kind of designs. As most of my designs are processor boards with several different telecom parts (framers, etc.) the percentage of parts I can take from a pre-defined schematic library provided by Protel is less than 5%. This is not because I don't like the way parts are defined in the Protel libraries - the parts I need to place simply are not there. Parts I need to define myself never have hidden power pins, and, I agree, it is usefull to define a special part within a component definition which carries only power pins, and another one, which shows possible no-connects. Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
At 03:06 PM 3/15/01 +1100, Ian Wilson wrote: [I had written:] >> course our experience differs. However, I think that if we could >> collect statistics on the designs actually being made with Protel all >> over the world, the majority would be single supply (or dual-supply >> analog, which amounts to much the same thing, only it is V+, V- and >> GND). Yes, I also do plenty of designs which are multiple-supply, but >> multiple "VCC" designs are more rare. > >In the last 30 designs I have been part of, over the last 5 years, none >have been simple unswitched single supply designs. Almost all of these >were multiple VCC designs - that is logic running at multiple voltages or >switched. I am not particularly busy, but in five years, I would see many hundreds of designs. Mr. Wilson's experience is skewed by the kind of work he does. Mine may also be skewed a bit, but I do general printed circuit design for all kinds of companies, including quite a bit of 2-sided, very simple stuff. I'd say that perhaps 30% of my load is multiple-supply. [I also wrote:] >>Tango Schematic allowed sheetwise renaming of nets; a particular >>structure was exempt from the net renaming warning (A power port plus a >>short piece of track with a net label was always considered to be a >>deliberate renaming). Thus one could assign VCC on one page to, say, +5V, >>and on another to +3.3V. This was more flexible than what is created by >>inflexible, global-always-when-hidden power pins. > >What a nightmare! I would be *hugely* against Protel worsening the >situation with this concept. Goes completely against the grain of what I >teach all the new engineers I see - the schematic *must* be as complete a >document as possible. Some of us, however, think that a document *is* complete if it includes all the correct data. If I were an engineer trying to slap out a digital design quickly, I'd be very tempted to use hidden pins with all the standard logic. In spite of Mr. Wilson's vehemence, the hidden pin issue is not going to go away. As I mentioned, we must not only be compatible with legacy designs, but also OrCAD and other CAD imports must be able to accomodate hidden pins. The only objection to hidden pins that Mr. Wilson makes, really, is that the pins are hidden. But if we all know that a 14 pin 7400 series part has power on pins 7 and 14, it may be good documentation but is not essential to show those pins. If a page has a different supply, net renaming as I mentioned is explicit and quite easy to understand. > It must document the design to the maximum possible extent. Sure. But the word "possible" must include issues like the time available. It might be argued that "there is no time to do it right but there is always time to go back and fix it," as if it were somehow intrinsically *wrong* to use clearly understandable hidden pins, and, further, that it is also always wrong to cut corners to get the job to fab today instead of tomorrow. I'd say that it is *usually* wrong to cut corners, but not always. There may indeed be time later that one does not have now. Hidden pins can really bite you if you don't know how they work, and somehow manage to overlook the usually obvious problems of incorrect power supply assignment with a blind trust in DRC. Most of the danger of working with hidden pins would disappear if we had the reporting tools suggested. So why try to force everyone to work the same way? Rather, I would suggest developing clear methods of using hidden pins that avoid the dangers, plus reports that warn the user when there are potential problems. I think we would all agree that testing a nets for some kind of power source, such as a regulator pin defined as a power driver or a connector pin, would be useful even if we had no hidden pins. It would be much more useful in dealing with hidden pins. The power pins are there in a hidden pin schematic. They are merely on the next page. I.e., you can get to that page by globally showing hidden pins. Some way of doing that and then restoring the hidden state without any fuss would make this a more practical reality. I.e., Mr Wilson wants full, explicit documentation; he has no problem with power pins being on a different sheet; he should therefore be satisfied with a way of uncovering the power assignments of a part quickly and easily, as if one were turning a page. > If I can't see a pin on a schematic then as far as I am concerned that > pin does not exist and I do not want to see the pin on the PCB. But, of course, one can see hidden power pins any time one wishes. Mr. Wilson is correct, though, if he is only thinking of printed schematics. > It is a simple rule and has saved the day on many designs - especially > where there are a number of people/companies involved. Individual > designers can do what they like - until they walk through our door. > >Ian Wilson Of course. Every company must have standards.
Re: [PEDA] Protel default Vcc hidden power pins
At 03:28 PM 3/15/01 +1100, you wrote: >On 06:02 PM 14/03/2001 -0800, Abd ul-Rahman Lomax said: > >>At 10:04 AM 3/15/01 +1100, Ian Wilson wrote: >> >>>Personally, I would mark *all* parts of my multi-part components as must >>>place. This ensures spare gates etc are visible and any floating inputs >>>are detected. First need: make spare gates visible Second need: detect all floating inputs >>Note that my suggested tool, "Place unused parts of multi-part >>components," would satisfy both needs. The tool might put such parts on >>the cursor, in succession, until all unused parts had been placed. > >I am missing something - I think. I think so too :-) >Satisfy both of which needs? See above. >Are you saying that a process that a user may or may not run (Place unused >parts of multi-part components) would make unnecessary the capacity for >ERC to actually check if the parts were placed (my original suggestion). No. ERC would still generate a warning, I would suggest, that unplaced part sections exist. The tool I suggested would make it easy to place them all with little thought, and if one forgot, the DRC would remind. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
At 04:21 PM 3/13/01 -0700, Gordon Price wrote: >Ladies & Gents, > How do you globally fix hidden power pins(from Protel library parts) >that go to a net called "Vcc", to go to a fully defined and existing layer >that has a net name of "+3.3V" Two ways: (1) Edit the library part so that the pin name has +3.3V instead of VCC. (2) Unhide the pins in the sheet editor and explicitly connect the pins to the power net you want to use. The second method is probably better. Some of us firmly believe that hidden pins should never be used. I'm not quite so radical, but they do have a point, or, more accurately, several points. > I have a power plane named "+3.3V" and can get my own parts to >connect to the plane but can't get Vcc nets(from Protel library parts) to >connect to the +3.3V net. Of course not. Assuming that you have a separate VCC net on the board, say +5V, then you must keep the nets separate. When you have multiple power voltages, the use of hidden pins becomes hazardous. They are only really useful when only one voltage is used to connect to hidden pins. > If I place a net reference of Vcc on the +3.3V net >the auto router runs traces instead of connecting to the defined power >plane. What net name was assigned to the power plane? I'd guess VCC. You successfully renamed VCC to +3.3V, but perhaps you did not change the power plane net assignment to +3.3V. (That is done in the stack manager in Protel 99.) > It would be nice to have more than one net name be able to go to a >given power plane and net. Where am I missing the boat??? The boat is a boat called "Net Names are Unique." As I recall (and from what was said above) you can rename nets on a sheet. It's a little fussy. I don't remember the rule: if I place a power object and connect it to a piece of wire with a net label on it, I think one of them has precedence over the other. But in the end, in what goes to the PCB, you have only one net with one name. There is no provision for anything else, and anything else would be *very* confusing. > I can't for the life of me understand with the prevalence of >different supply voltages of chips, why Protel uses hidden power pins and >fixed net names. I am using +1.8V, +3.3V and +5V on one board. It's a library control problem. Do you want the users to be able to edit pin attributes in the sheet editor? Some CAD programs allow this, some do not. I think most do not, and Protel is with the majority. I'd rather that it be allowed, but any edit to a pin in the sheet editor should set a flag that can then be used to generate an edited pin report. Another report should give the names of all hidden pins in a design with information about the part to which the pin belongs. The advantages of this: (1) We could unhide pins, edit the name, and rehide them if we really want to have hidden power pins. (2) We could change the electrical attribute of "I/O" pins in programmable parts to match the configuration as used, and thus get the advantages of improved electrical rules checking for those nets. I do not suggest, however, that we be able to edit pin *numbers*. This is far too dangerous. If we really need to edit pin numbers, then we should make a new symbol. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
On 06:30 PM 14/03/2001 -0800, Abd ul-Rahman Lomax said: >At 06:07 PM 3/14/01 -0600, David W. Gulley wrote: >>Abd ul-Rahman Lomax wrote: >> >> > The vast majority of integrated circuits in designs which cross >> > my desk are single-supply, and the majority of designs have only >> > two power nets: ground and one other. >> >>And as has been demonstrated so many times, one person's experience with >>designs is vastly different from an other's! >> >> A design I am currently working on has five digital power supplies >>(5.0, 3.3, 2.5 1.8 and 1.2) as well as two analog supplies. > >Of course our experience differs. However, I think that if we could >collect statistics on the designs actually being made with Protel all over >the world, the majority would be single supply (or dual-supply analog, >which amounts to much the same thing, only it is V+, V- and GND). Yes, I >also do plenty of designs which are multiple-supply, but multiple "VCC" >designs are more rare. In the last 30 designs I have been part of, over the last 5 years, none have been simple unswitched single supply designs. Almost all of these were multiple VCC designs - that is logic running at multiple voltages or switched. >"More rare" can still be "common", so Mr. Gulley's experience does not >surprise me at all. And certainly Protel must be able to handle with ease >multiple-supply designs. The present hidden-pin system clearly is not >sufficient. > >Tango Schematic allowed sheetwise renaming of nets; a particular structure >was exempt from the net renaming warning (A power port plus a short piece >of track with a net label was always considered to be a deliberate >renaming). Thus one could assign VCC on one page to, say, +5V, and on >another to +3.3V. This was more flexible than what is created by >inflexible, global-always-when-hidden power pins. What a nightmare! I would be *hugely* against Protel worsening the situation with this concept. Goes completely against the grain of what I teach all the new engineers I see - the schematic *must* be as complete a document as possible. It must document the design to the maximum possible extent. If I can't see a pin on a schematic then as far as I am concerned that pin does not exist and I do not want to see the pin on the PCB. It is a simple rule and has saved the day on many designs - especially where there are a number of people/companies involved. Individual designers can do what they like - until they walk through our door. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
On 06:02 PM 14/03/2001 -0800, Abd ul-Rahman Lomax said: >At 10:04 AM 3/15/01 +1100, Ian Wilson wrote: > >>Personally, I would mark *all* parts of my multi-part components as must >>place. This ensures spare gates etc are visible and any floating inputs >>are detected. > >Note that my suggested tool, "Place unused parts of multi-part >components," would satisfy both needs. The tool might put such parts on >the cursor, in succession, until all unused parts had been placed. I am missing something - I think. Satisfy both of which needs? Are you saying that a process that a user may or may not run (Place unused parts of multi-part components) would make unnecessary the capacity for ERC to actually check if the parts were placed (my original suggestion). If the library symbol was able to flag an error if one or more special parts (sections) were not in the design then this allows ERC to catch the error. ERC is currently not very good at catching errors of omission (floating inputs and power pins only basically). Your suggested process makes it easier to fix the error once it occurs and to prevent the error in the first place but it can't guarantee that the error gets noticed. My comment about flagging all parts of a symbol as "must place" is purely so I get an error if I leave a section of a multi-part off the schematic. Since my designs show all parts of all sch symbols I would want to know if any section was missing - even if it is completely benign. I repeat: Your proposed process improves my workflow but it does nothing to check the quality of my work. My proposed change to the library attributes and the ERC allow the quality of my work to be checked but do nothing to improve my workflow. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
I would like to make a brief comment about hiding power pins. I have been burned. My advice to anyone who thinks this is a good idea is don't do it. Show everything where nothing is assumed to be connected. This allows proper identification of all bypass caps shown right where they are connected to the device. -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Tuesday, March 13, 2001 6:21 PM To: Protel EDA Forum Subject: Re: [PEDA] Protel default Vcc hidden power pins At 04:21 PM 3/13/01 -0700, Gordon Price wrote: >Ladies & Gents, > How do you globally fix hidden power pins(from Protel library parts) >that go to a net called "Vcc", to go to a fully defined and existing layer >that has a net name of "+3.3V" Two ways: (1) Edit the library part so that the pin name has +3.3V instead of VCC. (2) Unhide the pins in the sheet editor and explicitly connect the pins to the power net you want to use. The second method is probably better. Some of us firmly believe that hidden pins should never be used. I'm not quite so radical, but they do have a point, or, more accurately, several points. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
At 06:36 PM 3/13/01 -0600, John Lemburg wrote: >I would like to make a brief comment about hiding power pins. I have been >burned. My advice to anyone who thinks this is a good idea is don't do it. >Show everything where nothing is assumed to be connected. This allows >proper identification of all bypass caps shown right where they are >connected to the device. I routinely use hidden power pins without a problem. But I also know that it is easy to wander blindly into the world of hidden pins and get burned fairly badly. *If* there is a single hidden power supply on the board, *and* one has verified that the hidden pins have the appropriate attributes, there can be good reasons for using them. Ideally, when we design parts that might be candidates for the use of hidden pins, the pins are placed such that they can be unhidden and used with ease and grace. Not all the Protel parts have been made this way. If one uses unhidden pins for power, with multigate ICs, as a common example, the question arises of where to put the power pins, i.e., on which section or on all sections. Suffice it to say that this can be a nuisance in itself. How many times I have ended up with a mess because section numbers were changed for various reasons with a part with power on a single section, I don't care to count. Something that I would try if I had time today would be to unhide the pins on one section of an IC with hidden power pins and connect that to a differently named power supply. I would expect this to generate an error or at least a net renaming warning if other sections with hidden pins were present in the design. If so, and if one wants to be explicit, one could simply unhide one section, any convenient section, assuming that all the sections have hidden pins, and wire it explicitly. This would be very safe. If one wired it explicitly to a different net than the hidden net, it would generate an error or warning. Thus one would have the best of both worlds. As to bypass capacitors, it is just as explicit to place a bypass cap with power objects next to the part in question, and it is easier to implement; one can do it for a whole page at once by placing one cap and its power objects and copying it as many times as necessary. Since it is not actually going to a pin, the location is not critical. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
Hi Gordon. You just Name those pins you want to connect to that power by name that pin to "+3.3V" and select the Hidden option. Good luck. > -Original Message- > From: Gordon Price [mailto:[EMAIL PROTECTED]] > Sent: Tuesday, March 13, 2001 3:22 PM > To: [EMAIL PROTECTED] > Subject: [PEDA] Protel default Vcc hidden power pins > > > Ladies & Gents, > How do you globally fix hidden power pins(from Protel library parts) > that go to a net called "Vcc", to go to a fully defined and existing layer > that has a net name of "+3.3V" > I have a power plane named "+3.3V" and can get my own parts to > connect to the plane but can't get Vcc nets(from Protel library parts) to > connect to the +3.3V net. If I place a net reference of Vcc on > the +3.3V net > the auto router runs traces instead of connecting to the defined power > plane. It would be nice to have more than one net name be able to go to a > given power plane and net. Where am I missing the boat??? > I can't for the life of me understand with the prevalence of > different supply voltages of chips, why Protel uses hidden power pins and > fixed net names. I am using +1.8V, +3.3V and +5V on one board. > > Thanks, > R. Gordon Price > Director of Research Engineering > Loronix Information Systems Inc. > Del Mar CA > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
At 10:04 AM 3/15/01 +1100, Ian Wilson wrote: >Personally, I would mark *all* parts of my multi-part components as must >place. This ensures spare gates etc are visible and any floating inputs >are detected. Note that my suggested tool, "Place unused parts of multi-part components," would satisfy both needs. The tool might put such parts on the cursor, in succession, until all unused parts had been placed. My preference, by the way, is also to place all parts, both so that I can ensure that unused inputs are tied where this is necessary, and also so that it is easy, next rev around, to identify unused gates or op amps should they be needed. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
On Tue, 13 Mar 2001 18:36:52 -0600, John Lemburg wrote: >I would like to make a brief comment about hiding power pins. I have been >burned. My advice to anyone who thinks this is a good idea is don't do it. >Show everything where nothing is assumed to be connected. This allows >proper identification of all bypass caps shown right where they are >connected to the device. And I will bring up the point (again) that what you should or should not show on a schematic depends on wether you consider the schematic to be a graphical aid for netlist and partlist entry or an actual schematical representation of a circuit. Also trying to make assumptions about power supply bypass capacitor placement from placement on a schematic is very dubious. If two chips end up next to each other do you really want two decoupling caps placed side by side? If you only place one which chip gets it on the schematic? Cheers, Terry. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
At 06:07 PM 3/14/01 -0600, David W. Gulley wrote: >Abd ul-Rahman Lomax wrote: > > > The vast majority of integrated circuits in designs which cross > > my desk are single-supply, and the majority of designs have only > > two power nets: ground and one other. > >And as has been demonstrated so many times, one person's experience with >designs is vastly different from an other's! > > A design I am currently working on has five digital power supplies >(5.0, 3.3, 2.5 1.8 and 1.2) as well as two analog supplies. Of course our experience differs. However, I think that if we could collect statistics on the designs actually being made with Protel all over the world, the majority would be single supply (or dual-supply analog, which amounts to much the same thing, only it is V+, V- and GND). Yes, I also do plenty of designs which are multiple-supply, but multiple "VCC" designs are more rare. "More rare" can still be "common", so Mr. Gulley's experience does not surprise me at all. And certainly Protel must be able to handle with ease multiple-supply designs. The present hidden-pin system clearly is not sufficient. Tango Schematic allowed sheetwise renaming of nets; a particular structure was exempt from the net renaming warning (A power port plus a short piece of track with a net label was always considered to be a deliberate renaming). Thus one could assign VCC on one page to, say, +5V, and on another to +3.3V. This was more flexible than what is created by inflexible, global-always-when-hidden power pins. >As to the rest of Abd's message, I agree wholeheartedly: >[...] > Except for the following: > > A warning that there are hidden power pins on a design would > > not be a bad idea. > With this sentence, I totally disagree with Abd, I think, > "A warning that there are hidden power pins on a design >*should* be REQUIRED!" Sorry, I must have been asleep. Thanks for correcting me, David. :-) [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
Abd ul-Rahman Lomax wrote: > > At 10:23 AM 3/14/01 +0100, [EMAIL PROTECTED] wrote: > >As chip designers tend to show > >ambition in specifying three and more power supplies for one chip, > >there is not much use in the hidden pin feature any more. > > The vast majority of integrated circuits in designs which cross > my desk are single-supply, and the majority of designs have only > two power nets: ground and one other. And as has been demonstrated so many times, one person's experience with designs is vastly different from an other's! A design I am currently working on has five digital power supplies (5.0, 3.3, 2.5 1.8 and 1.2) as well as two analog supplies. The design uses several SN74LVC14A Schmitt-trigger inverters for cleaning up some slow edges. Interestingly one SN74LVC14A provides 6 inverters, which is how many are required on the board; however, I need 2 at 3.3V, 3 at 2.5V and 1 at 1.8V. Using the hidden pins would be a killer, as would just allowing individual gates. So the three 14-pin packages are used in their entirety to insure that the next guy to "just add an inverter" has to decide which of the 3 packages he intends utilize. I do have designs where I use hidden pins, but (for me) they are getting rarer. As to the rest of Abd's message, I agree wholeheartedly: > Further, it should be considered that there is a huge base of > legacy designs which would be wrecked if Protel no longer > supported hidden pins. > *But* it would not be difficult to provide tools that would make > the use of hidden pins less hazardous, or the elimination of > hidden pins in a design easier. Yes! Yes! Except for the following: > A warning that there are hidden power pins on a design would > not be a bad idea. With this sentence, I totally disagree with Abd, I think, "A warning that there are hidden power pins on a design *should* be REQUIRED!" David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
On 12:32 PM 14/03/2001 -0800, Abd ul-Rahman Lomax said: >At 08:29 AM 3/14/01 +, Coleman, Tim wrote: > >>With regard to power pins on multiple part components(or even large single >>part components like a uP or memory). We create a 'power part' that has just >>the power pins and any NC pins. This part of the component is then placed as >>part of the power distribution and if a de-coupling capacitor is required it >>can be placed directly on the pins of the power part of the component. > >This is an excellent way to go, but it does require making one's own >parts. I would also note that if one neglects to place a power section for >a part, no rule, as far as I know, will detect that it is missing. > >If one follows Mr. Coleman's practice, it would be useful to be able to >generate an unconnected pin report. This would detect all pins on the >schematic *including pins on unplaced sections (which exist in the >cache)*; it would report all pins which are unconnected -- probably by >comparison with a netlist if it is a server we write -- and would >specially flag unconnected power pins. I have been wanting a more elaborate rules system for Sch for some time and have raised the issue before to see what rules the group would like. That seems to the logical extension of these two interlinked hidden pin threads. Suggestion: An attribute (per section/part of a multi-part component) in a sch library that says this "part must be placed". The ERC could then check that for each symbol the required "must place" section(s) is/are included. (David Cary - did you get that for your features database?) Personally, I would mark *all* parts of my multi-part components as must place. This ensures spare gates etc are visible and any floating inputs are detected. Like others I am a firm believer that the sch must be complete and show every pin. Design review, debugging, test and future improvements are made so much easier not to mention the improved ability of the ERC system to detect problems. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
At 08:29 AM 3/14/01 +, Coleman, Tim wrote: >With regard to power pins on multiple part components(or even large single >part components like a uP or memory). We create a 'power part' that has just >the power pins and any NC pins. This part of the component is then placed as >part of the power distribution and if a de-coupling capacitor is required it >can be placed directly on the pins of the power part of the component. This is an excellent way to go, but it does require making one's own parts. I would also note that if one neglects to place a power section for a part, no rule, as far as I know, will detect that it is missing. If one follows Mr. Coleman's practice, it would be useful to be able to generate an unconnected pin report. This would detect all pins on the schematic *including pins on unplaced sections (which exist in the cache)*; it would report all pins which are unconnected -- probably by comparison with a netlist if it is a server we write -- and would specially flag unconnected power pins. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
At 10:23 AM 3/14/01 +0100, [EMAIL PROTECTED] wrote: >As chip designers tend to show >ambition in specifying three and more power supplies for one chip, there is >not much use in the hidden pin feature any more. The vast majority of integrated circuits in designs which cross my desk are single-supply, and the majority of designs have only two power nets: ground and one other. > I would suggest to drop >this feature completely. It is a relic from the times when a chip had a >power supply of 5V, and that was it. The feature remains almost as useful as it ever was. Further, it should be considered that there is a huge base of legacy designs which would be wrecked if Protel no longer supported hidden pins. In addition, the ability to load OrCAD schematics would be trashed. *But* it would not be difficult to provide tools that would make the use of hidden pins less hazardous, or the elimination of hidden pins in a design easier. For an example of the first, reports that detect the common errors involved with hidden pins could be generated. A power source electrical attribute should be created. A "Power source missing from power net" warning should be included in ERC. Sometimes we want to isolate a power pin from the power net, with an inductor, for example, but extra warnings, once we know how to suppress them with No-ERC markers, do little or no harm. A warning that there are hidden power pins on a design would not be a bad idea. For the second, consider a library of standard logic parts, the kind which presently have hidden power pins as the default. For some of them, it seems I recall, if you unhide the power pins you get a bit of a mess; they are not placed well; sometimes they are on top of each other. A new library could be created with better power pin placement. Another library would have versions of the parts with a power section; updating all these symbols would not change a schematic at all, visually, nor with respect to connectivity, except for power connectivity. Then a command would be provided "Place Unused Parts" which would scan the project for unused sections and pop them onto a new sheet. Thus one could convert a hidden pin schematic to an explicit schematic fairly painlessly. (Actually, one could make a server or utility that would simply create these unused sections, modifying the cache accordingly and removing the hidden pins from the placed sections.) [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
Greetings all, > As to bypass capacitors, it is just as explicit to place a bypass cap with > power objects next to the part in question, and it is easier to implement; > one can do it for a whole page at once by placing one cap and its power > objects and copying it as many times as necessary. Since it is not actually > going to a pin, the location is not critical. I would very much appreciate a discussion on how to place bypass caps (on circuit diagram) so as to end up with short leads direct to the relevant pins (on the final PCB). I have tried using "Place>Directive>PCB Layout" Markers without much success, am now exploring using Design Rules to force the AutoRouter to be sensible about bypass cap connections. I'm guessing that the "From-To Editor" has a big part in all this, but I am finding it incredibly frustrating to use.. I can easily pre-route power/bypass cap traces and then lock them down, but that prevents the auto router moving them to different layers, etc.. Any suggestions as how best to tackle the whole question of optimum EMC layout would be very welcome. Thanks . Zim * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
Un-hide hidden pins from component properties, and connect them wherever you want. --- Jari Kaija Electronics Designer PKC Group Oyj Mobile: +358 (0)40 5200265 Phone: +358 (0)201 752252 TeleFax: +358 (0)201 752401 Kiveläntie FIN-90440 KEMPELE FINLAND [EMAIL PROTECTED] http://www.pkcgroup.com http://kotisivu.mtv3.fi/oma/jari.kaija --- Gordon Price cc: Subject: [PEDA] Protel default Vcc hidden power pins 14.03.2001 01:21 Please respond to "Protel EDA Forum" Ladies & Gents, How do you globally fix hidden power pins(from Protel library parts) that go to a net called "Vcc", to go to a fully defined and existing layer that has a net name of "+3.3V" I have a power plane named "+3.3V" and can get my own parts to connect to the plane but can't get Vcc nets(from Protel library parts) to connect to the +3.3V net. If I place a net reference of Vcc on the +3.3V net the auto router runs traces instead of connecting to the defined power plane. It would be nice to have more than one net name be able to go to a given power plane and net. Where am I missing the boat??? I can't for the life of me understand with the prevalence of different supply voltages of chips, why Protel uses hidden power pins and fixed net names. I am using +1.8V, +3.3V and +5V on one board. Thanks, R. Gordon Price Director of Research Engineering Loronix Information Systems Inc. Del Mar CA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
> >I would like to make a brief comment about hiding power pins. I have been > >burned. My advice to anyone who thinks this is a good idea is don't do it. > >Show everything where nothing is assumed to be connected. I second this motion! Which snake are you more likely to get bitten by: the one you can see, or the one that is hidden? And so it goes with power pins. When I create parts symbols, I always make the power pins visible. That way I can connect them to whichever power bus I need to, and know that they are indeed connected. The same goes for NC pins. Show them, and use a no-erc symbol on them to explicitly declare that "No, I didn't forget to connect it. It's supposed to be unconnected". [Off topic] I also hate assembly language code written with macros. Same concept (hidden code). It makes it very difficult to figure out what's really happening. Best regards, Ivan Baggett Bagotronix Inc. website: http://www.bagotronix.com - Original Message - From: Abd ul-Rahman Lomax <[EMAIL PROTECTED]> To: Protel EDA Forum <[EMAIL PROTECTED]> Sent: Tuesday, March 13, 2001 8:39 PM Subject: Re: [PEDA] Protel default Vcc hidden power pins > At 06:36 PM 3/13/01 -0600, John Lemburg wrote: > >I would like to make a brief comment about hiding power pins. I have been > >burned. My advice to anyone who thinks this is a good idea is don't do it. > >Show everything where nothing is assumed to be connected. This allows > >proper identification of all bypass caps shown right where they are > >connected to the device. > > I routinely use hidden power pins without a problem. But I also know that > it is easy to wander blindly into the world of hidden pins and get burned > fairly badly. *If* there is a single hidden power supply on the board, > *and* one has verified that the hidden pins have the appropriate > attributes, there can be good reasons for using them. Ideally, when we > design parts that might be candidates for the use of hidden pins, the pins > are placed such that they can be unhidden and used with ease and grace. Not > all the Protel parts have been made this way. > > If one uses unhidden pins for power, with multigate ICs, as a common > example, the question arises of where to put the power pins, i.e., on which > section or on all sections. Suffice it to say that this can be a nuisance > in itself. How many times I have ended up with a mess because section > numbers were changed for various reasons with a part with power on a single > section, I don't care to count. > > Something that I would try if I had time today would be to unhide the pins > on one section of an IC with hidden power pins and connect that to a > differently named power supply. I would expect this to generate an error or > at least a net renaming warning if other sections with hidden pins were > present in the design. > > If so, and if one wants to be explicit, one could simply unhide one > section, any convenient section, assuming that all the sections have hidden > pins, and wire it explicitly. This would be very safe. If one wired it > explicitly to a different net than the hidden net, it would generate an > error or warning. > > Thus one would have the best of both worlds. > > As to bypass capacitors, it is just as explicit to place a bypass cap with > power objects next to the part in question, and it is easier to implement; > one can do it for a whole page at once by placing one cap and its power > objects and copying it as many times as necessary. Since it is not actually > going to a pin, the location is not critical. > > [EMAIL PROTECTED] > Abdulrahman Lomax > P.O. Box 690 > El Verano, CA 95433 > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
John, I think it is a well established rule amongst most of the listserver members that hidden pins are a pending disaster for any non-digital, non-single supply design. Most everyone who has ever done more then one or two designs has been burnt by this issue, sometimes more then once. Sincerely, Brad Velander Lead PCB Design Norsat International Inc. #100 - 4401 Still Creek Dr., Burnaby, B.C., Canada. V5C6G9. voice: (604) 292-9089 (direct line) fax:(604) 292-9010 email: [EMAIL PROTECTED] www: www.norsat.com -Original Message- From: John Lemburg [mailto:[EMAIL PROTECTED]] Sent: Tuesday, March 13, 2001 4:37 PM To: Protel EDA Forum Subject: Re: [PEDA] Protel default Vcc hidden power pins I would like to make a brief comment about hiding power pins. I have been burned. My advice to anyone who thinks this is a good idea is don't do it. Show everything where nothing is assumed to be connected. This allows proper identification of all bypass caps shown right where they are connected to the device. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
Hi, I would say, from experiance, that hidden pins are not good, my advice is don't go that route, show everything even NC pins. With regard to power pins on multiple part components(or even large single part components like a uP or memory). We create a 'power part' that has just the power pins and any NC pins. This part of the component is then placed as part of the power distribution and if a de-coupling capacitor is required it can be placed directly on the pins of the power part of the component. This enables us to seperate the power distrubution from the rest of the circuit, it ensures that we have no hidden pins and simplies the schematic. It works quite well. -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Wednesday, March 14, 2001 1:39 AM To: Protel EDA Forum Subject: Re: [PEDA] Protel default Vcc hidden power pins At 06:36 PM 3/13/01 -0600, John Lemburg wrote: >I would like to make a brief comment about hiding power pins. I have been >burned. My advice to anyone who thinks this is a good idea is don't do it. >Show everything where nothing is assumed to be connected. This allows >proper identification of all bypass caps shown right where they are >connected to the device. I routinely use hidden power pins without a problem. But I also know that it is easy to wander blindly into the world of hidden pins and get burned fairly badly. *If* there is a single hidden power supply on the board, *and* one has verified that the hidden pins have the appropriate attributes, there can be good reasons for using them. Ideally, when we design parts that might be candidates for the use of hidden pins, the pins are placed such that they can be unhidden and used with ease and grace. Not all the Protel parts have been made this way. If one uses unhidden pins for power, with multigate ICs, as a common example, the question arises of where to put the power pins, i.e., on which section or on all sections. Suffice it to say that this can be a nuisance in itself. How many times I have ended up with a mess because section numbers were changed for various reasons with a part with power on a single section, I don't care to count. Something that I would try if I had time today would be to unhide the pins on one section of an IC with hidden power pins and connect that to a differently named power supply. I would expect this to generate an error or at least a net renaming warning if other sections with hidden pins were present in the design. If so, and if one wants to be explicit, one could simply unhide one section, any convenient section, assuming that all the sections have hidden pins, and wire it explicitly. This would be very safe. If one wired it explicitly to a different net than the hidden net, it would generate an error or warning. Thus one would have the best of both worlds. As to bypass capacitors, it is just as explicit to place a bypass cap with power objects next to the part in question, and it is easier to implement; one can do it for a whole page at once by placing one cap and its power objects and copying it as many times as necessary. Since it is not actually going to a pin, the location is not critical. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
Hi, I must admit that I still use hidden pins for 5V connections, which I call VCC like the naming convention in the Protel libraries suggests. I know I shouldn't, as it is getting more and more dangerous, if several different power nets are to be used in a design. As chip designers tend to show ambition in specifying three and more power supplies for one chip, there is not much use in the hidden pin feature any more. I would suggest to drop this feature completely. It is a relic from the times when a chip had a power supply of 5V, and that was it. Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
