On 07/16/2017 12:54 AM, Sivan Toledo via USRP-users wrote:
> OK, tried it and I clearly need to call the "make" functions, otherwise
> the code segfaults.
Yes, UHD won't allocate memory implicitly in the C-API.
-- M
>
> On Sat, Jul 15, 2017 at 7:02 PM, Sivan Toledo
Mareike,
the reason for the delays is that your software is polling the GPIO, and
that goes over network. You're adding in network latency, and SW
scheduling latency.
Also, with the DDC, once a packet leaves the computer, it needs to go
through various stages before it reaches the ADC (after the
Daniel,
all of our devices are listed (with rates) on our website:
https://www.ettus.com/product
The X-series has the highest achievable rates. What you can sustain
depends on many things, including the computer running UHD and the
implementation. An E-Series typically won't be able to sustain
How did you install GNU Radio and UHD, respectively?
-- M
On 07/18/2017 09:24 AM, Matheou, Konstantin J. (GRC-LCI0)[ZIN
TECHNOLOGIES INC] via USRP-users wrote:
> I finally got things connected to the B210, and now I am having
> software/firmware compatibility issues.
>
>
>
> I did do
Altuğ,
per channel, there's 2 half-bands and 1 CIC. The rule is: We try and
enable as many half-bands as possible, the rest is done by CIC. So, any
ratio of sample_rate to master_clock_rate that is divisible by 4 has 2
half-bands, any other even ratio has 1 half-band, and the remainder is
done in
On 07/18/2017 08:22 AM, Jie Song via USRP-users wrote:
> Hi,
>
> Are there any source codes for those examples in the UHD software
> library directory and I can refer to?
Jay,
https://github.com/EttusResearch/uhd/tree/maint/host/examples
-- M
___
It's pretty raw, but there's fosphor code in gr-ettus that displays
stuff via browser. See here:
https://github.com/EttusResearch/gr-ettus/tree/master/web
Don't ask me any questions about it :)
-- M
On 07/17/2017 08:48 AM, Steve Ringwald via USRP-users wrote:
> Hi,
>
>
>
> I’m currently
On 07/18/2017 02:41 PM, Estrada Lupianez, Jenniffer Marie via USRP-users
wrote:
> Can anyone point to any documentation or give some insight on how the
> E310 FPGA Verilog code design is laid out? I am not familiar with
> Verilog, and just extrapolating from what I understand from VHDL. What
> is
Dear UHD users,
when running uhd_images_downloader with the -i switch, the script will
still attempt to clear the target directory (this is the default
behaviour). To avoid this, you have the option of specifying `-k` (or
`--keep`) to not delete anything.
Future versions of UHD will have
So did using second_addr fix your problem?
-- M
On 07/20/2017 06:36 PM, Eugene Grayver via USRP-users wrote:
> This is not a question, but a note for others:
>
>
>
> I have two TwinRX boards in an X310. Connected using dual 10 GbE links
> to the PC. FPGA type XG is loaded. Both links get
Dan,
you can also use timed commands to write to GPIOs at the "same time" as
a certain sample. I use quotes, because there's some delay between the
sample touching the radio state machine and it hitting the antenna, as
well as between GPIOs being toggled in the FPGA and the pin actually
going
multi_usrp has many APIs, not all apply for all devices.
enumerate_registers() is from USRP2-era.
I'm curious -- have you already done the FPGA work, or is this where
you're starting?
In general, registers are exposed via the RFNoC XML file (e.g.,
radio_x300.xml).
-- M
On 09/12/2017 02:04 PM,
On Wed, Sep 27, 2017 at 01:42:22PM -0400, Jason Matusiak via USRP-users wrote:
> OK, dumb question, but I just can't come up with a good answer. I
> understand that the RFNoC FIFOs are a must if you only have one NoC block
> that you want to use and are using the GNURadio host [1]. So why do
On 08/14/2017 06:28 AM, via USRP-users wrote:
> Hi,
>
> I'm interested in constructing a beamforming system using X310s, and try
> to utilize the FPGA resources within the X310 USRP device.
>
> After some searching and reading of the introduction materials on RFNoC,
> I am still wondering
Dear friends and fans of software defined radio and free/open source
radio topics in general,
next year's FOSDEM (the free and open source developer's meeting in
Brussels, Europe) will, once again, feature a track on Software Defined
Radio and other radio-related topics.
Therefore, we invite
My apologies -- the SDR devroom is Sunday the 4th, not Saturday.
Regards,
Martin
On 10/06/2017 10:00 PM, Martin Braun wrote:
> Dear friends and fans of software defined radio and free/open source
> radio topics in general,
>
> next year's FOSDEM (the free and open source developer's meeting in
The AB and BA frontend configurations are not supported with RFNOC (or
UHD 3.10) on the X-Series. In a nutshell, it's because the original
drivers were registering phony frontends to simulate switching between
them, but they all go to the same connectors. The RFNoC architecture
doesn't let us
Daniel,
FFT controls happen through the 'shift', 'direction', and 'scaling'
properties. See, e.g., here:
https://github.com/EttusResearch/uhd/blob/ec9138eb6634b0af106762832c7518c887576a94/host/include/uhd/rfnoc/blocks/fft.xml#L71-L82
The control word is constructed in the block from those
The RC1 is based off of master branch, see also:
https://github.com/EttusResearch/uhd/releases/tag/v3.12.0.0-rc1
Cheers,
Martin
On 05/17/2018 02:31 PM, Martin Braun wrote:
> Yes,
>
> two release candidates back to back!
>
> While we're wrapping up the 3.11.1.0 release, we're already
On 06/06/2018 08:41 AM, Philip Balister wrote:
>> Tag, FPGA images and github-auto-produced tarballs can be found here:
>> https://github.com/EttusResearch/uhd/releases/tag/v3.12.0.0
>
> If you are using tarball checksums to validate the tarball, github will
> occasionally regenerate the tarball
On 06/06/2018 08:26 AM, Martin Braun wrote:
> - 3.12.0.0 removed some public API calls, it is thus an API-breaking
> release (note that these were some obscure API calls, most users
> won't see a difference. GNU Radio users certainly won't).
> If you want to keep everything as stable as
On 06/13/2018 12:49 PM, Farhad Mirkazemi via USRP-users wrote:
> I'm trying to manipulate my usrp2 clock using the example clock_ctrl.cpp
> but when I try to build it, I get cmake error related as following; the
> warning should be ok but I don't understand the error which says it does
> not know
I'm not sure this is the XML file. It looks like the traffic is going
from your block to the radio block controller because the outgoing SID
is not set properly.
However, the outgoing ctrl_iface SID is derived from the incoming
packet. Have you had other blocks work in the past?
Did it stop
On 06/13/2018 12:30 AM, ishai alouche via USRP-users wrote:
> Hi all,
>
> I open with rfnocnodtool new block with the name siggen like the block
> that exist in the basic rfnoc block in the gnu-radio. So i have two
> rfnoc block with the same name in different directory.
> I decide to delete the
I would expect it grow indefinitely, but it might slow down after 1.2
MB. If repeat is on, expect lots of data.
The 106 bytes vs. 64 bytes is more interesting. I don't see why, but
maybe somewhere the last 42 bytes are getting stuck. It might even be in
GNU Radio.
Try a file that's a multiple of
On 06/09/2018 12:59 PM, Zhongyuan Zhao via USRP-users wrote:
> Hi,
>
> I was configuring N310 for the first time. My UHD version is 3.12 with
> branch of python-api,
>
> When I try to update the SD image of firmware, according to
> the https://kb.ettus.com/N300/N310_Getting_Started_Guides
>
>
On 06/12/2018 10:28 AM, Ayaz Mahmud via USRP-users wrote:
> Hi,
>
>
>
> I am trying to transmit and receive a .png file through OFDM (*Block
> diagram attached*). The file size is only 1.5kB. While running I am
> getting the below warning & error in console. Can someone point out the
> reason
Two more comments:
- The clock is not exported by default. So MB 1 won't see a reference
clock, and then you get the error you saw.
- You can get frequency alignment between the boards this way, but the
time will definitely be un-aligned, like Michael said.
-- M
On 06/11/2018 03:38 PM, Michael
On 06/11/2018 12:42 PM, Luis Felipe Albarracin Sanchez via USRP-users wrote:
>
> Hello all,
>
> I am having an Issue when trying to test a model with a USRP B210, i
> have instaled GNURadio, via:
>
> *$ apt install gnuradio*
>
> then i tried to connect mi USRP to the model, but the followig
Matis,
you also need to keep in mind that via USB, we can only receive a
certain amount of samples at a time, and it's not a factor of 16384.
-- M
On 06/08/2018 04:18 PM, Marcus Müller via USRP-users wrote:
> Hi Matis,
>
> the time stamp of the first buffer after a disruption should indeed be
On 05/01/2018 05:13 AM, Ronakraj Gosalia via USRP-users wrote:
> Hi everyone,
>
> I am using a USRP E312 with GNU Radio 3.7.10.2. GNU Radio has an inbuilt
> FEC block that supports Turbo Product Codes (TPC). I'm trying to run a
> flowgraph (completely in simulation) on the E312 that includes a
On 06/07/2018 03:55 AM, Derek Kozel via USRP-users wrote:
> Hello Walter,
>
> The N310 uses MPMD as it's host side interface so the appropriate flag
> is -DENABLE_MPMD. I'll see about documenting that better. The E3xx build
> flag is entirely separate.
>
I assume you're using a BasicRX/TX combo and a recent UHD version (3.11
and above).
How exactly are you using receiving? Are you sending a single stream
command, or multiple stream commands? If its the latter, are you setting
time stamps?
-- M
On 06/05/2018 11:25 AM, Nicolai Kern via USRP-users
On 05/12/2018 05:17 AM, EJ Kreinar via USRP-users wrote:
> I also find this confusing...
>
> Even better: how about a scheme where x3xx finds both x300/x310, but
> x310 only gets x310, etc??
We use the 'product' key for that.
-- M
___
USRP-users
On 05/18/2018 05:55 PM, harfan ryanu via USRP-users wrote:
> Hi All,
> I have question related to two function in UHD. There is a function to
> choose subdev (set_tx/rx_subdev_spec) and set antenna
> (set_tx/rx_antenna). What is the difference between these two function?
> If i choose for example
It's the right file, however, this kind of modification is outside of
the scope of what we can help you with. Good luck!
-- M
On 06/13/2018 02:49 PM, Farhad Mirkazemi wrote:
> Hello martin,
>
> Thanks for your reply;meanwhile, I am modifying/setting the r divider to
> "2" in the clock_ctrl.cpp
On 01/26/2018 02:28 AM, Дмитрий Михайличенко via USRP-users wrote:
> Hi,
>
> I am trying to do FFT using corresponding RFNoC block in X310. It works
> if FFT size is 1024 but fails if the size is 2048 or 4096. The block
> does not return any data and I see the following errors in uhd:
>
>
On 05/10/2018 11:16 AM, Devin Kelly via USRP-users wrote:
> Hello,
>
> I'm trying to log underflows. All I really need is a list of timestamps
> (or sample numbers) when an underflow occurs. I can't easily figure out
> how to do this. I'm using UHD 3.9.7.
You will need to call
Hi all,
after release-candidating, we have now finalized the 3.12.0.0 release.
As mentioned before, you might not want to upgrade, but simply run the
3.11.1.0 release which has fewer feature-related changes, but most of
the bugfixes. Here's the decision guidelines which were already in the
RC1
On 06/21/2018 10:57 AM, Ayaz Mahmud via USRP-users wrote:
> Hello All,
>
>
>
> I am trying to build OFDM_MIMO (2 x 2). I have used the blocks from OFDM
> example folders and joined tx & rx together and transmitting/receiving
> over USRP B210.
>
>
>
> My aim is to get a channel state
Can you try recv_frame_size=1024 as part of the device args?
-- M
On 06/13/2018 03:23 PM, Ayaz Mahmud wrote:
> Hi,
>
>
>
> Yes, Its B210 and works with other example like tx_ofdm.
>
>
>
> Ayaz
>
>
>
>
> *From:*
Hi,
we just pushed changes to the script live. However, you should be able
to build an RFNoC image by modifying the rfnoc_ce_auto_inst_n310.v, and
building an RFNoC image, e.g. by running
$ make N310_RFNOC_HG
Cheers,
Martin
On 06/20/2018 06:52 AM, Rob Kossler via USRP-users wrote:
> Hi
Hi all,
after a while of testing and gathering feedback, we have merged the UHD
Python API into master branch. In general, we are happy with its state,
but that doesn't mean it's perfect and complete.
First off, there's at least one known issue with the Python API: It does
not build on Windows.
On 05/02/2018 11:04 AM, Dave NotTelling via USRP-users wrote:
> Are versions >= 3.10 still considered experimental? I thought that any
> version with a release_XXX_XXX_XXX was considered stable. When I run
> cmake ../ on any version 3.10 or higher it warns me that I am on a
> development branch.
Hey Jeff,
at first glance, it looks like you're doing it all right. What's the
size of your input buffer on your custom DUC? Also, can you post a full
log of the streamer setup?
-- M
On 01/09/2018 08:41 AM, Long, Jeffrey P. via USRP-users wrote:
> Looking for some advice and help on RFNOC….
>
Koyel,
CHDR is documented on our manual:
http://files.ettus.com/manual/page_rtp.html#rtp_chdr
However, you typically don't need to care about CHDR. Most blocks
connect to the axi_wrapper, which takes care of any RFNoC internals. Can
you tell us more about what you want to do?
-- M
On
On 01/11/2018 01:38 AM, Дмитрий Михайличенко via USRP-users wrote:
> Hi,
>
> I am trying to understand timestamp tracking in FPGA and noticed one
> possible issue in axi_rate_change.v module .
>
> VITA time in packet headers is counted in ticks of master clock
> frequency, i.e. 200 MHz. For me
This is, in fact, the recommended solution. Our error message needs some
improvement. AFAIK, the images from master branch should be working with
this procedure.
-- M
On 01/19/2018 09:27 AM, Ryan Marlow via USRP-users wrote:
> Alternatively, upgrade your FPGA image to use the latest DDC code.
>
On 01/29/2018 07:37 PM, Tarik Kazaz via USRP-users wrote:
> Hello everyone,
>
>
>
> I am just starting to use RFNoC and I am a bit confused with hardware
> compatibility for RFNoC development.
>
> In order to describe my setup I will list items below:
>
>
>
> 1. I have NI USRP RIO
On 01/26/2018 03:49 PM, Martin K via USRP-users wrote:
> I have Cygwin64 setup in Windows 10
> Vivado 15.4.2 installed and licensed.
>
> [...]
> Some web searching shows that other people have had trouble with the mig
> failing - on both Windows and Linux, but obviously it works for you
> guys.
On 01/31/2018 04:27 AM, Bakshi, Arjun via USRP-users wrote:
> Hi,
>
>
> For a setup where the tx-rx are indoors, can I assume that the USRPs
> transmit power will not cause any significant interference to licensed
> users? I'm not planning on using an amplifier, but I will be sweeping
> over a
On 01/29/2018 10:35 PM, MASDR GS via USRP-users wrote:
> Is there a specific method/process to install external modules into the
> E310? For example, "python bit-array". We would need this module
> installed to run a .grc file using GNUradio directly on the E310. I have
> tired installing bitarray
to reload
> image.
>
> I think instead of .bit, I should flash it with .lvbit if I want to use USRP
> over PCIe with RFNoC? Or I am wrong.
>
> Kind Regards,
>
> Tarik
>
> -Original Message-
> From: USRP-users [mailto:usrp-users-boun...@lists.ettus.com] O
Can confirm: If you're building GNU Radio from source, it'll work with
almost any version of UHD (note that on next branch, we've finally
bumped the minimum UHD version, but it's something like 3.5.5 or so).
-- M
On 02/01/2018 05:29 PM, Ron Economos via USRP-users wrote:
> I think the
Hi all,
it's been a long time since our last major UHD release! We'll have
another one relatively soon, I've just tagged our RC1 and we're
currently testing it for a while before we push it live.
There are hundreds and hundreds of commits with respect to our latest
stable release. The release
On 07/25/2018 02:08 PM, Jim Rorick via USRP-users wrote:
> Folks -
>
> Quick question - saw that 3.13 was released with lots of changes. I’m a poor
> old retired guy using a legacy USRP-1 (WX, LFTX/LFRX daughter boards) with
> GNURADIO for amateur radio. At what version should I lock-in UHD?
Hassna,
you can't build RFNoC images with Vivado_Lab. You need the full Vivado.
-- M
On 07/31/2018 12:14 PM, Ouassal, Hassna via USRP-users wrote:
> Hello,
>
>
>
> I ma wokring through "Build custom image with pre-built RFNoC blocks"
>
>
> I am running the following script:
>
>
On 07/31/2018 11:40 AM, Sirkin, Joshua F. via USRP-users wrote:
> Has sc8 capability been added to the X310? I know it the past it hasn't but
> this page seems to indicate sc8 is generally implemented
> https://files.ettus.com/manual/structuhd_1_1stream__args__t.html. We have an
> X310 with a
On 08/07/2018 12:22 PM, Jay Kuhn via USRP-users wrote:
> Error: RuntimeError: FPGA component `DDC' is revision 1 and UHD supports
> revision 2. Please either upgrade the FPGA image (recommended) or
> downgrade UHD.
Jay,
this means you upgraded the FPGA, but not to the correct version. Please
The actual AXI interface is pretty fast, but for all practical purposes,
if you want to stream samples, you're in the 1-2 Msps range.
You can run benchmark_rate on the device to get an idea. It will top out
at around 12.5 Msps, and you can push it a little if you use taskset to
nail it to one
On 08/15/2018 11:46 AM, Rob Kossler via USRP-users wrote:
> Anyone know the cause & solution to the following startup error? This
> just started today after a cascade of problems which ultimately required
> me to reflash the SD card.
>
> $ uhd_usrp_probe --args="addr=192.168.61.2"
> [INFO] [UHD]
On 08/09/2018 02:31 PM, Rob Kossler via USRP-users wrote:
> When I first started using MPM 3.13, I was pleased to see the fast
> initialization times compared to previous versions. Now, after spending
> the better part of a couple of days troubleshooting issues, I am much
> less thrilled with
On 08/09/2018 08:50 AM, Philip Balister via USRP-users wrote:
> On 08/08/2018 11:49 PM, Walter Maguire via USRP-users wrote:
>> Hi all,
>>
>> The readme file at https://github.com/EttusResearch/meta-ettus seems to
>> be out of date with the current sumo release of poky. meta-ettus seems
>> to
t; as soon as we have a fix.
>
> Regards,
> Michael
>
>
> On Wed, Aug 15, 2018 at 3:52 PM, Martin Braun via USRP-users
> mailto:usrp-users@lists.ettus.com>> wrote:
>
> On 08/09/2018 02:31 PM, Rob Kossler via USRP-users wrote:
> > When I first started us
On 08/24/2018 10:14 AM, Tom McDermott via USRP-users wrote:
> I installed and built gnuradio and UHD some time ago from the SBRAC script.
>
> I am at the head of gnuradio maint-3.7, and am on uhd maint. My
> version of uhd is 3.10.2.0 and my FPGA
> images are also 3.10.2. There appears to be
Andreas,
you *should* be able to use the .bit file. Does this happen when you
build from master branch? The Vivado version is correct.
-- M
On 08/23/2018 02:11 AM, Sylvain Munaut via USRP-users wrote:
> Hi,
>
>> Just for curiosity:
>> The .bit-file is exactly the same as the .bin-file, except
> > TX Dboard: B
> > TX Subdev: Magnesium
> > TX Channel: 2
> > TX DSP: 0
> > TX Dboard: C
> > TX Subdev: Magnesium
> > TX Channel: 3
> > TX DSP: 0
> > TX Dboard
On 07/13/2018 11:41 AM, Rob Kossler via USRP-users wrote:
> Hi,
> With the recent changes to the branches, I understand that users doing
> RFNoC development should be using master branch and users that
> previously used 'maint' should be using 3.10, 3.11, or 3.12 as
> appropriate. I am wondering
On 07/09/2018 03:06 PM, Rob Kossler via USRP-users wrote:
> Using the latest 'rfnoc-devel' (eec24d7b) with my N310, I get the
> following error when running the example program 'benchmark_rate'. The
> error message indicates no PPS detected whenever the channel count is
> greater than one. Note
Louis,
you don't need to start something, but I'm wondering if MPM is maybe
crashing (it's the service that turns the device into a smart USRP).
Can you try ssh'ing in and running
$ ps | grep usrp
You should see something like this:
root@ni-n3xx-***:~# ps | grep usrp
1422 root
On 07/17/2018 09:14 AM, Martin Braun wrote:
> On 07/13/2018 11:41 AM, Rob Kossler via USRP-users wrote:
>> Hi,
>> With the recent changes to the branches, I understand that users doing
>> RFNoC development should be using master branch and users that
>> previously used 'maint' should be using
On 06/27/2018 11:31 AM, Rob Kossler via USRP-users wrote:
> Hi,
> I am getting some unexpected behavior from my N310 using the example
> 'tx_waveforms' utility and stock FPGA image using 'rfnoc-devel'. If I
> simply switch to 'maint', things behave as expected. Here are the issues...
>
> 1.
On 07/12/2018 03:24 PM, Jacob Knoles via USRP-users wrote:
> Hey all,
>
> I have built the latest version of UHD and am trying to load up my X300
> but having major issues.
> I have used the image downloader script to get the latest versions of
> the FPGA image and the image loader to burn the
On 07/12/2018 02:37 PM, Rob Kossler via USRP-users wrote:
> * Inaccurate Tx power output levels using UHD 3.12 or Master. The
> graph below shows the issue of erratic Tx power levels using 3.12
> (right plot) and well-behaved Tx power levels using 3.11 (left plot)
> o this problem
On 07/23/2018 06:57 AM, Rob Kossler wrote:
> Martin,
> Re-flashing the SD card with the 3.12 image fixed my issue!
Rob,
that's great news, and I'm happy you're unstuck! I'm still not entirely
sure what the exact reason is for this is, but here's a short analysis:
On the N310, we use an
Keith,
what's the subdev spec you're using?
There shouldn't have been any issues, and we do test releases using the
N200, but maybe we missed a case here.
-- M
On 07/24/2018 12:42 PM, Keith k via USRP-users wrote:
> Hello all
>
> My multiusrp application will run using 3.11 and below, but
On 07/24/2018 01:59 PM, Martin Braun wrote:
> Rob,
>
> two more comments: The git hash of the FPGA source gets baked into the
> image, and you can read /mboards/0/fpga_version_hash to identify the image.
...and uhd_usrp_probe prints that, too.
-- M
Jason,
this is a tough one. I have no ideas, other than 'throw in a couple of
ILAs and see where it's stuck'.
-- M
On 07/23/2018 12:03 PM, Jason Matusiak via USRP-users wrote:
> I have a flowgraph with a custom RFNoC block in the middle. That block
> has 2 inputs and 2 outputs. Just to get
On 06/28/2018 05:09 AM, Fabian Schwartau via USRP-users wrote:
> Hi everyone,
>
> I am still working on the synchronization of my two USRP X310. Both get
> the same 10 MHz, 1 PPS and LO signals. I made a small piece of code to
> toggle one of the GPIOs at the Aux I/O of each USRP in a timed
On 07/18/2018 05:40 AM, Massimo Bastianon via USRP-users wrote:
> I'm struggling with an easy task: get USRP B200mini working with my code.
>
> I'm using windows 10 x64 and visual studio 2017, I downloded and
> compiled boost 1.67.0 (both 32 and 64 bit). I used udh.dll from UHD
> 3.12.0.0 and
On 06/25/2018 07:20 AM, Andreas Bauer via USRP-users wrote:
> Hello,
>
>
> we are currently working with a USRP X310 with a Twin RX daughter board.
> We are interested on more information about the CHDR protocol.
>
>
> The documentation on https://files.ettus.com/manual/page_rtp.html seems
>
Link should be:
https://github.com/EttusResearch/fpga/blob/f27926410328883a315d5230146936d2d782bd09/usrp3/top/e300/e310_core.v#L319
On 07/24/2018 02:20 PM, Martin Braun wrote:
> I think you might be fine changing this line:
>
>
FYI, we fixed a couple of sc12/8 related issues on our latest master
branch. As Marcus says, if you're doing dual channel on the B210, you
can only go to 30.72 Msps though.
-- M
On 07/24/2018 12:06 PM, Marcus D. Leech via USRP-users wrote:
> On 07/24/2018 03:18 AM, RizThon via USRP-users wrote:
com>> wrote:
>
> Hello Martin
>
> Im using "tx_subdev" : "A:A" in my config.
>
> On Tue, Jul 24, 2018 at 2:16 PM, Martin Braun via USRP-users
> mailto:usrp-users@lists.ettus.com>> wrote:
>
> Keith,
>
> wh
We can't speed up Vivado, unfortunately. Maybe if we design an RFNoC
block that does place and route
So, there's not much you can do. You might be able to use design
checkpoints, but that's an advanced Vivado feature and we don't have
support out of the box for that. You need to know what
On 07/23/2018 03:17 PM, Erik Malone via USRP-users wrote:
> Hi
>
> I'm looking for a way to log all signals when simulating an RFNoC design
> in batch mode. This would help me to run longer tests and then bring up
> a waveform whenever an error occurred. Preferably, I'd like to keep
> within
I think you might be fine changing this line:
https://github.com/EttusResearch/fpgadev/blob/f27926410328883a315d5230146936d2d782bd09/usrp3/top/e300/e310_core.v#L319
...but it's untested and unsupported.
Cheers,
Martin
On 07/22/2018 04:02 AM, carry chen via USRP-users wrote:
> Hi,
>
> list,
>
Hi all,
we have just tagged the 3.13.0.0-RC1 version of UHD. It includes a
variety of improvements for the N310 and B200, and is the first version
to include the Python API. Please find the full changelog below.
When we release the full version, we will also publish up-to-date SD
card images for
v: Magnesium
>
> [00:00:34.792002] Setting device timestamp to 0...
> [INFO] [MULTI_USRP] 1) catch time transition at pps edge
> [INFO] [MULTI_USRP] 2) set times next pps (synchronously)
> [00:00:36.807511] Testing receive rate 12.50 Msps on 2 channels
>
On 09/03/2018 08:21 PM, Chintan Patel via USRP-users wrote:
> Hello,
>
> I have defined a new readback register in the FPGA in the b205_core
> file, adjacent to the lock state register. What is the least invasive
> function call/method in the UHD driver/software to be able to read this
> newly
On Mon, Sep 03, 2018 at 11:39:56AM +, Peng Wang via USRP-users wrote:
>Hi all,
>
>I have couple of USRP X310 and also the PCIe connectivity kit. However, I
>found that the driver [1] says that it can only support up to kernel
>version 4.2.x. Since I am using ubuntu 18.04 with
On 09/03/2018 07:50 PM, Marcus D. Leech via USRP-users wrote:
> On 09/03/2018 12:15 AM, Marcus D. Leech via USRP-users wrote:
>> On 09/03/2018 12:11 AM, RizThon wrote:
>>> Thanks, I'll try to run it on some intel hardware ("Ettus Research
>>> recommends using the Intel Series 7, 8, and 9 USB
On Fri, Aug 31, 2018 at 10:14:27AM -0400, Marcus D. Leech via USRP-users wrote:
> On 08/31/2018 09:26 AM, Flo A. via USRP-users wrote:
> >Hei!
> >
> >I have a very general question regarding the function of the digital mixer
> >as part of the USRP motherboard-DDC:
> >
> >Since the RF signal is
On Wed, Sep 05, 2018 at 11:01:18AM -0400, Marcus D. Leech wrote:
> I also tried benchmark_rate. In random mode, I have no overflow in sc8,
> but in sc16 I have lots of overflows and error messages. Without the
> random mode, I can go up to 36MS/s in sc16, and 56MS/s in sc12! So for
On Fri, Aug 17, 2018 at 01:02:28PM -0400, Daryl Lee via USRP-users wrote:
> In November of 2016, I cross-compiled UHD (git-cloned) on my Ubuntu 16.04
> development host targeting a Zynq chip with Linux built with Petalinux
> 2016.3. Life has passed me by and now I need to re-build the library
have modified
>uhd-fpga/usrp3/tools/scripts/setupenv_base.sh for path to VIvado, 'make
>xsim' doesn't seem to touch it when running.
Did you try running setup_env.sh --vivado-path=?
-- M
> Tien
>On Fri, Feb 9, 2018 at 11:05 AM, Martin Braun via USRP-users
> wro
On Fri, Aug 17, 2018 at 03:53:56PM -0700, Andrew Danowitz via USRP-users wrote:
> Hi,
> I generated an rfnoc fpga image using the latest UHD-fpga tools on the
> rfnoc-devel branch. When I go to run it with the latest UHD on the
> rfnoc-devel branch, I get RuntimeError: RuntimeError: FPGA component
You can do this, as long as you have 2 separate streamers. The master
clock rate will be the same on both, so you can only have different
decimations/interpolations. For example, you could have 10 Msps on one
and 20 Msps on the other if your MCR is 200 MHz (which is the default).
-- M
On
Hi all E310/E312/E313 users,
I would like to focus people's attention to some changes we have just
started rolling out, and will continue to roll out over the next months.
Executive Summary
=
- For those requiring *no* RFNoC support whatsoever, just plain RX/TX
and UHD support,
On 07/10/2018 07:14 PM, Rob Kossler wrote:
> Thanks Michael,
> Is there any place where the minor branches are summarized? In other
> words, what are the primary differences among 3.9, 3.10, 3.11, and 3.12?
Rob,
good question. We provide a changelog for that:
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