The rk3588_pll_set_rate() function contains special handling intended
only for PLLs on RK3588 that are also applied to PLLs on RK3576.
This special handling should ideally be moved from the common pll funcs
into the clk_rk3588 driver. Add IS_ENABLED() guards as an initial step
to limit this special handling to PLLs on RK3588 targets.
Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
---
Changes in v2:
- Add fixes tag
- Collect r-b tag
---
drivers/clk/rockchip/clk_pll.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index a2b16543e811..e00975565a0c 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -459,7 +459,7 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock
*pll,
* When power on or changing PLL setting,
* we must force PLL into slow mode to ensure output stable clock.
*/
- if (pll_id == 3)
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && pll_id == 3)
rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1);
if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
@@ -467,15 +467,15 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock
*pll,
pll->mode_mask << pll->mode_shift,
RKCLK_PLL_MODE_SLOW << pll->mode_shift);
}
- if (pll_id == 0)
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && pll_id == 0)
rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
pll->mode_mask << 6,
RKCLK_PLL_MODE_SLOW << 6);
- else if (pll_id == 1)
+ else if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && pll_id == 1)
rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
pll->mode_mask << 6,
RKCLK_PLL_MODE_SLOW << 6);
- else if (pll_id == 2)
+ else if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && pll_id == 2)
rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
pll->mode_mask << 14,
RKCLK_PLL_MODE_SLOW << 14);
@@ -511,7 +511,7 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock
*pll,
pll->mode_mask << pll->mode_shift,
RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
}
- if (pll_id == 0) {
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && pll_id == 0) {
rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
pll->mode_mask << 6,
2 << 6);
@@ -521,7 +521,7 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock
*pll,
rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1),
RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
0 << RK3588_CORE_B13_DIV_SHIFT);
- } else if (pll_id == 1) {
+ } else if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && pll_id == 1) {
rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
pll->mode_mask << 6,
2 << 6);
@@ -531,7 +531,7 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock
*pll,
rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1),
RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
0 << RK3588_CORE_B13_DIV_SHIFT);
- } else if (pll_id == 2) {
+ } else if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && pll_id == 2) {
rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
pll->mode_mask << 14,
2 << 14);
@@ -549,7 +549,7 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock
*pll,
0 << RK3588_CORE_L02_DIV_SHIFT);
}
- if (pll_id == 3)
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && pll_id == 3)
rk_clrsetreg(base + 0x84c, 0x1 << 1, 0);
debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
--
2.55.0
