The PPLL registers belong to the PHP CRU, rather than the PMU CRU.
Rename the register macro and update the PPLL entry to reflect this.
Fixes: 165d258386a7 ("arm: rockchip: Add cru header for rk3588")
Signed-off-by: Jonas Karlman <[email protected]>
---
Changes in v2:
- Split from "rk3588: Fix trivial clock configuration errors"
- Add fixes tag
---
arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 +-
drivers/clk/rockchip/clk_rk3588.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index c83010e518ee..39295adeb38a 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -126,10 +126,10 @@ struct pll_rate_table {
#define RK3588_SDMMC_CON0 0xC30
#define RK3588_SDMMC_CON1 0xC34
+#define RK3588_PHP_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE +
0x800)
#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE +
0xa00)
-#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE +
0x300)
#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE +
0x800)
#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE +
0xa00)
diff --git a/drivers/clk/rockchip/clk_rk3588.c
b/drivers/clk/rockchip/clk_rk3588.c
index 872e36748caf..3b21c7f8465d 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -61,7 +61,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = {
RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
[NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
- [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
+ [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PHP_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, ROCKCHIP_PLL_FIXED_MODE,
rk3588_pll_rates),
#ifdef CONFIG_XPL_BUILD
--
2.55.0
