[PATCH v2 09/37] clk: rockchip: rk3568: Use PWM0 divider shift

[Jonas Karlman]

Use CLK_PWM0_DIV_SHIFT rather than CLK_PWM0_SEL_SHIFT when writing
the PWM0 divider and the oscillator was selected as parent.

This has no behavior change, shifting zero by either constant still
result in same zero value.

Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.sch...@cherry.de>
---
Changes in v2:
- Split from "rk3568: Fix trivial clock configuration errors"
- Add fixes tag
- Collect r-b tag
---
 drivers/clk/rockchip/clk_rk3568.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index 88bbfb68cac6..398f76488470 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -294,7 +294,7 @@ static ulong rk3568_pwm_set_pmuclk(struct 
rk3568_pmuclk_priv *priv,
                                     CLK_PWM0_SEL_MASK | CLK_PWM0_DIV_MASK,
                                     (CLK_PWM0_SEL_XIN24M <<
                                      CLK_PWM0_SEL_SHIFT) |
-                                    0 << CLK_PWM0_SEL_SHIFT);
+                                    0 << CLK_PWM0_DIV_SHIFT);
                } else {
                        src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);
                        assert(src_clk_div - 1 <= 127);
-- 
2.55.0