The CLK_PWM0 divider mask is used twice, leaving the parent selection
unchanged. Change to use the intended CLK_PWM0 parent selection mask.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
---
Changes in v2:
- Split from "rk3568: Fix trivial clock configuration errors"
- Add fixes tag
- Collect r-b tag
---
drivers/clk/rockchip/clk_rk3568.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3568.c
b/drivers/clk/rockchip/clk_rk3568.c
index 86881728667a..88bbfb68cac6 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -299,7 +299,7 @@ static ulong rk3568_pwm_set_pmuclk(struct
rk3568_pmuclk_priv *priv,
src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);
assert(src_clk_div - 1 <= 127);
rk_clrsetreg(&pmucru->pmu_clksel_con[6],
- CLK_PWM0_DIV_MASK | CLK_PWM0_DIV_MASK,
+ CLK_PWM0_SEL_MASK | CLK_PWM0_DIV_MASK,
(CLK_PWM0_SEL_PPLL << CLK_PWM0_SEL_SHIFT) |
(src_clk_div - 1) << CLK_PWM0_DIV_SHIFT);
}
--
2.55.0
