The k parameter supplies the fractional part of an rk3588-style PLL
rate. When changing from a fractional rate to an integer rate, the
k value is left unchanged, leaving the old fractional part active.
Always write k to the register, including zero, so integer rates clear
any prior fractional part. This also matches how Linux configures these
PLLs.
Fixes: b851c006a150 ("clk: rockchip: pll: Add pll_rk3588 type for rk3588")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
---
Changes in v2:
- Update commit message
- Add fixes tag
- Collect r-b tag
---
drivers/clk/rockchip/clk_pll.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 5de930e41dce..6664fe3921b8 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -490,11 +490,9 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock
*pll,
RK3588_PLLCON1_S_MASK),
(rate->p << RK3588_PLLCON1_P_SHIFT |
rate->s << RK3588_PLLCON1_S_SHIFT));
- if (rate->k) {
- rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),
- RK3588_PLLCON2_K_MASK,
- rate->k << RK3588_PLLCON2_K_SHIFT);
- }
+ rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),
+ RK3588_PLLCON2_K_MASK,
+ rate->k << RK3588_PLLCON2_K_SHIFT);
/* Power up */
rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1),
RK3588_PLLCON1_PWRDOWN);
--
2.55.0
