The PPLL on RK3588 and RK3576 has no PLL mode register and cannot switch between slow, deep slow or normal mode.
Extend ROCKCHIP_PLL_FIXED_MODE support to the pll_rk3588 type and mark both PPLLs with this flag. Skip mode register writes when changing rates and treat the PLLs as operating in normal mode when reading rates. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Quentin Schulz <[email protected]> --- Changes in v2: - Update comment in clock.h header - Update commit message - Collect r-b tag --- arch/arm/include/asm/arch-rockchip/clock.h | 2 +- drivers/clk/rockchip/clk_pll.c | 21 +++++++++++++-------- drivers/clk/rockchip/clk_rk3576.c | 3 ++- drivers/clk/rockchip/clk_rk3588.c | 3 ++- 4 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 8d3819778eb1..43b63f72703d 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -19,7 +19,7 @@ struct udevice; * PLL flags */ #define ROCKCHIP_PLL_SYNC_RATE BIT(0) -/* normal mode only. now only for pll_rk3036, pll_rk3328 type */ +/* normal mode only. */ #define ROCKCHIP_PLL_FIXED_MODE BIT(1) enum { diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 6664fe3921b8..a2b16543e811 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -462,9 +462,11 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, if (pll_id == 3) rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1); - rk_clrsetreg(base + pll->mode_offset, - pll->mode_mask << pll->mode_shift, - RKCLK_PLL_MODE_SLOW << pll->mode_shift); + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { + rk_clrsetreg(base + pll->mode_offset, + pll->mode_mask << pll->mode_shift, + RKCLK_PLL_MODE_SLOW << pll->mode_shift); + } if (pll_id == 0) rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), pll->mode_mask << 6, @@ -504,8 +506,11 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); } - rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, - RKCLK_PLL_MODE_NORMAL << pll->mode_shift); + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { + rk_clrsetreg(base + pll->mode_offset, + pll->mode_mask << pll->mode_shift, + RKCLK_PLL_MODE_NORMAL << pll->mode_shift); + } if (pll_id == 0) { rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), pll->mode_mask << 6, @@ -566,10 +571,10 @@ static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, con = readl(base + pll->mode_offset); shift = pll->mode_shift; - if (pll_id == 8) - mode = RKCLK_PLL_MODE_NORMAL; - else + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) mode = (con & (pll->mode_mask << shift)) >> shift; + else + mode = RKCLK_PLL_MODE_NORMAL; switch (mode) { case RKCLK_PLL_MODE_SLOW: return OSC_HZ; diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index db8ce25852fd..92bde425b0ee 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -57,7 +57,8 @@ static struct rockchip_pll_clock rk3576_pll_clks[] = { [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3576_PLL_CON(112), RK3576_MODE_CON0, 2, 15, 0, rk3576_24m_pll_rates), [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128), - RK3576_MODE_CON0, 10, 15, 0, rk3576_24m_pll_rates), + RK3576_MODE_CON0, 10, 15, ROCKCHIP_PLL_FIXED_MODE, + rk3576_24m_pll_rates), }; #ifdef CONFIG_SPL_BUILD diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index be401a9faeec..b9fd4bec311b 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -62,7 +62,8 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = { [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120), RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128), - RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), + RK3588_MODE_CON0, 10, 15, ROCKCHIP_PLL_FIXED_MODE, + rk3588_pll_rates), #ifdef CONFIG_XPL_BUILD /* * The SPLL is part of the SBUSCRU, not the main CRU and as -- 2.55.0
