This series fixes a few trivial copy-paste mistakes and other misc clock issues for RK35xx SoCs.
Some of these fixes have only been compile tested as it involves clocks or rates that are rarely used in U-Boot. The 'special pll handling' should ideally be moved into clk_rk3588 driver, something that can be done in a future follow-up series. Similarly, any refactoring has been held back for a future follow-up series. Changes in v2: - Add patch to fix automatic PLL fractional calculation - Add patch to request a working rate for saradc on RK3528 - Split "Fix trivial clock configuration errors" - Update commit messages - Add fixes tag - Collect r-b tags Jonas Karlman (37): clk: rockchip: pll: Fix fractional PLL rate calculation clk: rockchip: pll: Fix automatic PLL fractional parameter calculation clk: rockchip: pll: Always write the dsmpd flag clk: rockchip: pll: Always write the k parameter clk: rockchip: pll: Use PLL_FIXED_MODE flag on RK3588/RK3576 PPLL clk: rockchip: pll: Limit special rk3588_pll handling to RK3588 clk: rockchip: rk3568: Use correct clock id for GPLL clk: rockchip: rk3568: Fix PWM0 parent selection mask clk: rockchip: rk3568: Use PWM0 divider shift clk: rockchip: rk3568: Use correct PLL rate for CLK_MAC0_2TOP clk: rockchip: rk3588: Use GPLL rate for CLK_TSADC clk: rockchip: rk3588: Use correct PLL rate for SCLK_UARTx divider clk: rockchip: rk3588: Fix ACLK_BUS_ROOT divider encoding clk: rockchip: rk3588: Set ACLK_BUS_ROOT to 375 MHz clk: rockchip: rk3588: Remove redundant PLL register macros clk: rockchip: rk3588: Rename PPLL register macro clk: rockchip: rk3588: Align BxPLL entries in PLL table clk: rockchip: rk3588: Use SPLL_HZ constant clk: rockchip: rk3576: Use correct mode register for VPLL clk: rockchip: rk3576: Fix ACLK_TOP_MID parent selection clk: rockchip: rk3576: Fix I2C rate selection clk: rockchip: rk3576: Fix CLK_I2C8 rate change clk: rockchip: rk3576: Use correct clock register for CLK_SARADC clk: rockchip: rk3576: Use correct TSADC clock register clk: rockchip: rk3576: Use correct PLL rate for UART fractional clocks clk: rockchip: rk3576: Use correct PLL rate for UART divisor clk: rockchip: rk3576: Rename PPLL register macro clk: rockchip: rk3576: Remove unused BPLL register macro clk: rockchip: rk3576: Group LPLL register macro with CCI macros clk: rockchip: rk3576: Align BPLL entry in PLL table clk: rockchip: rk3528: Return correct rate for CLK_PWMx clk: rockchip: rk3528: Fix VOP clock configuration clk: rockchip: rk3528: Align PPLL entry in PLL table clk: rockchip: rk3506: Return correct rate for CLK_I2C0 and CLK_I2C1 clk: rockchip: rk3568: Drop unused GRF syscon lookup clk: rockchip: rk3588: Drop unused GRF syscon lookup adc: rockchip-saradc: Use 3 MHz clock rate for RK3528 arch/arm/include/asm/arch-rockchip/clock.h | 2 +- .../include/asm/arch-rockchip/cru_rk3568.h | 1 - .../include/asm/arch-rockchip/cru_rk3576.h | 5 +- .../include/asm/arch-rockchip/cru_rk3588.h | 6 +- drivers/adc/rockchip-saradc.c | 2 +- drivers/clk/rockchip/clk_pll.c | 75 ++++++++++--------- drivers/clk/rockchip/clk_rk3506.c | 2 + drivers/clk/rockchip/clk_rk3528.c | 7 +- drivers/clk/rockchip/clk_rk3568.c | 12 +-- drivers/clk/rockchip/clk_rk3576.c | 26 +++---- drivers/clk/rockchip/clk_rk3588.c | 35 ++++----- 11 files changed, 82 insertions(+), 91 deletions(-) -- 2.55.0
