The clock driver always reports ACLK_BUS_ROOT rate as 375 MHz. However,
the clock is initialized to use GPLL as parent and a target rate of
300 MHz, with GPLLs typicall 1.188 GHz rate the clock ends up at 297 MHz.
Change to use CPLL as parent and request a 375 MHz rate, the same rate
that is already being reported by the driver and what the SoC DT uses in
assigned-clock-rates. With CPLLs typicall 1.5 GHz rate, this matches the
parent and rate Linux typically ends up using for this clock.
Fixes: 716ed2a8c0bb ("clk: rockchip: rk3588: add hardcoded assigned clocks
values")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
---
Changes in v2:
- Split from "rk3588: Fix ACLK_BUS_ROOT rate set during probe"
- Add fixes tag
- Collect r-b tag
---
drivers/clk/rockchip/clk_rk3588.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3588.c
b/drivers/clk/rockchip/clk_rk3588.c
index 50e0a27819df..872e36748caf 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1923,10 +1923,10 @@ static void rk3588_clk_init(struct rk3588_clk_priv
*priv)
{
int ret, div;
- div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz);
+ div = DIV_ROUND_UP(CPLL_HZ, 375 * MHz);
rk_clrsetreg(&priv->cru->clksel_con[38],
- ACLK_BUS_ROOT_SEL_MASK |
- ACLK_BUS_ROOT_DIV_MASK,
+ ACLK_BUS_ROOT_SEL_MASK | ACLK_BUS_ROOT_DIV_MASK,
+ (ACLK_BUS_ROOT_SEL_CPLL << ACLK_BUS_ROOT_SEL_SHIFT) |
(div - 1) << ACLK_BUS_ROOT_DIV_SHIFT);
if (priv->cpll_hz != CPLL_HZ) {
--
2.55.0
