[PATCH v2 10/37] clk: rockchip: rk3568: Use correct PLL rate for CLK_MAC0_2TOP

[Jonas Karlman]

Use the PPLL rate instead of HPLL rate when the PPLL is parent of the
CLK_MAC0_2TOP clock.

Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.sch...@cherry.de>
---
Changes in v2:
- Split from "rk3568: Fix trivial clock configuration errors"
- Add fixes tag
- Collect r-b tag
---
 drivers/clk/rockchip/clk_rk3568.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index 398f76488470..940b824103cc 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1882,7 +1882,7 @@ static ulong rk3568_gmac_src_get_clk(struct 
rk3568_clk_priv *priv,
        case CLK_MAC0_2TOP_SEL_25M:
                return 25 * MHz;
        case CLK_MAC0_2TOP_SEL_PPLL:
-               return rk3568_pmu_pll_get_rate(priv, HPLL);
+               return rk3568_pmu_pll_get_rate(priv, PPLL);
        default:
                return -ENOENT;
        }
-- 
2.55.0