The GPLL entry incorrectly uses PLL_HPLL. Use PLL_GPLL to match the
PLL represented by this entry.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
---
Changes in v2:
- Split from "rk3568: Fix trivial clock configuration errors"
- Add fixes tag
- Collect r-b tag
---
drivers/clk/rockchip/clk_rk3568.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3568.c
b/drivers/clk/rockchip/clk_rk3568.c
index bb49af358e60..86881728667a 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -77,7 +77,7 @@ static struct rockchip_pll_clock rk3568_pll_clks[] = {
RK3568_MODE_CON, 2, 10, 0, NULL),
[CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
RK3568_MODE_CON, 4, 10, 0, rk3568_pll_rates),
- [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16),
+ [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3568_PLL_CON(16),
RK3568_MODE_CON, 6, 10, 0, rk3568_pll_rates),
[NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32),
RK3568_MODE_CON, 10, 10, 0, rk3568_pll_rates),
--
2.55.0
