Re: Newbie Questions!

2006-08-12 Thread Shmuel Metz (Seymour J.)
In
[EMAIL PROTECTED],
on 07/19/2006
   at 05:02 PM, SUBSCRIBE IBM-MAIN tdell T'[EMAIL PROTECTED]
said:

PDP's have a bus arbitration or granting scheme,

DEC had a number of very different processors with PDP in their
name; I suspect that you're thinking of the PDP-11, and I'm not sure
that it is even true for all PDP-11 models. It's certainly not true
for, e.g., PDP-5.

Mainframe's as far I knew didn't.

Again, there are a lot of very different mainframe implementations,
even within the same line. Many of them have bus arbitration.
 
-- 
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Re: Newbie Questions!

2006-07-20 Thread Hunkeler Peter (KIUB 34)
  Through the ISPVCALL STATUS function, I found that the system I'm
  on is a zArch 2064 with 4 CPUs; however, is there a way I can
retrieve
[snip]
All that being said it could be a 2064-104, 2064-1C4, or a 2064-2C4
depending on features.  You can use the command
D M=CPU to find your model number.

The ISPVCALL command tells you the number of General Purpose processors
(GCPs) the current LPAR (i.e. z/OS image) has. The machine itself might 
have more GCPs being used by other LPARs (z/OS or other operating system
images).

Also there are zAAP and zIIP processors which, while physically
identical
to GCPs, are only being used to execute certain types of threads (JAVA
tasks and DB2 SRBs). Those processors do not appear in the model number.

If you have access to RMF, a partition data report will give you more
details about the physical machine.

Peter Hunkeler
CREDIT SUISSE

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Re: newbie questions!

2006-07-19 Thread Jon Brock
I strongly disagree.  Some good programmers are arrogant, but then again so are 
some bad ones.  The best ones realize that they don't -- and can't -- know it 
all, and they make allowances for it.  

Edsger Dijkstra even made humility the point of a paper he delivered at a 
Turing Award lecture, said paper being entitled The Humble Programmer.  His 
argument was that most of the art/science of programming centers around trying 
to compensate for our finite cranial capacity.  This is indisputably true.  

As Steve McConnell puts it, The people who are the best at programming are the 
people who realize how small their brains are.  They are humble.  The prople 
who are the worst at programming are the people who refuse to accept the fact 
that their brains aren't equal to the task.  

That may be a different sense of the word humility than you were discussing, 
but I think it is relevant.  In more practical terms, arrogant programmers all 
too frequently become prima donnas, which often affords them the opportunity to 
become the best programmer nobody wants to work with.

Jon




snip
'Humility'?  Anyone entering a new field has perforce much to learn from 
some of its experienced denizens, but humility should be short-lived.

No good programmer I have every known was at all humble, and the great ones 
were/are well aware of their abilities, even [some few of them] arrogant 
about their skills.
/snip

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Re: Newbie Questions!

2006-07-19 Thread Tom Marchant
On Tue, 18 Jul 2006 15:46:27 -0400, Kuredjian, Michael 
[EMAIL PROTECTED] wrote:

I'm currently in University on my Co-op term as a COBOL programmer for 
host systems (zOS). I have a few basic questions regarding the 
zArchitecture that I can't seem to elicit answers to from my co-workers. 
The questions are as follows:

1. zOS has a kernel called the BCP, or Base Control Program. In Linux
or Windows, it's established that the kernel runs on a general purpose
CPU( PowerPC, x86, MIPS, etc...); however, I would like to know if
such a central CPU exists in the mainframe,  and if that central CPU
is of some common architecture like, POWER. If not, are there any
documents that I can look into that will describe the CPU
architecture for me?

While the processor has been enhanced over the years, the CPU may be the 
first general purpose architecture still in existence.  The 360 
architecture is still an integral and important part of z/Architecture, and 
almost any program written for 360 will run without being modified on 
z/Architecture.

2. ESCON and FICON are data busses used for external storage devices,
but what does the mainframe use for internal data bus, InfiniBand,
HyperTransport?

IBM doesn't make the internal details available.  In order to perform, 
there is a lot of point-to-point interconnect.  Paths to memory are very 
wide, again to improve performance.  I can't seem to find the last 
reference I found, but I think it's 256 bytes.  FICON is essentially Fibre 
Channel with extra layers to improve security.

3. Does the mainframe use common interconnects on the hardware level?
I'm thinking of PCIe, PCI-X, MCA, or PCI.

AS someone mentioned, there are PCI slots for cryptographic processors, but 
for general use, none of those is fast enough.  Connections from memory to 
the channels is through 16 Self Timed Interconnect (STI) busses per book (a 
maximum of 64), each of which is capable of independently transferring 2.7 
Gigabytes per second.  The z9 EC can support up to 336 FICON channels, and 
STI is how the data is transferred between the channels and memory.

The channels on the mainframe do not talk directly to devices, but to 
control units, which are specialized processors that relieve the processor 
of the details of most of the workings of the device.

There are tons of details on the IBM web site.  Try these, for example:
http://www-03.ibm.com/systems/z/hardware/
http://www-03.ibm.com/servers/eserver/zseries/zos/

Good luck, and welcome to the platform!

Tom Marchant

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Re: Newbie Questions!

2006-07-19 Thread Kuredjian, Michael
Thanks to all of those that are replying. I've found a wealth of information in 
the IBM RD website. They have an issue that details the architecture of the 
z990 CPU very clearly. It seems as through IBM is modernizing the arch to 
handle more OOE/Superscalar execution as they make a push to SOA and e-business 
models. Out of curiosity, I've started poking around the system I've access to 
through ISPF to find out more regarding the hardware. Through the ISPVCALL 
STATUS function, I found that the system I'm on is a zArch 2064 with 4 CPUs; 
however, is there a way I can retrieve the model # of this system as well?

-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED]
Behalf Of Tom Marchant
Sent: Wednesday, July 19, 2006 10:35 AM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Newbie Questions!


On Tue, 18 Jul 2006 15:46:27 -0400, Kuredjian, Michael 
[EMAIL PROTECTED] wrote:

I'm currently in University on my Co-op term as a COBOL programmer for 
host systems (zOS). I have a few basic questions regarding the 
zArchitecture that I can't seem to elicit answers to from my co-workers. 
The questions are as follows:

1. zOS has a kernel called the BCP, or Base Control Program. In Linux
or Windows, it's established that the kernel runs on a general purpose
CPU( PowerPC, x86, MIPS, etc...); however, I would like to know if
such a central CPU exists in the mainframe,  and if that central CPU
is of some common architecture like, POWER. If not, are there any
documents that I can look into that will describe the CPU
architecture for me?

While the processor has been enhanced over the years, the CPU may be the 
first general purpose architecture still in existence.  The 360 
architecture is still an integral and important part of z/Architecture, and 
almost any program written for 360 will run without being modified on 
z/Architecture.

2. ESCON and FICON are data busses used for external storage devices,
but what does the mainframe use for internal data bus, InfiniBand,
HyperTransport?

IBM doesn't make the internal details available.  In order to perform, 
there is a lot of point-to-point interconnect.  Paths to memory are very 
wide, again to improve performance.  I can't seem to find the last 
reference I found, but I think it's 256 bytes.  FICON is essentially Fibre 
Channel with extra layers to improve security.

3. Does the mainframe use common interconnects on the hardware level?
I'm thinking of PCIe, PCI-X, MCA, or PCI.

AS someone mentioned, there are PCI slots for cryptographic processors, but 
for general use, none of those is fast enough.  Connections from memory to 
the channels is through 16 Self Timed Interconnect (STI) busses per book (a 
maximum of 64), each of which is capable of independently transferring 2.7 
Gigabytes per second.  The z9 EC can support up to 336 FICON channels, and 
STI is how the data is transferred between the channels and memory.

The channels on the mainframe do not talk directly to devices, but to 
control units, which are specialized processors that relieve the processor 
of the details of most of the workings of the device.

There are tons of details on the IBM web site.  Try these, for example:
http://www-03.ibm.com/systems/z/hardware/
http://www-03.ibm.com/servers/eserver/zseries/zos/

Good luck, and welcome to the platform!

Tom Marchant

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Re: Newbie Questions!

2006-07-19 Thread Ron and Jenny Hawkins
Tom,

 FICON is essentially Fibre
 Channel with extra layers to improve security.

Extra layers to improve security?

I would have said that essentially FICON is ESCON encapsulated in Fibre
Channel Protocol.

Ron

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Re: Newbie Questions!

2006-07-19 Thread Bruce Black


I would have said that essentially FICON is ESCON encapsulated in Fibre
Channel Protocol.
Ron, I don't pretend to be expert in channel protocols, but from what I 
read the FICON protocols are quite different from ESCON.  I've read that 
ESCON does a channel-CU conversation for each CCW in a chain, with data 
blocks in between, but FICON batches up CCWs and usually sends an entire 
CCW chain in one block. 

Did I dream this, or would be more accurate to say that FICON is zArch 
channel programming encapsulated in FCP?   I also believed that the 
FICON extensions to FCP were to accomplish this, not for security


--
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Senior Software Developer
Innovation Data Processing

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Re: Newbie Questions!

2006-07-19 Thread Shmuel Metz (Seymour J.)
In
[EMAIL PROTECTED],
on 07/18/2006
   at 05:26 PM, SUBSCRIBE IBM-MAIN tdell T'[EMAIL PROTECTED]
said:

To recap..

Much of that is wrong.

Mainframes don't actually have a backplane that's governed by a bus
arbitrator scheme as some implementation have done in the past. 

Some do.

That channel subsystem as it was called, was strictly a place for the
more experienced coders so beware. It has it's own methodology when
it came to writing code.

You don't write code for the channel. There is a very limited set of
opcodes for channel command words and there is no provision for even
simple computation.

The channel subsystem is really a processor in it's own right.

On some mainfames, not on all. The channels on, e.g., the 360/40,
360/50, 370/145, 370/155, worked by cycle stealing.

 All throughout the architecture you'll find various processors that
are part of the machine architectural composition, 

No, that's implementation.
 
-- 
 Shmuel (Seymour J.) Metz, SysProg and JOAT
 ISO position; see http://patriot.net/~shmuel/resume/brief.html 
We don't care. We don't have to care, we're Congress.
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Re: Newbie Questions!

2006-07-19 Thread Shmuel Metz (Seymour J.)
In
[EMAIL PROTECTED],
on 07/18/2006
   at 03:46 PM, Kuredjian, Michael [EMAIL PROTECTED]
said:

1. zOS has a kernel called the BCP, or Base Control Program.

Now. The term kernel in CS carries with it a load of assumptions
that simply don't apply; they aren't even wrong, but totally
meaningless. You might think of the nucleus as being the kernel, but
that would still be horribly misleading. The BCP includes a host of
functions that run in normal address spaces and tasks, roughly
comparable to process and threads in the Unix world.

In Linux or Windows, it's established that the kernel runs on a
general purpose CPU( PowerPC, x86, MIPS, etc...); however, I would
like to know if such a central CPU exists in the mainframe,  and if
that central CPU is of some common architecture like, POWER.

There are many mainframes. The ones that z/OS runs on have
architectures called S/390 and zSeries.

If not, are there any documents that I can look into that will
describe the CPU architecture for me?

Wouldn't such documents mean that there *is* a common architecture?
As, in fact, there is, and it is described in the zSeries Principles
of Operation.

2. ESCON and FICON are data busses used for external storage
devices, but what does the mainframe use for internal data bus,
InfiniBand, HyperTransport?

It's not part of the architecture what it uses internally, and
different processor complexes use different busses, none of which are
in your list.

3. Does the mainframe use common interconnects on the hardware
level? I'm thinking of PCIe, PCI-X, MCA, or PCI.

The architecture defines interconnects that are not in your list. Some
processor complexes have PCI slots, but that is *not* part of the
architecture.

Please skim[1] PoOps and then come back with the questions it raises.

[1] You probably don't want to read it straight through just yet.

-- 
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Re: newbie questions!

2006-07-19 Thread Shmuel Metz (Seymour J.)
In [EMAIL PROTECTED], on 07/19/2006
   at 12:55 AM, john gilmore [EMAIL PROTECTED] said:

No good programmer I have every known was at all humble,

That depends on what you mean be humility; every good programmer
that I've met was aware of his own abilities *and* of his own
limitations.

even [some few of them] arrogant about their skills.

When arrogance keeps them from seeing problems in their code then they
aren't great programmers, or even good programmers.
 
-- 
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 ISO position; see http://patriot.net/~shmuel/resume/brief.html 
We don't care. We don't have to care, we're Congress.
(S877: The Shut up and Eat Your spam act of 2003)

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Re: newbie questions!

2006-07-19 Thread Shmuel Metz (Seymour J.)
In [EMAIL PROTECTED],
on 07/19/2006
   at 09:57 AM, Jon Brock [EMAIL PROTECTED] said:

Edsger Dijkstra even made humility the point of a paper he delivered
at a Turing Award lecture, said paper being entitled The Humble
Programmer. 

Unfortunately, he displayed supreme arrogance in that very paper :-(

In more practical terms, arrogant programmers all too frequently
become prima donnas,

That's the least of the problems. They develop blind spots that cause
bugs to remain unresolved.

-- 
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 ISO position; see http://patriot.net/~shmuel/resume/brief.html 
We don't care. We don't have to care, we're Congress.
(S877: The Shut up and Eat Your spam act of 2003)

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Re: Newbie Questions!

2006-07-19 Thread Gabriel Tully

On 7/19/06, Kuredjian, Michael [EMAIL PROTECTED] wrote:



 Through the ISPVCALL STATUS function, I found that the system I'm on is
a zArch 2064 with 4 CPUs; however, is there a way I can retrieve the model #
of this system as well?




2064 is the model number, which is a zSeries 900 processor.

Gabe

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Re: Newbie Questions!

2006-07-19 Thread Gabriel Tully

On 7/19/06, Edward Jaffe [EMAIL PROTECTED] wrote:




2064 is the model number, which is a zSeries 900 processor.


No. 2064 is the CPU type. The model number is a (usually three digit)
number that follows the type, separated by a hyphen. For example,
2064-101.




Semantics in my opinion.  I've seen numerous references to both.  I figured
since the OP started this newbie thread I would KISS.  But I agree and defer
to you.

Gabe

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Re: Newbie Questions!

2006-07-19 Thread SUBSCRIBE IBM-MAIN tdell
To reap what I have sowed.

Most programmers have confidence, which is not to be confused with
arrogance, which has no place in a craft like this. This is a practiced
craft, so I haven't met anybody , with the exception of the Scientist's at
Palo Alto , who could call themselves above their craft (even they where a
humble lot) and those guys where good.

PDP's have a bus arbitration or granting scheme, Mainframe's as far I knew
didn't. They may have used other schemes, but as far as I could tell, I
didn't know of any. As as I was taught , the CS used an interrupt driven
scheme for device allocation. Beyond that I leave those areas for the more
seasoned experts who know. CDC's or Ahmdal's,  Burroughs where not my take,
they could have used anything I , and would have not known any different

CCW coding to which I was referring is the way you custom programmed
various I/O device ( including CKD, printers or tape, or Card reader or
punches, even 3770/3780['s ). Much of that coding was handled by the more
experienced coders, who new something about the target devices. General
assembler application programming,  where I did my coding was another set
of skills entirely.

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Re: Newbie Questions!

2006-07-19 Thread Gabriel Tully


 Through the ISPVCALL STATUS function, I found that the system I'm
 on is a zArch 2064 with 4 CPUs; however, is there a way I can retrieve
the
 model # of this system as well?

 2064 is the model number, which is a zSeries 900 processor.

No. 2064 is the CPU type. The model number is a (usually three digit)
number that follows the type, separated by a hyphen. For example,
2064-101.




All that being said it could be a 2064-104, 2064-1C4, or a 2064-2C4
depending on features.  You can use the command
D M=CPU to find your model number.

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Re: Newbie Questions!

2006-07-19 Thread Ron and Jenny Hawkins
Bruce,

 Ron, I don't pretend to be expert in channel protocols, but from what I
 read the FICON protocols are quite different from ESCON.  I've read that
 ESCON does a channel-CU conversation for each CCW in a chain, with data
 blocks in between, but FICON batches up CCWs and usually sends an entire
 CCW chain in one block.
 
 Did I dream this, or would be more accurate to say that FICON is zArch
 channel programming encapsulated in FCP?   I also believed that the
 FICON extensions to FCP were to accomplish this, not for security
 

There are probably a dozen ways to say it simply, but simple must ignore the
nuances. FCP is a transport protocol that we can stuff things inside of.

We could say that FICON is CKD over FCP, ESCON over FCP or zArch
channel programming encapsulated in FCP? There are changes that FCP allow to
occur (as you described), and there are ESCON limitations that remained in
FICON for quite some time (e.g. single hop ISL). 

Personally I feel that ESCON on FCP is a comparable generalisation to SCSI
over FCP and IP over FCP.

Ron

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Newbie Questions!

2006-07-18 Thread Kuredjian, Michael
I'm currently in University on my Co-op term as a COBOL programmer for host 
systems (zOS). I have a few basic questions regarding the zArchitecture that I 
can't seem to elicit answers to from my co-workers. The questions are as 
follows:

1. zOS has a kernel called the BCP, or Base Control Program. In Linux or 
Windows, it's established that the kernel runs on a general purpose CPU( 
PowerPC, x86, MIPS, etc...); however, I would like to know if such a central 
CPU exists in the mainframe,  and if that central CPU is of some common 
architecture like, POWER. If not, are there any documents that I can look into 
that will describe the CPU architecture for me?

2. ESCON and FICON are data busses used for external storage devices, but what 
does the mainframe use for internal data bus, InfiniBand, HyperTransport?

3. Does the mainframe use common interconnects on the hardware level? I'm 
thinking of PCIe, PCI-X, MCA, or PCI.

That's all for now, but I'm sure subsequent answers will generate follow-up 
questions on my part. Thanks for taking the time to read this!

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Re: Newbie Questions!

2006-07-18 Thread McKown, John
I'll take a try at a few of these.
 -Original Message-
 From: IBM Mainframe Discussion List 
 [mailto:[EMAIL PROTECTED] On Behalf Of Kuredjian, Michael
 Sent: Tuesday, July 18, 2006 2:46 PM
 To: IBM-MAIN@BAMA.UA.EDU
 Subject: Newbie Questions!
 
 
 I'm currently in University on my Co-op term as a COBOL 
 programmer for host systems (zOS). I have a few basic 
 questions regarding the zArchitecture that I can't seem to 
 elicit answers to from my co-workers. The questions are as follows:
 
 1. zOS has a kernel called the BCP, or Base Control Program. 
 In Linux or Windows, it's established that the kernel runs on 
 a general purpose CPU( PowerPC, x86, MIPS, etc...); however, 
 I would like to know if such a central CPU exists in the 
 mainframe,  and if that central CPU is of some common 
 architecture like, POWER. If not, are there any documents 
 that I can look into that will describe the CPU architecture for me?

In the zSeries world, the bible for how the CPU operates is called
The Principles of Operations. You can read this on the web at:

http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR003/CCON
TENTS

Now, this does not describe 100% of all of the facilities embedded in
the zSeries. It mainly describe the __majority__ of the instructions
implemented on the zSeries and how some things such as timers and memory
access work.

There are secret facilities within the zSeries which are not
documented outside of IBM.

 
 2. ESCON and FICON are data busses used for external storage 
 devices, but what does the mainframe use for internal data 
 bus, InfiniBand, HyperTransport?

The zSeries uses its own internal data bus technology. I think they call
it the STI (Self Timed Interface?). But these internals are not as
widely documented as the ones that you mentioned. Basically, I think
that IBM doesn't care if you know how it works internally because: (1)
you can't make use of the knowledge anyway and (2) if it were
documented, somebody might try to make that knowledge part of their
software, leading to problems with that software in the future.

You might want to go to the web site:

http://researchweb.watson.ibm.com/journal/rd/

there are many articles here on IBM technologies, including the zSeries,
iSeries, and pSeries. Along with a boat load of more theoritical
papers. But you can stumble on facinating reading at times.

You might especially like:

http://researchweb.watson.ibm.com/journal/rd48-34.html (IBM eServer
zSeries)

http://researchweb.watson.ibm.com/journal/rd46-45.html (IBM eServer
z900)

http://researchweb.watson.ibm.com/journal/rd43-56.html (old S/390 Server
G3  G4)

http://researchweb.watson.ibm.com/journal/rd39-12.html (CMOS
techonology)



 
 3. Does the mainframe use common interconnects on the 
 hardware level? I'm thinking of PCIe, PCI-X, MCA, or PCI.

Generally, no. However, the current zSeries do have some PCI slots in
which some specialized cards can be inserted. I think one of the main
uses is for the cryptographic coprocessors. It is certainly not a
general interface where a end-user could insert their own PCI card.

 
 That's all for now, but I'm sure subsequent answers will 
 generate follow-up questions on my part. Thanks for taking 
 the time to read this!


--
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Senior Systems Programmer
HealthMarkets
Keeping the Promise of Affordable Coverage
Administrative Services Group
Information Technology

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Re: Newbie Questions!

2006-07-18 Thread Matthew Stitt
At least for question 1, go find a manual called the Principles of
Operations.  You can search the IBM website by that name and then download
it to read.

The BCP is nothing more than the core MVS components.  MVS is comprised of
many subsystems, each doing a specialized function.  The Kernel in your
terms is the MVS Nucleus, which controls the activity between the many
subsystems.

There are many CPu's on a Z-series.  Some have as few as one, some have as
many as 54.  The BCP runs on all of them at the same time.

For answers to questions 2 and 3, you might try searching the IBM Journal,
and the IBM Journal of Research and Developement.  Machine architectures
change every few years, so the answers depend on the type of machine you are
interested in.

On Tue, 18 Jul 2006 15:46:27 -0400, Kuredjian, Michael
[EMAIL PROTECTED] wrote:

I'm currently in University on my Co-op term as a COBOL programmer for host
systems (zOS). I have a few basic questions regarding the zArchitecture that
I can't seem to elicit answers to from my co-workers. The questions are as
follows:

1. zOS has a kernel called the BCP, or Base Control Program. In Linux or
Windows, it's established that the kernel runs on a general purpose CPU(
PowerPC, x86, MIPS, etc...); however, I would like to know if such a central
CPU exists in the mainframe,  and if that central CPU is of some common
architecture like, POWER. If not, are there any documents that I can look
into that will describe the CPU architecture for me?

2. ESCON and FICON are data busses used for external storage devices, but
what does the mainframe use for internal data bus, InfiniBand, HyperTransport?

3. Does the mainframe use common interconnects on the hardware level? I'm
thinking of PCIe, PCI-X, MCA, or PCI.

That's all for now, but I'm sure subsequent answers will generate follow-up
questions on my part. Thanks for taking the time to read this!

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Re: Newbie Questions!

2006-07-18 Thread john gilmore
There is an IBM redbook, which you can download (no charge) at the IBM 
publications website, called


Introduction to z/OS and the mainframe environment

Get it and read it.  You will then be able to reformulate your questions.

John Gilmore
Ashland, MA 01721-1817
USA






From: Kuredjian, Michael [EMAIL PROTECTED]
Reply-To: IBM Mainframe Discussion List IBM-MAIN@BAMA.UA.EDU
To: IBM-MAIN@BAMA.UA.EDU
Subject: Newbie Questions!
Date: Tue, 18 Jul 2006 15:46:27 -0400

I'm currently in University on my Co-op term as a COBOL programmer for host 
systems (zOS). I have a few basic questions regarding the zArchitecture 
that I can't seem to elicit answers to from my co-workers. The questions 
are as follows:


1. zOS has a kernel called the BCP, or Base Control Program. In Linux or 
Windows, it's established that the kernel runs on a general purpose CPU( 
PowerPC, x86, MIPS, etc...); however, I would like to know if such a 
central CPU exists in the mainframe,  and if that central CPU is of some 
common architecture like, POWER. If not, are there any documents that I can 
look into that will describe the CPU architecture for me?


2. ESCON and FICON are data busses used for external storage devices, but 
what does the mainframe use for internal data bus, InfiniBand, 
HyperTransport?


3. Does the mainframe use common interconnects on the hardware level? I'm 
thinking of PCIe, PCI-X, MCA, or PCI.


That's all for now, but I'm sure subsequent answers will generate follow-up 
questions on my part. Thanks for taking the time to read this!


--
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Search the archives at http://bama.ua.edu/archives/ibm-main.html


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Re: Newbie Questions!

2006-07-18 Thread Mark Zelden
Hi.  Welcome to the world of z and IBM-MAIN.  

Go to http://www.ibm.com/servers/eserver/zseries/zos/bkserv/
On the right side of the page there is a link to the z/OS basics
skill center and a z/OS Basics Redbook.  This Redbook may be a
good place to start along with the basics skill center. 

If you want to learn about systems programming at some point, there 
are also a set of Redbooks called The ABCs of System Programming or 
the ABCs of z/OS System Programming.

z/OS / zSeries / System z is vast... the follow up questions could 
go on for years!  :-)   Also learn to search the archives of
ibm-main to see if you question has been asked / answered 
before.

More details to your questions below... but you have to do the
downloading / reading yourself. :-)

On Tue, 18 Jul 2006 15:46:27 -0400, Kuredjian, Michael
[EMAIL PROTECTED] wrote:



1. zOS has a kernel called the BCP, or Base Control Program. In Linux or
Windows, it's established that the kernel runs on a general purpose CPU(
PowerPC, x86, MIPS, etc...); however, I would like to know if such a central
CPU exists in the mainframe,  and if that central CPU is of some common
architecture like, POWER. If not, are there any documents that I can look
into that will describe the CPU architecture for me?



Go to http://www.redbooks.ibm.com/ and search for IBM System z9 109
Technical Introduction.  This will tell you about the most current
technology. The prior technology was z990 (and z890) and before that
was z900 (and z800).  Prior to the z900 the hardware (and software)
was limited to a 31-bit architecture.  If you are interested in that
look for 9672. 

2. ESCON and FICON are data busses used for external storage devices, but
what does the mainframe use for internal data bus, InfiniBand, HyperTransport?


See #1.  I thought I heard something about InfiniBand being used 
internally, but that may still be in the next processor generation.

3. Does the mainframe use common interconnects on the hardware level? I'm
thinking of PCIe, PCI-X, MCA, or PCI.


Search the same Redbook site for the IBM System z Connectivity Handbook


Cheers,

Mark
--
Mark Zelden
Sr. Software and Systems Architect - z/OS Team Lead
Zurich North America / Farmers Insurance Group
mailto: [EMAIL PROTECTED]
z/OS and OS390 expert at http://searchDataCenter.com/ateExperts/
Mark's MVS Utilities: http://home.flash.net/~mzelden/mvsutil.html

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Re: Newbie Questions!

2006-07-18 Thread Charles Mills
Everything everyone has said so far is correct but IMHO all of the answers
to question 1. (which is really two questions, kernel and architecture) have
started at a level of detail beyond your question.

The z/OS hardware is its own architecture. It is not x86 or POWER or Sparc
or any popular architecture such as those. I guess the correct name at
this point for the processor hardware design is zSeries architecture but
you will often hear it informally called 390 architecture out of old habit
- System 390, System 370, and System 360 were earlier names for the system.

As others have pointed out, the processor is exhaustively, but not
completely, documented in Principles of Operation. The old name, System
360, was chosen to evoke an all points of the compass approach to the
hardware. It implements byte-, word- (multiple sizes of word), decimal-, and
floating point-oriented instructions, as well as many, many special-purpose
instructions. As others have said, IBM has recently placed tremendous
emphasis on multi-processor designs - the speed of the box is many times
greater than the speed of any one CPU.

The kernel and all programs run on these processors. Well, actually, the
channels - the external buss - implement instructions of their own, but
that's way beyond the scope of this e-mail.

The apparent processor architecture is - like most modern machines -
implemented largely in microcode running on a lower level processor. (Also
something called millicode, but let's not go there for now.) IBM has been
moving that lower level processor in the general direction of the POWER
chips, but they aren't there yet, so far as I know.

Someone will no doubt quibble with nearly everything I say above. Welcome to
IBM-MAIN.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On Behalf
Of Kuredjian, Michael
Sent: Tuesday, July 18, 2006 12:46 PM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Newbie Questions!


I'm currently in University on my Co-op term as a COBOL programmer for host
systems (zOS). I have a few basic questions regarding the zArchitecture that
I can't seem to elicit answers to from my co-workers. The questions are as
follows:

1. zOS has a kernel called the BCP, or Base Control Program. In Linux or
Windows, it's established that the kernel runs on a general purpose CPU(
PowerPC, x86, MIPS, etc...); however, I would like to know if such a central
CPU exists in the mainframe,  and if that central CPU is of some common
architecture like, POWER. If not, are there any documents that I can look
into that will describe the CPU architecture for me?

--
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send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO
Search the archives at http://bama.ua.edu/archives/ibm-main.html


Re: Newbie Questions!

2006-07-18 Thread Edward Jaffe

Charles Mills wrote:

... I guess the correct name at
this point for the processor hardware design is zSeries architecture


It's called z/Architecture, just like it says on the cover of the 
Principles of Operation manual.


--
Edward E Jaffe
Phoenix Software International, Inc
5200 W Century Blvd, Suite 800
Los Angeles, CA 90045
310-338-0400 x318
[EMAIL PROTECTED]
http://www.phoenixsoftware.com/

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Re: Newbie Questions!

2006-07-18 Thread Ted MacNEIL
It's called z/Architecture

I always called the manual z/Arch POP.
I picked that up from a Canadian IBM'r.

But, most didn't understand what that meant.
When in doubt.
PANIC!!

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Re: Newbie Questions!

2006-07-18 Thread SUBSCRIBE IBM-MAIN tdell
All of the threads here where right on target, and should serve you well if
you follow them as prescribed. I have found that there is no definitive
source on the architecture. It is really a vast  landscape , I actually
read the hardware manual supplied with the 3031 CPU's,, they had a lot of
instruction detail,, what a geek I was.

To recap..


Mainframes don't actually have a backplane that's governed by a bus
arbitrator scheme as some implementation have done  in the past.  That
channel subsystem as it was called, was strictly a place for the more
experienced coders so beware. It has it's own methodology when it came to
writing code.The channel subsystem is really a processor in it's own right.

 All throughout the architecture you'll find various processors that are
part of the machine architectural composition, but IBM does not disclose
their originsie. OS/2 was used as a  loader at one time. HMC's are now
INTEL based..etc..

To actually program at the assembler level is fairly easy, debugging is
where the nightmare starts. I/O on z/OS is straightforward, I/O  on VSE is
a little tricky. I/O on VM was a no brainier even though the manuals were
almost indecipherable at times. V/M did  provide the optimal learning
environment since you could at one time run both DOS/MVS like macros. You
interactively execute a program without much fear of harm, but you still
had have some minimal knowledge of what was actually being performed on
your behalf.


IMHO the best place to start is by tracking down some of the old 360/370
textbooks. Many (all)  are out of print.. But you can try OPAMP technical
books in Los Angeles.
Occasionally I'll see a book by  Ivan ( make that Dr Ivan) Flores, Harry
Katzan et al. These were good text books. There were some early books on
microprogramming that did some in depth examination of the instruction sets
from various Mainframe Manufacturers. You can try locating them, but this
might be a little too over the top also. I find that the ABC's books are
filled with good and useful information,  but even they can be a little too
over whelming at times.

My two bits to learning.

KISS, beg , borrow , steal  , share good code. Make sure you have a GREEN
card handy, THE POP is your friend, Macro instruction documentation  are
essential to getting past the bumps, and there will be many. If you ever
run across those old blue XA manuals on macro coding grab'em they're
golden, and you can still gleam a few tidbits from'em. Learn XDC or TSO
test. Be humble,, there always a darn good assembler programmer hanging
around who tell you a thing or two. I'm 25 years in and the guy sitting
next to me is 50 years in. I'm humbled

Good luck and  keep following the thread.

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Re: newbie questions!

2006-07-18 Thread john gilmore
'Humility'?  Anyone entering a new field has perforce much to learn from 
some of its experienced denizens, but humility should be short-lived.


No good programmer I have every known was at all humble, and the great ones 
were/are well aware of their abilities, even [some few of them] arrogant 
about their skills.


Nothing much is ever achieved without radicall intellectual curiosity, a 
need to know how things work, and high ambition.  The mules who transport 
visitors to and from the bottom of the Grand Canyon of the Colorado perform 
a valuable function, but it would be a mistake to consult even the most 
experienced of them about the archeology or geology of the Canyon.


John Gilmore
Ashland, MA 01721-1817
USA

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