Timothy Normand Miller wrote:
On 8/16/07, Mark <[EMAIL PROTECTED]> wrote:
Sorry if this has already been described somewhere, but i was wondering
how that is done as well. the IOBs mess up my timing analysis a lot.
I know with Xilinx's tools, you can use synthesis attributes in the HDL,
XST command-line options, or constraints in the UCF to prevent flops
from getting packed into IOBs. You can also apply constraints in the
UCF to ignore timing on certain paths (say, from pins to flops). It's
documented in the constraints guide (the IOB and TIG constraints, I
think) and the XST manual.
You want to avoid not just the IOBs, but also the routing delays to
get from the pins to your logic and back to the pins. Your approach
of adding flops on inputs and outputs is the right thing to do, but
sometimes, you end up having to add another layer.
IOBs, block RAMs, and multipliers are on the fringes, and whether
you're trying to avoid them (like in this case) or actually use them
for normal purposes, a common challenge is dealing with the fact that
your logic may be quite far away from the dedicated modules.
I'm pretty sure that all the FPGA vendors' timing analyses separate
delays into four categories: pin to pin, pin to flop, flop to flop, and
flop to pin. The fMax reported by TRCE only considers flop to flop
paths. Moreover, the entire toolchain only tries to optimize the timing
for flop to flop paths (with the possible exception of packing flops
into IOBs). Of course, user constraints can override that default
behaviour (one example is placing delay constraints on pin to flop
paths). If you disable packing flops into IOBs, the reported fMax
should be a realistic upper limit on the performance you can expect from
your circuit (to the best of my knowledge). As for lower bounds, the
sky (er, ground?) is the limit, particularly as the device utilization
climbs over 90-95%.
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