Timothy Normand Miller wrote:
On 8/15/07, Mark <[EMAIL PROTECTED]> wrote:
For an 8x8->16 multiplier, I get:
Synplify tries for 200MHz, achieves 110MHz
MAP reports 41 slices (1%)
PAR tries for 114MHz, achieves 98MHz
Cool. Now, the Xilinx tool will figure out if you've put extra layers
or registers after the multiplier and automatically pipeline it. What
do you get if you register the product and then add another register
delay?
It doesn't appear as though Synplify for Lattice will do so. I get the
same timing with 1, 2, or 3 stages of registers after the multiplier and
the number of registers in the map report goes up as expected.
Is it possible Xilinx doesn't automatically pipeline multipliers in
general, only hard multipliers? My guess is that they push those
registers during mapping, not during synthesis.
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