On 8/19/07, Mark <[EMAIL PROTECTED]> wrote: > > I'm pretty sure that all the FPGA vendors' timing analyses separate > delays into four categories: pin to pin, pin to flop, flop to flop, and > flop to pin. The fMax reported by TRCE only considers flop to flop > paths. Moreover, the entire toolchain only tries to optimize the timing > for flop to flop paths (with the possible exception of packing flops > into IOBs). Of course, user constraints can override that default > behaviour (one example is placing delay constraints on pin to flop > paths). If you disable packing flops into IOBs, the reported fMax > should be a realistic upper limit on the performance you can expect from > your circuit (to the best of my knowledge). As for lower bounds, the > sky (er, ground?) is the limit, particularly as the device utilization > climbs over 90-95%.
These tools have always been a weak point for me, so I'm sure you can get more out of them than I get. In practice, I design stuff, then hand it off to Howard who is much better with... well, pretty much every aspect of chip design. :) When doing these extra-layers-of-register-wrappers, I'm attempting to isolate the main circuit of interest and have the IOBs taken out of consideration, not just for direct affects on timing, but also to prevent having the circuit stretched out artificially across the chip just so that it can be hooked up to the pins that are around the edges. Of course, this can then turn out to be too optimistic, because when you combine with other logic, you start competing for resources. This sort of thing happened with the memory controller. I got it down to like 4.7ns when I synthesized it in isolation, but when Howard combined it with other logic, it came to like 5.5ns or worse. He made some futher changes and got it down to like 5.1ns. > It looks like > the source flop is packed into an IO (again, I don't yet know how to > address that on this toolchain). See what I said above. Add some extra layers of registers to prevent stretching. The IOB registers are more distanced from our logic than slice registers, and routing to the pins also adds extra delay. We should consider developing some general wrapper with some real logic in it. For instance, we could use the PCI controller and wire it up to any piece of logic we want to characterise with some register interface. More work, but our logic is then isolated from the IOBs in a more realistic way AND we have some realistic competition got slide and routing resources. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
