Hi Terry,

Bare board test is becoming an increasingly difficult and increasingly
important issue.  It was one thing to test boards when track and gap spacing
was 12 mils and your standard IC had pads spaced on 0.1 inch centers.  Today
the industry is building boards with BGA and other high density packages and
track widths and pad sizes are constantly shrinking.  When several of these
high density packages are placed in a confined area, the board can no longer
be tested on bed of nails testers (at least not on a single fixture).  The
test pin density just becomes too congested.  Flying probe testing and
combination testing (part of the netlist is tested on the bed of nails
tester and part on the flying probe tester) is often necessary.  Controlled
impedance boards are becoming more and more important.  Buried resistors,
while not yet commonplace are seen more often.  Blind and buried vias add to
the complexity.  Testing these complex boards, is not just a matter of
making sure that "everything that should be connected is" and "everything
that should not be connected is not".  It's now important to know that the
trace impedance falls within a particular range and that buried resistors
fall within tolerance.

Lavenir has spent many man years trying to perfect netlist extraction from
Gerber data.  I would like to say that we are pretty good at this, but quite
honestly, this is a very difficult task.  It is one thing, to extract a
netlist from "well behaved" Gerber data.  Unfortunately, many CAD programs
output Gerber data in many different flavors.  Not all of these are easy to
deal with.  Furthermore, this has been complicated by the introduction of
"polygon" data in the Gerber files.  Some programs generate their data by
outputting a series of bizarre overlapping polygons, that are themselves not
well defined (open vertices, complex shapes, etc.).  Some of the data we see
is unbelievable.  It can make extracting a decent, accurate netlist a
virtual nightmare.

In an ideal world, the PCB manufacturer would build my PCB and test it to my
Protel netlist.  After all, I'm familiar with my design, I know what I want,
I rely on the Protel netlist.  As a designer, I don't really care about
IPC-D-356.  I just want my board built so that it matches my design.  But,
most PCB manufacturers don't know what a Protel netlist is.  These
manufacturers receive files from numerous different CAD packages.  And even
within a given CAD package, specs change all the time.  PCB manufacturers
cannot keep up with all of the differing netlist formats from all of the
various CAD programs.  They deal in the Gerber world.  Despite its many
problems, Gerber is the common language that this industry revolves around.
And, your board will be built based upon the Gerber data that you supply.

I think every PCB manufacturer would love to deliver netlist tested boards,
that match their customer's design netlist.  However, it is my experience
that very few manufacturers are able to guarantee this on a routine basis.
Several years ago, Lavenir was asked to write a Netlist Compare function.
Initially, we thought that this would allow the PCB manufacturer to compare
a CAD generated netlist to a netlist extracted from the Gerber data.
However, this was not at all why the manufacturer wanted the compare
function.  Instead, the manufacturer would first extract a netlist from the
Gerber data.  This became the reference netlist.  Then, the manufacturer
would do all of the editing necessary to actually build your board.  I think
most designers would have kittens if they realized how much PCB
manufacturers need to modify the Gerber data in order to make a buildable
board.  Once all of the editing was complete, the fabricator would once
again extract a netlist from the revised Gerber data.  This netlist was then
"compared" to the netlist originally extracted.  This feature was used
primarily to insure that the PCB manufacturer did not introduce any errors
during their manipulation of the customer data.  It had nothing to do with
insuring that the board matched the customer design netlist !

I believe that in an ideal world, CAD tool providers would be cooperating
with PCB manufacturers to insure that boards were being built to the
designers specs.  Anything that the CAD vendor can do to enhance this
process will be better for all of us.  An unified netlist specification,
that deals specifically with the requirements faced by the PCB manufacturer,
should be well understood by the providers of our CAD tools.  The IPC-D-356A
specification is what we have for now.  Most of the bare board testers can
accept this netlist format.  It is what is being used to test your boards.
The IPC is hard at work on generating a revision to this specification.  I
applaud the efforts that Protel is making to provide an integrated tool that
addresses not only design issues, but also manufacturing issues.  It is not
a small task.

 Best regards,


Max P. Henzi, CEO
Lavenir Technology
2440 Estand Way
Pleasant Hill, CA 94523
voice: (925) 680-7400  fax: (925) 686-5131 
email: [EMAIL PROTECTED]
Web: www.lavenir.com 

 -----Original Message-----
From:   Terry Harris [mailto:[EMAIL PROTECTED]] 
Sent:   Tuesday, May 01, 2001 3:04 PM
To:     Protel EDA Forum
Subject:        Re: [PEDA] Export an IPC-D-356 format Netlist for PWB
MFGcircuittesting

On Tue, 01 May 2001 13:38:09 -0700, Abdulrahman Lomax wrote:

>IPC-D-356 includes pad location information, which then allows correlation 
>with the gerber data. If a pad is located on the top side at X,Y, then any 
>copper at that location is supposedly part of the net associated with that
pad.

I searched the web a bit more of D-356.   D-356 is very basic, enough
information to make a bed of nails if the generator bothered to correctly
identify 'mid' pads. 

D-356A is a major extension which can contain all kinds of information
including a representation of copper on the PCB, planes, specific test
information, adjacency information (to avoid redundant open circuit tests)
and other stuff I can't remeber. 

I still don't see supplying a D-356 netlist to a PCB house for them to test
the boards against is a good idea. Supplying a D-356 netlist (in either
direction) for cross checking a test netlist derived from gerbers is a good
idea. 

Haven't I seen a guy from Lavinir post here? They produce gerber scanning
software that creates D-356 netlists, maybe he has something to add on the
subject. 


Cheers, Terry.



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