At 06:43 AM 1/25/2002 -0600, Bryn Wolfe wrote: >Actually, though, Hot Air Leveling should not cause the burst unless there is >soldermask on both the top and bottom, or if it is a blind via. However, I >can't >think of a way in Protel to tell it to tent only the component side. You'd >probably >have to do some editing in the gerber file.
Well, it's easier than that. But still a nuisance. >This sounds like a feature that should be added to Protel, that is, >selecting which >side of the board tenting of through-hole vias occurs on: top, bottom, or >both. The feature is there, but it doesn't work. A solder mask expansion design Rule with top layer and via scope would, one would think, apply only to top layer masks. But the rule is not working that way, it seems. I think that vias are considered to live on Multilayer, which causes problems in many ways (such as with blind and buried vias, which are displayed only if Multilayer is on, regardless of the actual layers they affect -- but in this case the gerber routines do appear to correctly identify the layers for plotting). I'm hoping that how vias are handled is fixed in Phoenix; it is one of the current serious shortcomings. In this case, there are two ways I know to selectively tent vias (top vs. bottom). One has been mentioned: make the top plot with vias tented and the bottom with them free of mask. This, however, is a manual operation, easily overlooked next rev.... Another would be to select all the vias, copy them to the clipboard, and unselect All. Then paste the vias using the same reference location. There are now two vias in each location, one of them selected. Convert the selected vias to free pads, leaving them selected so that you can now globally edit them to the layer where you want solder mask to appear. You can also give them a distinctive padname, such as "topvia," if you put them on the top layer. This layer is the layer which will have solder mask openings. Tent all vias. You may, if you wish, set very tight, even slightly negative solder mask openings for Free-topvia. Be sure, in the global edit, to eliminate the hole, the holesize should be zero. The down side of this method is that editing will be a slight nuisance, since the topvia pads. But before doing the next rev, you could delete all Free-topvia pads. At least you will have been reminded.... Note that there seems to be, similarly, no simple way to directly control solder mask expansion on *pads* according to top or bottom. The problem is not just with vias. Actually, when you look at the solder mask expansion rule dialog, it is fairly obvious that it has not received proper programming attention: all copper layers are shown, not just top and bottom.... Note to Protel programmers: we don't put solder mask on inner layers! Ditto paste mask... :-) I wouldn't really complain if the rule scope dialogs allowed more flexibility than could actually be used; but there are other desired scope possibilities that are missing. The whole system needs more attention, again, we have hopes for Phoenix.... [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
