[coreboot] Rebasing a 2009 branch on current master (VX900 anyone?)

Hi, I am that guy that never seems to get VX900 working properly. I've recently received some code[1] for the VX900 from VIA. It is based on a coreboot fork from about 2009. Rather than try to continue my own VX900 effort, I think it is better to use the code provided by VIA, and clean that one u

Re: [coreboot] Rebasing a 2009 branch on current master (VX900 anyone?)

On 05/30/2013 01:45 PM, Cristian Măgherușan-Stanciu wrote: > Wow, I can't believe I was so close to the commit before the fork ;-D​ > > I also think this is a good strategy, please keep us posted on any progress. > Peter and Cristi, thank a bunch for your help. Your suggestions helped me a lot i

[coreboot] Hijacking (was Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1) )

On 05/20/2013 10:16 AM, Marius Schäfer wrote: > Hello, > > I just want to play around with coreboot on my old VIA EPIA-M, as it > should be supportet and a good place to start. I just followed the Build > HOWTO. But I always end up with 'lzma: Decoding error = 1'. > I clonded coreboot from git, in

Re: [coreboot] Best Supported Laptop

On 06/03/2013 03:10 PM, Oliver Schinagl wrote: > On 06/03/13 16:03, Denis 'GNUtoo' Carikli wrote: >> Hi, >> >> On Sun, 2 Jun 2013 20:54:04 -0500 >> slhac tivist wrote: >> >>> >Which supported laptop is the most free? >> The Lenovo X60. > Strange that an Intel Part has the best support. > I find

Re: [coreboot] Best Supported Laptop

On 06/04/2013 12:36 AM, David Hendricks wrote: > On Mon, Jun 3, 2013 at 1:57 PM, Alex G. wrote: >> >> On 06/03/2013 03:10 PM, Oliver Schinagl wrote: >>> On 06/03/13 16:03, Denis 'GNUtoo' Carikli wrote: >>>> Hi, >>>> >&

Re: [coreboot] CoreBoot compatible

On 12/20/2010 11:15 PM, stanley wrote: Will coreboot work on my machine? I have some good news and some not so good news. Good news first: The north/southbridges you have are supported. The SuperIO is supported. There is a very similar supported motherboard, the GA-MA785GMT-UD2H, whic

[coreboot] Porting to ASUS K8V-X SE, found possible infinite loop in pnp_get_ioresource() (pnp_device.c)

IOS to load (but not boot yet). It might be that I'm doing something terribly wrong earlier on; therefore, if you need to look at the K8T800 or motherboard code, I can create a patch against the last svn commit (I'm curently developing over r6247). Alex G. -BEGIN PGP SIGNATURE---

Re: [coreboot] Does coreboot+seabios suppport loading linux LiveCD?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 It should work. I'm porting the K8V-X SE, and it will boot off CDs, and get to the point where the kernel puts some debug messages. And this with some of the configuration still faulty. The fact that your boot stops may indicate a bug in coreboot, but

[coreboot] [PATCH] Fix infinite loop in pnp_get_ioresource()

Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if a rare condition arises. Signed-off-by: Alexandru Gagniuc --- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Fix infinite loop in pnp_get_ioresource()

Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if a rare condition arises. Signed-off-by: Alexandru Gagniuc --- Index: src/devices/pnp_device.c === --- src/devices/pnp_device.c (revision 6315) +++ src/devices/p

[coreboot] [PATCH] Add PCI ID's for VIA K8T800 and K8M800 chipsets

Added PCI ID's for the functions of the VIA K8T800(Pro) and K8M800 chipsets. Signed-off-by: Alexandru Gagniuc --- Although this is very trivial, I don't think I'm in the position to ack. Alex Index: pci_ids.h === --- pci_ids.h (re

Re: [coreboot] [PATCH] Fix infinite loop in pnp_get_ioresource()

d. See patch. > Can you test, please? It should tell you which device / index is > causing the problem. > > Stefan > > On Fri, Jan 28, 2011 at 2:14 AM, Alex G. wrote: >> Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if >> a rare con

Re: [coreboot] [PATCH] Add PCI ID's for VIA K8T800 and K8M800 chipsets

> > Hm.. Is there a chance to name them other than _1 ... _7? It's not > really more readable than just using the numbers directly.. > Yes, for those which I have the information about. See attached patch. Alex Signed-off-by: Alexandru Gagniuc Index: src/include/device/pci_ids.h =

Re: [coreboot] [PATCH] Fix infinite loop in pnp_get_ioresource()

> > Unfortunately the patch was lost. Please send it, want to fix all > bugs like this! :) > You're a bit late :) . I resent the patch last night, and Stefan wrote a better one based on it. Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] A couple of lost [PATCH]es

Hi, There were a couple of patches flying around the last days, (which, I have to admit, are of specific interest to me), which seem to have died-off. I've never seen such an (IPDS) Instant Patch Death Syndrome in other projects I contributed to, so perhaps my email was not being delivered. See p

[coreboot] [PATCH] Add support for VIA K8T800 northbridge

See patch for details. I have an ASUS K8V-X SE with the named NB, and this patch is sufficient to get the HT link working properly, and to get a working V-Link with the southbridge. The modifications in the vt8237r directory allow the respective SB to find the K8T800 and K8M800 NBs. I will need s

Re: [coreboot] [PATCH] add PC87382 to superiotool

On 02/01/2011 12:58 PM, Sven Schnelle wrote: > Hi List, > > this patch adds the NSC PC87382 to superiotool. It is a rather small > 'superio' device, containing one Serial Port, one Infrared Port, GPIO > and a Docking LPC switch. It is used in various Thinkpads. > > It adds 0x164e/0x16ef to the list

Re: [coreboot] errata#89 patch for Family 0Fh Prozessors

Erratum 89 is already handled on line 390: if (!is_cpu_pre_b3()) { /* Erratum 89 ... */ msr = rdmsr(NB_CFG_MSR); msr.lo |= 1 << 3; If this is also needed when CONFIG_K8_REV_F_SUPPORT == 1, then we should move the existing one out of the #if CONFIG_K8_REV_F_SUPPORT == 0 so it gets exe

[coreboot] [PATCH] Add license headers for AMD family Fh

See patch. Alex Add GPL license headers to all files in src/cpu/amd/model_fxx (except microcode). Signed-off-by Alexandru Gagniuc Acked-by Alexandru Gagniuc Trivial Index: src/cpu/amd/model_fxx/Kconfig === --- src/cpu/amd/model_fx

Re: [coreboot] [PATCH] Add license headers for AMD family Fh

> Not trivial at all, but legally kind of troublesome. Got to NACK this, > sorry. > No problem > coreboot is GPLv2, not GPLv2+ > http://www.coreboot.org/Development_Guidelines says GPLv2+. So which is the correct license? Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreb

Re: [coreboot] [PATCH] Add license headers for AMD family Fh

On 02/02/2011 09:50 PM, Patrick Georgi wrote: > Am 02.02.2011 20:39, schrieb Alex G.: >>> coreboot is GPLv2, not GPLv2+ >> http://www.coreboot.org/Development_Guidelines says GPLv2+. >> So which is the correct license? > We have some GPLv2 and some GPLv2+ files, so the c

Re: [coreboot] errata#89 patch for Family 0Fh Prozessors

That looks way better. :) Acked-by: Alexandru Gagniuc On 02/02/2011 10:17 PM, Josef Kellermann wrote: > Am 02.02.2011 20:11, schrieb Alex G.: >> Erratum 89 is already handled on line 390: >> >> if (!is_cpu_pre_b3()) { >> >> /* Erratum 89 ... */ >>

Re: [coreboot] errata#89 patch for Family 0Fh Prozessors

src/northbridge/amd/amdk8/coherent_ht_car.c was renamed to someting else since then (I wasn't around then), and the patch can no longer be applied. Can you please check this? Alex On 02/02/2011 11:20 PM, Rudolf Marek wrote: > While we are at it. I'm attaching some very old patch (r2978 ;) > whic

Re: [coreboot] errata#89 patch for Family 0Fh Prozessors

On 02/03/2011 10:17 AM, Josef Kellermann wrote: >> e are at it. I'm attaching some very old patch (r2978 ;) >> which contains some errata fixes too, if you have some spare time >> please try to check if it is correct. >> >> Signed-off-by: Rudolf Marek >> >> >> Thanks, >> Rudolf >> > Hi, > are you

Re: [coreboot] errata#89 patch for Family 0Fh Prozessors

> Hi, > sorry for the misunderstanding. > Setting bit 32 in msr should be -> 'msr.hi |= (1<< 0)', no? LOL! Nice catch. This is what happens when you're still up at 6AM, obsessive drawing lines on a Google Earth printscreen in order to finish a project due in a few hours. :P It's funny to see th

[coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver

(See Patch) This fixes the "ERROR: device PNP: 002e.207 index 98 has no mask." that I have been getting on the W83627EHG. Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver

Sorry about forgetting to attach the patch. Alex On 02/05/2011 09:50 PM, Alex G. wrote: > (See Patch) > > This fixes the > "ERROR: device PNP: 002e.207 index 98 has no mask." > that I have been getting on the W83627EHG. > > Alex > > Fixes a problem wit

Re: [coreboot] [PATCH] errata#89 patch for Family 0Fh Prozessors

Can someone with commit access please commit this patch, or NACK it? Alex On 02/02/2011 11:55 PM, Alex G. wrote: > That looks way better. :) > > Acked-by: Alexandru Gagniuc > > On 02/02/2011 10:17 PM, Josef Kellermann wrote: >> Am 02.02.2011 20:11, schrieb Alex G.: >

Re: [coreboot] [PATCH] Fix issue with Winbond W83627EHG MIDI driver

>> Index: src/superio/winbond/w83627ehg/superio.c >> === >> --- src/superio/winbond/w83627ehg/superio.c (revision 6323) >> +++ src/superio/winbond/w83627ehg/superio.c (working copy) >> @@ -189,7 +189,7 @@ >> { &ops, W83627EHG_HW

Re: [coreboot] Help with RX serial interrupts?

Are you sure it's not just a bad PIC/APIC config? Alex On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote: > Designation: Non-SSA/Finmeccanica > > Hi all. > > I would like to apologise for being a lurker on this list and only > popping up when I need help. But I need help……….. > > I’ve run into

[coreboot] [PATCH] Fix some errata for AMD Family F processors

See patch for detailed description. Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Fix some errata for AMD Family F processors

On 02/08/2011 11:37 PM, Alex G. wrote: > See patch for detailed description. > > Alex I should really attach the patch first before writing anything. Sorry about that. Here's the patch. Alex Implemented workaround fot erratum 169, obsoleting errattum 131. Workaround for 131 re

Re: [coreboot] Help with RX serial interrupts?

; > -Original Message- > From: coreboot-bounces+svotier=drs-ds@coreboot.org > [mailto:coreboot-bounces+svotier=drs-ds@coreboot.org] On Behalf Of > Alex G. > Sent: Tuesday, February 08, 2011 4:15 PM > To: coreboot@coreboot.org > Subject: Re: [coreboot] Help wi

[coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support

Find attached a new version of my previous patch for the K8T800. In my previous patch, I was worried that the .tblpointer could contain incorrect values. I have hexdumped the image for the A8V-E SE (K8T8900 chipset), and it contains the correct values. The same applies to the board I'm porting (wit

Re: [coreboot] question: Is it possible for OS to initialize the memory

AFAIK, the controller needs to initialise all channels at once. Worse yet, if you only have two slots, chances are those are on the same channel, so commands intended for the first dimm will unavoidably reach the second dimm. You would need to stop the MC for this to happen. You lose all the tables

Re: [coreboot] amd/rs690/gfx.c cleanup

On 02/14/2011 06:07 PM, Josef Kellermann wrote: > removed /* LPC DMA Deadlock workaround? */ ... > > setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in > amdk8/coherent.c > > see patch for details. > > Signed-off-by: Josef Kellermann > WOW! Nice

Re: [coreboot] patch for errata#169

On 02/14/2011 05:17 PM, Josef Kellermann wrote: > this patch should be applied to k8_f0 (NODE_HT(x)), not k8_f3 (NODE_MC(x)). > see patch for details. > > Signed-off-by: Josef Kellermann > You are correct. This is what happens when writing patches at 2AM. I'm glad you c

Re: [coreboot] Free (possibly recoverable?) Gigabyte GA-MA785GMT-UD2H

> I've been speaking with mrnuke on the IRC channel and he mentioned two > things: 1) There might be some clever strategy to recover the board, and Can you post some high resolution, clear, pictures of the exposed area? You described some sparks, which means there's a high chance any damaged compo

Re: [coreboot] build service results for r6367

This patch should add the missing file. Signed-off-by: Alexandru Gagniuc --- On 02/16/2011 04:21 PM, repository service wrote: > Dear coreboot readers! > > This is the automatic build system of coreboot. > > The developer "stuge" checked in revision 6367 to > the coreboot repository. This caus

Re: [coreboot] build service results for r6367

Fix build errors from r6367. Signed-off-by: Alexandru Gagniuc --- Belay my last patch. This patch fixes both types of errors that happen in r6367. Sorry about this. Alex On 02/16/2011 04:33 PM, Alex G. wrote: > This patch should add the missing file. > > Signed-off-by: Alexandr

Re: [coreboot] Seeing the output messages

On 02/16/2011 08:09 PM, Joseph Smith wrote: > On 02/16/2011 05:15 AM, ali hagigat wrote: >> Joe, >> I wonder if you can answer my questions if you really know about them. >> I do not have any mother board with Coreboot support now. I am >> reviewing the code statically. >> Regards >> >> >> On Wed,

Re: [coreboot] support request - SOYO 7VBA133

On 02/18/2011 08:51 PM, José Neto wrote: > Oh sorry... > But i have no idea for where start. > Unfortunately, wanting is not being able to. > Thanks anyway! > Start with Peter Stuge's "Bringing coreboot to a system near you" video. Alex -- coreboot mailing list: coreboot@coreboot.org http://www

[coreboot] [PATCH] Correct wrong PCI ID vor VIA K8M890 Chrome

before anyone bricks a board Alex. With the K8T800/M800 patch, the PCI IDs for the VIA chrome were moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly. (3220 instead of 3230). This patch defines the corect PCI ID for this device. Signed-off-by: Alexandru Gagniuc Acked-by: Ale

Re: [coreboot] Help for motherboard

On 02/19/2011 01:39 PM, sh4...@gmail.com wrote: > But I did not found here new Intel and AMD cpu for motherboards in > Desktop/Workstation section (except Laptop) > mentioned for e.g. > Intel Core 7i > Intel Core 3i Won't happen because Intel won't tell us how to initialize that hardware. So

Re: [coreboot] Help for motherboard

On 02/19/2011 06:58 PM, sh4...@gmail.com wrote: > > I wanted general purpose regular desktop for programming, internet, > GNU/Linux with common servers dovecote, tomcat, apache etc > Probably a socket AM2+ board will be best for you if you want to run coreboot. The Gigabyte GA-MA785GMT-UD2H is t

Re: [coreboot] HP Proliant dl145 g3 Can't read Boot disk

On 02/21/2011 03:53 PM, Kevin O'Connor wrote: > On Sat, Feb 19, 2011 at 06:26:30PM -0500, jarray52 jarray52 wrote: >> Hi, >> >> My HP Proliant dl145 g3 with Coreboot Bios and SeaBIOS payload cannot read >> my hard disk. Here is the serial console output. >> >> http://coreboot.pastebin.com/HYee3u0t

Re: [coreboot] coreboot on amd g34 platforms

On 02/21/2011 07:07 PM, Alexandr Frolov wrote: > Hello all, > > Is there any activities to support coreboot for AMD G34 motherboards? > Not that I know of, but the chipset should be theoretically supported. You'd have to check the source tree and the datasheet to see if the PCI IDs match. I know

Re: [coreboot] HP Proliant dl145 g3 Can't read Boot disk

On 02/21/2011 09:01 PM, Kevin O'Connor wrote: > On Mon, Feb 21, 2011 at 06:16:55PM +0200, Alex G. wrote: >> On 02/21/2011 03:53 PM, Kevin O'Connor wrote: >>> The log shows SeaBIOS found an ATA controller, but did not find any >>> drives attached to the controll

Re: [coreboot] HP Proliant dl145 g3 Can't read Boot disk

On 02/22/2011 01:45 AM, Kevin O'Connor wrote: > Thanks. The lspci shows: > > 01:0e.0 RAID bus controller: Broadcom BCM5785 [HT1000] SATA (Native SATA > Mode) (prog-if 05) > > So, the device doesn't use a standard class code. Does anyone know if > it accepts standard ATA or AHCI commands? If s

Re: [coreboot] [PATCH] disabling microcode update

On 02/22/2011 02:47 AM, Peter Stuge wrote: > Xavi Drudis Ferran wrote: >> Does everyone prefer to have it not include update_microcode.c and >> change romstage.c in those boards that call update_microcode(...) ? > > At least I like this better. It makes it clear what effect this > option has for m

Re: [coreboot] 870 attempt

On 02/24/2011 04:14 AM, Jonathan A. Kollasch wrote: > Hi, > > I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 > board. Raminit seems to go okay, as does the first bits of ramstage. > However, ramstage fails after the first two passes through > rs780_enable(). It stalls in get

Re: [coreboot] [PATCH] disabling microcode update

On 02/23/2011 03:51 PM, Xavi Drudis Ferran wrote: > > Pompous ? > Yes. This is an option for experienced users, and people too smart for they own sake (pozitive connotation), that value their freedom more than practicality. They will go to an extra effort to ensure that. Therefore, considering the

Re: [coreboot] [PATCH] disabling microcode update

On 02/24/2011 12:26 PM, Peter Stuge wrote: > Alex G. wrote: >> Is the 'adding a line in Kconfig' option hassle free enough for you? >> I just don't see a way to make it obscure enough it menuconfig, but I >> won't object if you do find one. > > D

Re: [coreboot] [PATCH] [and discussion] Add target for ASUS K8V-X SE motherboard

Ping! Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] outb(* 0x80) to post_code()

Applies to fresh svn...[OK] abuild run..[OK] See patch. Alex Index: src/southbridge/via/vt8231/early_smbus.c === --- src/southbridge/via/vt8231/early_smbus.c (revision 6380) +++

Re: [coreboot] [PATCH] outb(* 0x80) to post_code()

Remove all occurences of outb(*, 0x80), and replace them with post_code(). Create post_codes.h to store a central place for post codes. Replace common post_codes with macros defined in post_codes.h. Signed-off-by: Alexandru Gagniuc --- Oops, forgot to include that. -- coreboot mailing list: co

Re: [coreboot] [PATCH] outb(* 0x80) to post_code()

Find attached the version with the colloquial verbiage abridged. Alex Remove all occurences of outb(*, 0x80), and replace them with post_code(). Create post_codes.h to store a central place for post codes. Replace common post_codes with macros defined in post_codes.h. Signed-off-by: Alexandru Gag

Re: [coreboot] [PATCH] outb(* 0x80) to post_code()

Hi Stefan and Patrick. I Just saw your emails. inb(0x80) or post_code(POST_SMBUS_DELAY): make up your minds :) Extra #include post_codes: *mrnuke starts chopping > Can we put this in one file together with > src/include/cpu/amd/geode_post_code.h Looks interesting. Looking into that. Using th

Re: [coreboot] [PATCH] outb(* 0x80) to post_code()

Signed-off-by Alexandru Gagniuc --- On 02/26/2011 02:58 AM, Stefan Reinauer wrote: >>> Can we put this in one file together with [...] >>> src/include/cpu/x86/post_code.h >> >> No. This would ruin the behavior of post_code() in console.c, which also >> outputs to console if the option is selecte

Re: [coreboot] [PATCH] disabling microcode update

On 02/26/2011 03:39 AM, xdrudis wrote: > This patch tries to fix compilation when you select EXPERT in make menuconfig. > HT Frequencies are multiples of 200MHz AFAIK, so there are no 300MHz and 500MHz. I'm not sure why the build breaks, and why this fixes it, but I don't think this is the right s

Re: [coreboot] [PATCH] disabling microcode update

On 02/26/2011 03:38 AM, xdrudis wrote: > This is the patch for option B. > > You may not be able to test it without my next patch. At least for me > selectiong EXPERT in make menuconfig breaks the build. Next patch fixes it. > > I don't like the wording for the help option. It creates the impr

[coreboot] [PATCH] Proposal for dealing with superio *.c includes

Hi guys! I present a proposal for dealing with the annoying: #include "superio/vendor/model/early_serial.c" present in virtually all romstage.c files. The steps are as follows: 1) Declare a generic prototype: superio_enable_early_serial(); 2) Remove #include */early_serial.c from romstage 3) add

Re: [coreboot] Intel's BIOS Implementation Test Suite

On 02/26/2011 06:23 PM, Scott Duplichan wrote: code is included, as far as I can tell. > > AMD recently contributed full processor and chipset reference code to the > coreboot project, along with two working coreboot ports to demonstrate > its use. > You cannot really compare AMD to Intel, the sa

Re: [coreboot] Intel's BIOS Implementation Test Suite

On 02/26/2011 08:24 PM, Joseph Smith wrote: > On 02/26/2011 11:27 AM, Alex G. wrote: >> On 02/26/2011 06:23 PM, Scott Duplichan wrote: >> code is included, as far as I can tell. >>> >>> AMD recently contributed full processor and chipset reference code to >>

Re: [coreboot] [PATCH] disabling microcode update

On 02/26/2011 10:19 PM, xdrudis wrote: > On Sat, Feb 26, 2011 at 04:01:56AM +0200, Alex G. wrote: >> On 02/26/2011 03:38 AM, xdrudis wrote: >>> This is the patch for option B. >>> >>> You may not be able to test it without my next patch. At least for me >

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

On 02/26/2011 10:50 PM, Patrick Georgi wrote: > Am Samstag, 26. Februar 2011, 14:17:37 schrieb Alex G.: >> 3) add a romstage-$(CONFIG_THIS_SUPERIO) += early_serial.c to the >> superio's Makefile.inc > This will fail for romcc boards, as for them, romstage must be compil

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

On 02/26/2011 11:16 PM, Peter Stuge wrote: > Alex G. wrote: >> Moves the inclusion of the superio early code from romstage.c in >> the mainboard directory to Makefile.inc in the superio directory. > > Will it work also for boards with more than one superio? > I'm v

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

On 02/26/2011 11:43 PM, Patrick Georgi wrote: > Am Samstag, 26. Februar 2011, 23:27:47 schrieb Alex G.: >> Why bother holding dear to romcc when the obvious solution is to move >> those boards to CAR? We introduce more unneeded complexity, and make it >> at least just as ha

Re: [coreboot] [PATCH] disabling microcode update

On 02/27/2011 12:46 AM, xdrudis wrote: > On Sat, Feb 26, 2011 at 11:22:17PM +0200, Alex G. wrote: > >> I look at the microcode as simply DIP switches used to configure the IRQ >> line on the hardware. If the manual (microcode updates) gives me >> erroneous information,

Re: [coreboot] [PATCH] disabling microcode update

On 02/27/2011 01:30 AM, Peter Stuge wrote: > xdrudis wrote: >> This is the patch for option B. > > Thanks! > > >> Make patching cpu microcode optional (for experts). >> >> Signed-off-by: Xavi Drudis Ferran > > Acked-by: Peter Stuge > > Committed as r6385 with some whitespace changes and rew

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

Signed-off-by: Alexandru Gagniuc --- > C: > Or, besides SUPERIO_VENDOR_NAME we can also have a Kconfig option > SUPERIO_VENDOR_NAME_HAS_EARLY_SERIAL, and base our decision of including > the early serial code in romstage based on the latter. > I don't like options A, B, and D, so I created a patc

[coreboot] [PROPOSAL] Obsoleting support for non-CAR boards

We've all been thinking about it, though never said it much. It's obvious that non-CAR boards have become a drag recently: we have to find workarounds the romstage linking system in order to move forward with some ideas. Let's take for example removing .c includes from the source tree. We have an

Re: [coreboot] Via Epia-LN is in "supported list" ...but not in menuconfig

On 02/25/2011 05:12 PM, mutt wrote: > Hi, > > i would build coreboot for my motherboard VIA EPIA LN, listed in the > supported board (http://www.coreboot.org/Supported_Motherboards) with > a dedicated page: http://www.coreboot.org/VIA_EPIA-LN > > I'm following the HOWTO, always in wiki, but in m

Re: [coreboot] CBSTOOL

On 02/28/2011 03:57 PM, Peter Stuge wrote: > ali hagigat wrote: >> I wonder if anybody can explain the function of CBFSTOOL commands: >> create, add-stage and locate in details, examples are below: > > Did you even try searching for cbfstool in the source tree or on the > web page? > Ali, let me

Re: [coreboot] Microcode CPU writeup

On 02/28/2011 04:14 PM, Xavi Drudis Ferran wrote: > On Mon 28/02/11 08:16 , Rudolf Marek wrote: > >> Hi all, >> >> Would someone be interrested if I write something about microcoded CPUs >> controllers? Like the classic uCode ROM + ALU + Regs + IO unit? >> >> Thanks, >> Rudolf >> > > I'd read i

Re: [coreboot] [PATCH] add functions to set Subsystem Vendor/Device to rl5c746

On 02/28/2011 06:28 PM, Peter Stuge wrote: > Sven Schnelle wrote: >> this patch adds functions to set the Subsystem Vendor/Device ID fields >> on Ricoh RL5C746. > > Is the procedure device specific? > It seems so. The procedure is different on VIA hardware. Alex -- coreboot mailing list: coreb

Re: [coreboot] [RFC] Converting W83977TF early serial from included to linked

On 02/28/2011 08:00 PM, Keith Hui wrote: > given earlier buzz suggesting we leave non-CAR boards behind? > There was no buzz. Just an idea I sent to the list that no one seemed interested in :(. To try to answer your question, switching early_serial from included to linked is exactly what I tried

Re: [coreboot] [PATCH][RFC] First step in converting W83977TF early serial from included to linked

On 03/01/2011 07:20 AM, Keith Hui wrote: > And here is the patch. abuild-tested. I will boot test it with P2B-LS > and P3B-F tomorrow but I want this patch out there to generate some > discussions and get more boot test coverage. > OK. > This I believe falls under "infrastructure projects" [1]. >

Re: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support

On 03/01/2011 11:14 PM, Stefan Reinauer wrote: > * Peter Stuge [110216 14:43]: >> Alex G. wrote: >>> Extended K8T890 driver to include the K8T800 and K8M800 northbridges. >>> The K8T800 is almost identical to the K8T800Pro, also added to this >>> patch. The K8T

Re: [coreboot] [PATCH] outb(* 0x80) to post_code()

On 03/01/2011 11:09 PM, Stefan Reinauer wrote: > * Alex G. [110226 02:35]: >> Index: src/include/console/post_codes.h >> === >> --- src/include/console/post_codes.h (revision 0) >> +++ src/include/conso

Re: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support

On 03/02/2011 02:08 AM, Stefan Reinauer wrote: > * Carl-Daniel Hailfinger [110302 01:05]: >> Auf 02.03.2011 00:40, Joseph Smith schrieb: >>> On 03/01/2011 04:14 PM, Stefan Reinauer wrote: >>>> * Peter Stuge [110216 14:43]: >>>>> Alex G. wrote: >&g

Re: [coreboot] [PATCH] outb(* 0x80) to post_code()

On 03/02/2011 10:55 AM, Alex G. wrote: > On 03/01/2011 11:09 PM, Stefan Reinauer wrote: >> Due to the GPLv2 only nature of many source code files, we can not allow >> GPLv3 or even GPLv3 or later code to be committed to the repository. >> Please make this GPLv2 if possible.

Re: [coreboot] [PATCH] outb(* 0x80) to post_code()

Signed-off-by: Alexandru Gagniuc --- Index: src/southbridge/via/vt8231/early_serial.c === --- src/southbridge/via/vt8231/early_serial.c (revision 6380) +++ src/southbridge/via/vt8231/early_serial.c (working copy) @@ -1,3 +1,4 @@ +#inc

Re: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard

On 02/24/2011 04:12 PM, Alex G. wrote: > Ping! > Ping6 ? Alex Add support for ASUS K8X-X SE motherboard. The good: SeaBIOS can start, run option roms, and boot off DVD, IDE, or CBFS. IRQ tables are fairly refined. MP-Table is complete and reflects actual hardware setup. The bad: ACPI

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

Option C with GPLv2+ licensing. Alex Signed-off-by: Alexandru Gagniuc Index: src/include/superio/early_serial.h === --- src/include/superio/early_serial.h (revision 0) +++ src/include/superio/early_serial.h (revision 0) @@ -0,0 +1,3

Re: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard

On 03/02/2011 11:41 PM, Joseph Smith wrote: > On 03/02/2011 04:38 PM, Peter Stuge wrote: >> Alex G. wrote: >>> Add support for ASUS K8X-X SE motherboard. >> .. >>> Linux cannot complete booting. >> >> Also not with acpi=off so that it uses the mptable

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

On 03/03/2011 01:01 AM, Keith Hui wrote: >> Option C with GPLv2+ licensing. > > A few quick things: > > SUPERIO_FINTEK_F81865F_HAS_EARLY_SERIAL seems long-winded for a name. > > I prefer to define CONFIG_SUPERIO_HAS_EARLY_SERIAL (or even just > CONFIG_HAS_EARLY_SERIAL) within the superio Kconfig

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

On 03/03/2011 09:35 AM, Georgi, Patrick wrote: > The chipset components in Kconfig could be derived from the > devicetree.cb (statically, on config time or before) - this would > simplify board config a bit by reducing duplication. > > Early serial could be managed with a new keyword there > ("chi

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes

On 03/03/2011 04:49 PM, Keith Hui wrote: > I like this solution too. Just that it requires hacking sconfig, and > I'm not even close to qualified to actually do it. :) > > And this requires sconfig to produce some other output for romstage as > well. The hardware tree it produces is currently only

Re: [coreboot] Issue mainboard asus a8n-e

On 03/01/2011 12:25 AM, ors wrote: > Author: raby71 > Date: Mon Feb 28 22:00 2011 > last Revision: 6380 > > hi all > > I try to work my board (asus a8n-e) with coreboot. I compiled coreboot > with a debian 5.07 installation. Try building coreboot with crossgcc. just cd into util/crossgcc/ and bui

Re: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard

On 03/03/2011 02:15 AM, Joseph Smith wrote: > Alex have you tried adding irqpoll to your command line? It may give you > some clues? > Just did: http://pastebin.com/6n2AV3DU I'm looking over the output to see if there's anything useful. Alex -- coreboot mailing list: coreboot@coreboot.org htt

Re: [coreboot] [flashrom] Add NSC PC87364 support to superiotool

On 03/06/2011 01:53 AM, Michael Karcher wrote: > Hello coreboot developers, > Add National Semiconductors PC87364. Signed-off-by: Michael Karcher >>> Acked-by: Stefan Reinauer >> Michael, AFAIK the flashrom and coreboot repositories have the same user >> rights, so in theory you should

Re: [coreboot] hardware specs and bios info

On 03/06/2011 08:09 AM, donnie hylton wrote: > i only have a 32 bit edition of windows installed iigh! > and i know nothing > about programming You don't need to know how too program the space shuttle to type a few lines (hehe, even copy paste) into the terminal. > so i am not able to use the linux

Re: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard

This is my last submission of this patch. I've made the board depend on CONFIG_EXPERT, and added a help menu describing it does not work. I leave the mptable because I have invested significant effort into making sure it is correct. I leave the APCI table because I have invested effort into getting

[coreboot] [The 604 CAR crusades][Master Yoda style] Preludium

Hi everyone, The Tyan S2735 a Socket 604 (Intel) board it is which CAR it uses I found. "Why care I should?" yourself you ask. Because eight boards which socket 604 use, ROMCC they are. dell/s1850 intel/jarrell intel/xe7501devkit supermicro/x6dai_g supermicro/x6dhe_g supermicro/x6dhe_g2 supermicr

[coreboot] [PATCH] [1/4] [The 604 CAR crusades] Episode I - The Superio Menace

See patch. Enable the NSC PC87427 early_init to be used with CAR boards. The regular coompiler will complain about unused variables or unused functions. Remove unused variables, and only include unused functions if __ROMCC__ is defined. Signed-off-by: Alexandru Gagniuc Index: src/superio/nsc/pc

[coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III - Revenge of the Abuild

While the previous two patches were innocently trivial and abuild tested, this one _will_ break the build for several Socket 604 boards. We want the build to be broken until we can port those to CAR. See patch for verbosity. The Tyan s2735 is a Socket 604 board that uses CAR. cache_as_ram.inc is i

[coreboot] [PATCH][2/4][The 604 CAR crusades] Episode II - The Northbridge Wars

See patch. We need to do two things to allow the intel e7520 to be used by CAR boards. Remove unused variables. Add a declaration for sdram_initialize(). Signed-off-by: Alexandru Gagniuc Index: src/northbridge/intel/e7520/raminit.c ===

[coreboot] [PATCH] [4/4] [The 604 CAR crusades] Episode IV - A new board

See patch. Fixes the build errors that occur when compiling the Supermicro X6DHE-G2 as a CAR board. Unused variables are removed, and unused functions are excluded with #if/#endif Signed-off-by: Alexandru Gagniuc Index: src/mainboard/supermicro/x6dhe_g2/Kconfig =

Re: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III - Revenge of the Abuild

On 03/09/2011 11:19 PM, Stefan Reinauer wrote: > * Alex G. [110309 21:59]: >> While the previous two patches were innocently trivial and abuild >> tested, this one _will_ break the build for several Socket 604 boards. >> We want the build to be broken until we can port thos

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