Re: [time-nuts] DDS'ery narrow scoped.
On 21/06/11 12:48, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. Cheers, Magnus - this reply was only a month late... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Magnus, It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) Luis Cupido. ct1dmk. p.s. No problem with the delay... ;-) On 7/21/2011 9:11 AM, Magnus Danielson wrote: On 21/06/11 12:48, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. Cheers, Magnus - this reply was only a month late... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Dear Luis, On 07/21/2011 05:30 PM, Luis Cupido wrote: Magnus, It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) As I was tired I did not disclose enough details for implementation, but selected to be brief to bring in the approach to see if it was obvious or not. OK. A typical phase accumulator of n bits have N = 2^n possible states. Considering that fout = fclk * M/N where M is the normal phase-accumulator frequency control you can also realize that it takes N/gcd(M,N) state-changes to come back to the original state, so it can take a number of output cycles for all the beat frequencies to take integer cycles. If you instead want to select N freely you have to realize that while we every clock cycle perform P = P + M we assume that the operation is modulus N, so the actual formula is P = (P + M) mod N but since N was of the form 2^n it is trivial to truncate the bit of and just do N bit addition. So far I have only been very picky about details. If we now want to choose N freely to be N = 2^n we realize that we still needs to do the modulus calculation. Come to think of it, it always has two outcomes... P = P + M and P = P + M - N We can also know which to pick, since P cannot be larger than N and it cannot be below zero, so assuming we have a P already within those limits all it takes is a comparision of P if (P+M = N) P = P + M - N else P = P + M That is enough for simulation, but doesn't quite cut it for FPGA since you would get the propagation delay of both the comparision and the additions... on every cycle. We can improve on this by calculating two potential sums, and watch the carry from one of them to let a mux select between them. Also, the M-N difference is fairly static, so we pre-calculate it. precalc O = M - N cycle P1 = P + M C|P2 = P + O if (C == 0) P = P2 else P = P1 That should give you all the M/N relationships you would like to play with in a fairly sufficient FPGA structure. Much finer control over spurioses that way. Still fairly cheap in FPGA terms. I hope you have what you need to start fooling around. I could throw together some VHDL code for you if you really need it. With above re-definition of the problem the performance hit in fclk should not be as severe as the naive approach. Luis Cupido. ct1dmk. p.s. No problem with the delay... ;-) As it ended with you not saying you had a good solution, I thought it would be nice to send a message anyway. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
IMHO, that would require a sine table with a steerable number of entries. Very problematic for a tunable DDS, but doable for a fixed frequency application, although address mirroring for ROM size reduction would require real address comparators instead just using the 2 MSBs as a selector. The table could also be in RAM instead of ROM without large increase of the cost in an FPGA, so with some processor support one might approach tunable. regards, Gerhard It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) On 7/21/2011 9:11 AM, Magnus Danielson wrote: You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Gerhard. This was an old thing I asked a month ago or so... Only the MSB of the accumulator is used to serve as reference to a pll. No sin or DAC involved ;-) Luis Cupido. ct1dmk On 7/21/2011 6:10 PM, dk...@arcor.de wrote: IMHO, that would require a sine table with a steerable number of entries. Very problematic for a tunable DDS, but doable for a fixed frequency application, although address mirroring for ROM size reduction would require real address comparators instead just using the 2 MSBs as a selector. The table could also be in RAM instead of ROM without large increase of the cost in an FPGA, so with some processor support one might approach tunable. regards, Gerhard It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) On 7/21/2011 9:11 AM, Magnus Danielson wrote: You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Your algorithm looks very much like the solution to the problem how to find divider values in a rf receiver having a very low IF and *not* full length divider chains for dividing all the needed reference frequencies. So how to find two values connected. Interesting. - Henry -- ehydra.dyndns.info Magnus Danielson schrieb: As I was tired I did not disclose enough details for implementation, but selected to be brief to bring in the approach to see if it was obvious or not. OK. A typical phase accumulator of n bits have N = 2^n possible states. ... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
On 07/21/2011 07:10 PM, dk...@arcor.de wrote: IMHO, that would require a sine table with a steerable number of entries. Very problematic for a tunable DDS, but doable for a fixed frequency application, although address mirroring for ROM size reduction would require real address comparators instead just using the 2 MSBs as a selector. The table could also be in RAM instead of ROM without large increase of the cost in an FPGA, so with some processor support one might approach tunable. True, this is an issue if you waveshape to sine/cosine or other suitable waveform. The scaling error is N/2^n so you would have to multiply by 2^n/N to get proper scale. A few shifted down adds to form a multiply approximation would help to reduce the phase-jump with associated spurious generation. However, in Luis application he only uses the MSB. The MSB would get a PWM factor skewed from 50%, in fact it becomes N/2^n. Again, PWM factor can be adjusted with the addition/multiplication trick mentioned above... if it is important for the application. Otherwise it is just wasted logic. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
On 07/21/2011 08:44 PM, Jim Lux wrote: On 7/21/11 8:30 AM, Luis Cupido wrote: Magnus, It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) You can set up a sine table with any number of entries. Powers of two are popular, but, it could be anything.. Say you had multiple tables, one 20 long, one 21 long, one 22 long. You could use the 20 long one for generating 1/20th of a Hz, the 21 long one for generating 1/21th Hz, etc. That so obvious, we did not consider it a problem. The problem is when you need a large variation of N. Using a tuneable scaling to map into a suitable length (power of too) would be a better choice. Most FPGAs today have hardware multiplier blocks that can do the scaling needed, otherwise shift-add scaling (similar to CORDIC) would be a possibility as I mentioned in another post. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Thanks Jim, Joseph already pointed me to a pdf in a previous post. Now it is digestion time... should I say congestion !!! those MASH delta-sigmas are killing me... lc. ct1dmk. On 6/23/2011 4:30 AM, Jim Lux wrote: On 6/22/11 3:36 PM, Luis Cupido wrote: I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. if you email the author, often they will send you a pdf of the paper (or they'll have it on the web). The standard IEEE copyright assignment lets the author self publish on their own website or by sending reprints electronically. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. On 6/21/2011 11:48 AM, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
May Google be with you: A search on the title and an author yielded: http://petrified.ucsd.edu/~ispg-adm/pubs/mtt-s_2006.pdf From: Luis Cupido cup...@mail.ua.pt To: Discussion of precise time and frequency measurement time-nuts@febo.com Date: 06/22/2011 06:37 PM Subject:Re: [time-nuts] DDS'ery narrow scoped. Sent by:time-nuts-boun...@febo.com I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. On 6/21/2011 11:48 AM, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. inline: graycol.gifinline: ecblank.gif___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
On 6/22/11 3:36 PM, Luis Cupido wrote: I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. if you email the author, often they will send you a pdf of the paper (or they'll have it on the web). The standard IEEE copyright assignment lets the author self publish on their own website or by sending reprints electronically. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Hello, El 21/06/2011 02:19, Luis Cupido escribió: Imagine an FPGA and a square wave coming out. Just that. Nothing more. (That is what I had in mind when querying about the MSB usage in the first place.) My first approach was the ACC MSB (and that is working already on the bench.) I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. What it the topology you're using now? Also, I would like to know which DDS core are you using? (since I will need to use one quite soon, probably on a Cyclone IV E) Best regards, Javier ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
But I forgot to add that the resultant jitter will be also the sampling rate period (10ns at 100MHz), so I think that the output will not be too clean... so I'm afraid it will not be a great improvement over using only the MSB :) Regards, Javier El 21/06/2011 08:37, Javier Herrero escribió: I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Luis, the information that you are concerned about close carrier spurs that will pass through the PLL's low pass filter is not precise enough: are you talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or are you going to build a device for precise timing applications where also spurs far below (perhaps orders of magnitude below) 1 Hz may be of concern? Best regards Ulrich Bangert, DF6JB -Ursprungliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von Luis Cupido Gesendet: Dienstag, 21. Juni 2011 02:20 An: Discussion of precise time and frequency measurement Betreff: [time-nuts] DDS'ery narrow scoped. Folks, Many thanks to you all, for the info. This is indeed a great forum. My aplic. is a DDS signal that will serve as reference for a pll with a relatively narrow loop filter. As I said before. Most replies presume the analog world with DAC filters etc etc. But that I know ;-) I'm digging out the possibilities in the digital side not involving going back to analog and back to digital. this is how this started :-) Now that you all have been so kind in the great comments you gave, please let me just be very very very specific. Imagine an FPGA and a square wave coming out. Just that. Nothing more. (That is what I had in mind when querying about the MSB usage in the first place.) My first approach was the ACC MSB (and that is working already on the bench.) So I'm researching a way to have that digital output cleaner (spurs) without leaving the digital(FPGA) world sticking to the block diagram of one FPGA one digital output. Specially worried about close in spurs (the far away ones won't bother me much). That is really scenario I'm trying to picture if there is any hope to generate a cleaner digital output out of an FPGA (dds with whatever processing required to be done after and producing a square wave). Thanks for your patience. Luis Cupido. ct1dmk P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
In the old days, HI, we used to use 6 dB/bit for SFDR for the DAC as a rule of thumb. In practice, it needed to be somewhat better. So, even with 6 dB/bit it would require a minimum of 25 bits. Good thing back then, in the early 70's I was working on ASW stuff at acoustic frequencies and some of this was doable. However, we did not require a great SFDR. More recently in the late 80's and 90's, I was concerned in getting DDSs in the 500 to 1 GHz range. Lots of RD money and lots of promises, but, no cigar for a real usable product. 73 - Mike Mike B. Feher, EOZ Inc. 89 Arnold Blvd. Howell, NJ, 07731 732-886-5960 office 908-902-3831 cell -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Ulrich Bangert Sent: Tuesday, June 21, 2011 5:03 AM To: 'Discussion of precise time and frequency measurement' Subject: Re: [time-nuts] DDS'ery John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com
Re: [time-nuts] DDS'ery
to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? It's being used as part of a digital downconverter in my case, not driving a DAC. In this application, DDS artifacts would ultimately show up as spurs on phase noise plots or as ripple in ADEV plots. I haven't seen any unaccounted-for spurs above -130 to -140 dBc (where they could be coming from pretty much anywhere), so I've been happy with the core's real-world performance. -- john, KE5FX ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Hi, I'm an Altera user and would say the DDS core generator is really very good, I would expect it to be not too different from Xilinx these days. (does anyone that lives on both worlds know better ?) lc ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Hi Ulrich, Loop bandwidth could be in the KHz region or even less. I could choose more or less freely from Hz to many KHz but there are obvious tradeoffs and it is hard to decide. The phase noise of the VCO when I go too narrow versus the ammount of spurs when I go too wide. Application is the first LO for an experiment in SDR radio at VHF-SHF region,(not HF). Luis Cupido. ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: Luis, the information that you are concerned about close carrier spurs that will pass through the PLL's low pass filter is not precise enough: are you talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or are you going to build a device for precise timing applications where also spurs far below (perhaps orders of magnitude below) 1 Hz may be of concern? Best regards Ulrich Bangert, DF6JB -Ursprungliche Nachricht- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. On 6/21/2011 7:43 AM, Javier Herrero wrote: But I forgot to add that the resultant jitter will be also the sampling rate period (10ns at 100MHz), so I think that the output will not be too clean... so I'm afraid it will not be a great improvement over using only the MSB :) Regards, Javier El 21/06/2011 08:37, Javier Herrero escribió: I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
I've played with the core from altera for a while, but since I was only interested in 1 bit I'm now playing with my own code. Trivial variations on the plain old clocked accumulator architecture. lc On 6/21/2011 7:37 AM, Javier Herrero wrote: What it the topology you're using now? Also, I would like to know which DDS core are you using? (since I will need to use one quite soon, probably on a Cyclone IV E) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Hi, I live in both worlds (more or less :) ), and the tools seems somewhat similar (I suspect that when one of them includes a feature, the other tries to catch the rythm and viceversa). I've had a look to the Xilinx DDS compiler, and it is somewhat different. You can download the free version of the Xilinx ISE Design Suite and play a bit around. For the project where I will implement the DDCON I selected the Altera mainly due to similarities with other project that also uses Altera, availability of development boards around, and also because I'm more familiar with Linux on the Nios-II processor than on the Microblaze (and that for this project I prefer to be in the low end - Cyclone or Spartan - rather than in the higher end - Stratix or Virtex). Regards, Javier El 21/06/2011 12:34, Luis Cupido escribió: Hi, I'm an Altera user and would say the DDS core generator is really very good, I would expect it to be not too different from Xilinx these days. (does anyone that lives on both worlds know better ?) lc ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go
Re: [time-nuts] DDS'ery
Clever! At least for your spectral measurements the signal never leaves the digital domain. What is the width of the multipliers involved in the mixing? Can you give me a clue, which ADCs you are working with in the front end? In this application, DDS artifacts would ultimately show up as spurs on phase noise plots or as ripple in ADEV plots. This matches exactly my own observations in terms of ripple in the Tau-Sigma digram when i used a standard like DDS from AD for this purpose. Exactly this is why I got interested in the XILNX DDS compiler. May be the ALTERA stuff is on the same level. Have used ALTERA FPGAs and CPLDs in the past but currently I am devoted to XILINX due to the easier availability in Germany. Best regards Ulrich Bangert, DF6JB Am 21.06.2011 um 12:10 schrieb John Miles: to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? It's being used as part of a digital downconverter in my case, not driving a DAC. In this application, DDS artifacts would ultimately show up as spurs on phase noise plots or as ripple in ADEV plots. I haven't seen any unaccounted-for spurs above -130 to -140 dBc (where they could be coming from pretty much anywhere), so I've been happy with the core's real-world performance. -- john, KE5FX ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Ulrich Bangert Ortholzer Weg1 27243 Gross Ippener Deutschland Tel +49 (0)4224 95071 Fax +49 (0)4224 95072 Mob +49 (0)172 8006546 www.ulrich-bangert.de ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
There is an excellent article about cordic on http://www.andraka.com/files/crdcsrvy.pdf There are a lot of other good publications on Ray Andraka's web site. I have published a accurate sine/cosine function on www.opencores.org underhttp://opencores.org/project,sincos It is VHDL only. The test bed is a DDS and it can write the generated waves to files for inspection with Matlab. I think I have caught all these off-by-1-LSBs by now. The sine function is ROM-based with size reduction by symmetry. Getting a cos at the same time is free wrt ROMs, just 2 adders more. Pipelining can be selected from combinatorial to 10 stages, depending on your speed requirements. Amplitude and phase resolution is automatically determined by the connected bus. feedback welcome. regards, Gerhard - Original Nachricht Von: li...@lazygranch.com An: Discussion of precise time and frequency measurement time-nuts@febo.com Datum: 20.06.2011 22:26 Betreff: Re: [time-nuts] DDS'ery With the coordic (yeah, sometimes cordic), you need to build it a few more bits wider than the DAC. Then it closely matches the lookup table. One of the best references for the coordic I found was a PhD dissertation at ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On 6/21/11 6:14 AM, dk...@arcor.de wrote: There is an excellent article about cordic on http://www.andraka.com/files/crdcsrvy.pdf Yes..good explanation.. So, in the general case where you might want to rotate by an arbitrary angle at each time step, where the angle doesn't happen to be 1/2^n, you still need either multiple shift/add operations, or a multiply add. (i.e. it's no different than longhand multiplication... it takes N (optional) adds to multiply by an N bit precision number, or you cleverly parallelize/pipeline it). And, in a lot of applications, you'll need to still do a multiply by the gain (product of all those cos phi) term you factored out I can see that there could be advantages in implementation, but in the general case, is it actually that much more efficient? (in a CPU with no multiply, yes, it's a lot better, because it's essentially the same as doing long multiplication, but you get more done for the same amount of work) Maybe it's a how many gates do you need for a given precision sort of thing? Or the fact that it generates sin/cos together (which is very useful in some cases) in a random give me the cos(theta) sort of situation (e.g. a calculator), compared to computing the series expansion, clearly CORDIC is the way to go. But in a DDS, you're generating a continuous series of samples. I'll have to think about it. (and, because it's integrating a difference equation, CORDIC does have the accumulating roundoff, unless you compute each sin/cos from scratch each time) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
-Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Ulrich Bangert Sent: Tuesday, June 21, 2011 4:37 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Clever! At least for your spectral measurements the signal never leaves the digital domain. What is the width of the multipliers involved in the mixing? Can you give me a clue, which ADCs you are working with in the front end? I was using AD9446s for a long time, but I'm going with LTC2216s for the final design. They're a lot pricier but they have better S/H front ends. That goes unnoticed in many cases but can be pretty important in others. The current implementation multiplies 26 bits from the DDS by 16 bits from the ADCs and keeps the top 28 bits of the baseband product. The noise floor does go up noticeably if you throw away too many bits. In this application, DDS artifacts would ultimately show up as spurs on phase noise plots or as ripple in ADEV plots. This matches exactly my own observations in terms of ripple in the Tau- Sigma digram when i used a standard like DDS from AD for this purpose. Exactly this is why I got interested in the XILNX DDS compiler. May be the ALTERA stuff is on the same level. Have used ALTERA FPGAs and CPLDs in the past but currently I am devoted to XILINX due to the easier availability in Germany. I think they've both got some really solid parts. I usually end up reading the app notes and core user manuals from both manufacturers, since (IMHO) Altera does a better job with their docs in some cases. -- john, KE5FX ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On 06/21/2011 04:29 PM, Jim Lux wrote: On 6/21/11 6:14 AM, dk...@arcor.de wrote: There is an excellent article about cordic on http://www.andraka.com/files/crdcsrvy.pdf Yes..good explanation.. So, in the general case where you might want to rotate by an arbitrary angle at each time step, where the angle doesn't happen to be 1/2^n, you still need either multiple shift/add operations, or a multiply add. (i.e. it's no different than longhand multiplication... it takes N (optional) adds to multiply by an N bit precision number, or you cleverly parallelize/pipeline it). And, in a lot of applications, you'll need to still do a multiply by the gain (product of all those cos phi) term you factored out I can see that there could be advantages in implementation, but in the general case, is it actually that much more efficient? (in a CPU with no multiply, yes, it's a lot better, because it's essentially the same as doing long multiplication, but you get more done for the same amount of work) Maybe it's a how many gates do you need for a given precision sort of thing? Or the fact that it generates sin/cos together (which is very useful in some cases) in a random give me the cos(theta) sort of situation (e.g. a calculator), compared to computing the series expansion, clearly CORDIC is the way to go. But in a DDS, you're generating a continuous series of samples. I'll have to think about it. (and, because it's integrating a difference equation, CORDIC does have the accumulating roundoff, unless you compute each sin/cos from scratch each time) You do calculate the sin/cos from scratch on each sample. The CORDIC add/sub strategy allows for pipe-line processing at sample rate and will take less real estate than equivalent LUT. Do read the article that Bruce referenced. You could also play a little with integrators and stuff to let the dynamics grow up if you can allow some upper frequency limitation. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
In message 4dff5d29.2070...@mail.ua.pt, Luis Cupido writes: Isn't it the very same thing as just using the most significant bit of the accumulator. Indeed it is, and that's how programmable digital clocks often work. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Forgot the sine table... I meant obviously ...an accumulator 'sine table' and DAC... lc. On 6/20/2011 3:46 PM, Luis Cupido wrote: Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. Or am I missing something here ? Comments appreciated. thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Hello, No, it is not the same. If you just use the MSB of the accumulator, it has a lot of period jitter. It can be unnoticeable if the ration between reference frequency and output frequency is very high. Think on the process inversely: draw a sine wave, and sample it at for example 4.3 samples per period, and look when the sample becames positive and when it is negative (that would be the same to take only the MSB). Best regards Javier El 20/06/2011 16:46, Luis Cupido escribió: Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. Or am I missing something here ? Comments appreciated. thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
In message 4dff5f2f.7050...@hvsistemas.es, Javier Herrero writes: No, it is not the same. If you just use the MSB of the accumulator, it = has a lot of period jitter. It can be unnoticeable if the ration between = reference frequency and output frequency is very high. In practice, this jitter is a lot lower than you get from squaring the sinewave. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Luis: No, not the same. The most significant bit out of the accumulator has the alias information on it (Fs +/- Fo), so it still needs to be run through the low pass filter to clean off the alias signals. The alias signals manifest themselves as jitter, so no amount of just clipping will remove them. If your application is not sensitive to the alias frequencies, then OK to drive out of the DDS directly. If you are driving something like a mixer in a wide band radio, then you still need to use the low pass filters. They don't call them anti-alias filters for no reason. --- Graham / KE9H == On 6/20/2011 9:46 AM, Luis Cupido wrote: Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. Or am I missing something here ? Comments appreciated. thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
The jitter when taking only the MSB is same as the DDS clock period. I don't think that squaring the filtered sinewave you will get that jitter (of course, if you square the sinewave with no filtering, you will get the same jitter that taking only the MSB). In fact, it is the reason that AD9850/AD9851 include a comparator instead of just an MSB output. Regards, Javier El 20/06/2011 17:04, Poul-Henning Kamp escribió: In message4dff5f2f.7050...@hvsistemas.es, Javier Herrero writes: No, it is not the same. If you just use the MSB of the accumulator, it = has a lot of period jitter. It can be unnoticeable if the ration between = reference frequency and output frequency is very high. In practice, this jitter is a lot lower than you get from squaring the sinewave. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Thanks for the comments... Yes the key is obviously the low pass filtering one has the other doesn't. I had mainly in my mind a PLL following that ACC. so actually driving a phase comparator of a PLL (narrow enough loop bw) that problem would not exist. Ok great. Good point on the mixer we got to have nothing in the alias region for it to be ok. (not my application at the moment but will keep that in mind) Thanks guys... Luis Cupido. ct1dmk. On 6/20/2011 4:11 PM, Graham / KE9H wrote: Luis: No, not the same. The most significant bit out of the accumulator has the alias information on it (Fs +/- Fo), so it still needs to be run through the low pass filter to clean off the alias signals. The alias signals manifest themselves as jitter, so no amount of just clipping will remove them. If your application is not sensitive to the alias frequencies, then OK to drive out of the DDS directly. If you are driving something like a mixer in a wide band radio, then you still need to use the low pass filters. They don't call them anti-alias filters for no reason. --- Graham / KE9H == On 6/20/2011 9:46 AM, Luis Cupido wrote: Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. Or am I missing something here ? Comments appreciated. thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Actually it is (n*Fs +/-Fo), however, they do go down in amplitude as a SinX/X. Theoretically, they would also be there after the Sin ROM, and the only one really of concern in the real world is the Fs - Fo, hence the LPF. When I used to design DDSs in the early 70's, we typically tried to use an Fs that was about 2.5 times the max desired Fo, to make filtering easier. We also used discrete parts then :). Now, with the higher speed devices available a real high Fs can be selected to meet a desired Fmax. Of course the limit is always being pushed, and, the devices are never fast enough. Regards - Mike Mike B. Feher, EOZ Inc. 89 Arnold Blvd. Howell, NJ, 07731 732-886-5960 office 908-902-3831 cell -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Graham / KE9H Sent: Monday, June 20, 2011 11:12 AM To: time-nuts@febo.com Subject: Re: [time-nuts] DDS'ery Luis: No, not the same. The most significant bit out of the accumulator has the alias information on it (Fs +/- Fo), so it still needs to be run through the low pass filter to clean off the alias signals. The alias signals manifest themselves as jitter, so no amount of just clipping will remove them. If your application is not sensitive to the alias frequencies, then OK to drive out of the DDS directly. If you are driving something like a mixer in a wide band radio, then you still need to use the low pass filters. They don't call them anti-alias filters for no reason. --- Graham / KE9H == On 6/20/2011 9:46 AM, Luis Cupido wrote: Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. Or am I missing something here ? Comments appreciated. thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. ... Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On Mon, 20 Jun 2011 16:39:16 +0100 Luis Cupido cup...@mail.ua.pt wrote: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? If you filter a square wave, you have a lot more harmonics than if you filter a signal that is already nearly sine. Hence the DAC stage gives you a higher signal purity. And as filters are never optimal, you'd rather go with a more pure signal :-) Attila Kinali -- Why does it take years to find the answers to the questions one should have asked long ago? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
De nada, Luis :) I've been playing around a bit with Altera NCO IP (in fact, I need to implement a digital NCO quite shortly for a project, although in this case close-in spurs are more tolerable than in other applications). A lot of information in the application note for ADI is also applicable to the purely digital side. I've not yet played on the practical side - this will be after summer :) Quartus software (for Altera FPGAs) enables to customize several parameters of their NCO IP, and plots an expected spectrum of the output signal. It is fun to explore the effect of different sin/cos algorithms (ROM-based, CORDIC, multiplier-based), phase accumulator and magnitude precision, and angular resolution. Although the IP is not free (but can be used for evaluation), Quartus Web Edition (that it is free) enables to play a bit around - and at least it is illustrative :) I forgot that Section 7 shows what occurs taking only the MSB (it shows it using a comparator after the DAC, without filtering and also after filtering). Best regards, Javier El 20/06/2011 18:46, Luis Cupido escribió: Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. ... Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On 6/20/11 7:46 AM, Luis Cupido wrote: Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. The zero crossing using just the MSB will have jitter, compared to making a sign wave and then letting the zero crossing occur between samples. Depending on your application, MSB only might work well enough. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On 6/20/11 8:39 AM, Luis Cupido wrote: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Spur content heading into the filter.. the sine table and DAC greatly reduces the harmonic content of the output, which makes filtering easier. You could think of the cos table and DAC as a specialized filter ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On 6/20/11 9:46 AM, Luis Cupido wrote: Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. ... Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Tons.. Jouko Vankka wrote whole books about it. Direct Digital Synthesizers and transmitters for software radio Direct Digital Synthesizers: Theory, Design and Applications You might want to look at various Error Feedback/Error Filtering schemes which allow you to use a smaller cosine table and/or smaller DAC and have better spur performance. Vankka, J, A direct digital synthesizer with a tunable error feedback structure, IEEE Trans on Comm, V45, #4, pp416-420, 1997 Vankka's EF technique works quite well at suppressing spurs close to the carrier (at the expense of pushing them farther out). Reinhardt, V, Spur Reduction Techniques in Direct Digital Synthesizers, Proc Intl Freq Control Symp, 1993 Flanagan, M., Zimmerman, G., Spur-reduced digital sinusoid synthesis IEEE Trans on Comm, V43, #7, pp2254-2262, 1995 (this one is about using dither to spread the spurs out) O'Leary, P., Maloberti, F., A direct-digital synthesizer with improved spectral performance, IEEE Trans on Comm, V39, #7, 1991 You might also look at some of the spur cancellation things, such as the one implemented in some of AD's DDS parts.. Basically, it's a second NCO that generates a coherent signal that is subtracted/added to the primary signal to notch out the spur. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Just a FYI, you don't have to use sine lookup tables. You can generate sine and cosine on the fly with a coordic. Perhaps not easy at RF speed, but very common in audio DSP. -Original Message- From: Jim Lux jim...@earthlink.net Sender: time-nuts-boun...@febo.com Date: Mon, 20 Jun 2011 12:04:24 To: time-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS'ery On 6/20/11 9:46 AM, Luis Cupido wrote: Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. ... Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Tons.. Jouko Vankka wrote whole books about it. Direct Digital Synthesizers and transmitters for software radio Direct Digital Synthesizers: Theory, Design and Applications You might want to look at various Error Feedback/Error Filtering schemes which allow you to use a smaller cosine table and/or smaller DAC and have better spur performance. Vankka, J, A direct digital synthesizer with a tunable error feedback structure, IEEE Trans on Comm, V45, #4, pp416-420, 1997 Vankka's EF technique works quite well at suppressing spurs close to the carrier (at the expense of pushing them farther out). Reinhardt, V, Spur Reduction Techniques in Direct Digital Synthesizers, Proc Intl Freq Control Symp, 1993 Flanagan, M., Zimmerman, G., Spur-reduced digital sinusoid synthesis IEEE Trans on Comm, V43, #7, pp2254-2262, 1995 (this one is about using dither to spread the spurs out) O'Leary, P., Maloberti, F., A direct-digital synthesizer with improved spectral performance, IEEE Trans on Comm, V39, #7, 1991 You might also look at some of the spur cancellation things, such as the one implemented in some of AD's DDS parts.. Basically, it's a second NCO that generates a coherent signal that is subtracted/added to the primary signal to notch out the spur. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Jim Lux wrote: On 6/20/11 9:46 AM, Luis Cupido wrote: Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. ... Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Tons.. Jouko Vankka wrote whole books about it. Direct Digital Synthesizers and transmitters for software radio Direct Digital Synthesizers: Theory, Design and Applications You might want to look at various Error Feedback/Error Filtering schemes which allow you to use a smaller cosine table and/or smaller DAC and have better spur performance. Vankka, J, A direct digital synthesizer with a tunable error feedback structure, IEEE Trans on Comm, V45, #4, pp416-420, 1997 Vankka's EF technique works quite well at suppressing spurs close to the carrier (at the expense of pushing them farther out). Reinhardt, V, Spur Reduction Techniques in Direct Digital Synthesizers, Proc Intl Freq Control Symp, 1993 Flanagan, M., Zimmerman, G., Spur-reduced digital sinusoid synthesis IEEE Trans on Comm, V43, #7, pp2254-2262, 1995 (this one is about using dither to spread the spurs out) O'Leary, P., Maloberti, F., A direct-digital synthesizer with improved spectral performance, IEEE Trans on Comm, V39, #7, 1991 You might also look at some of the spur cancellation things, such as the one implemented in some of AD's DDS parts.. Basically, it's a second NCO that generates a coherent signal that is subtracted/added to the primary signal to notch out the spur. See also: http://www.iro.umontreal.ca/~mignotte/IFT3205/Documents/TipsAndTricks/UltraLowPhaseNoiseDSPOscillator.pdf http://www.iro.umontreal.ca/%7Emignotte/IFT3205/Documents/TipsAndTricks/UltraLowPhaseNoiseDSPOscillator.pdf Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Inside an FPGA, CORDIC can be implemented performing quite fast. An open-source implementation of CORDIC algorithm and a DDS using look-up table or CORDIC can be found in OpenCores, gh_vhdl_lib. Jim, thank you very much for all the excellent references, and particularly the last one about the CORDIC variation. The Altera simulations of its NCO showns significant more spurii for CORDIC (traditional one) than the other alternatives for same phase accumulator and magnitude precisions, and angular same angular resolution, but it is by far the most effective in terms of FPGA usage. Probably I will use the CORDIC approach in the implementation of my digital down-converter, but the OpenCores core instead of the Altera IP, if it is clean enough (the signal I need to downconvert is 8-bit quantized and with poor S/N ratio, so some -40dB spurious will not have significance). Regards, Javier El 20/06/2011 21:17, li...@lazygranch.com escribió: Just a FYI, you don't have to use sine lookup tables. You can generate sine and cosine on the fly with a coordic. Perhaps not easy at RF speed, but very common in audio DSP. -Original Message- From: Jim Luxjim...@earthlink.net Sender: time-nuts-boun...@febo.com Date: Mon, 20 Jun 2011 12:04:24 To:time-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS'ery On 6/20/11 9:46 AM, Luis Cupido wrote: Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. ... Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Tons.. Jouko Vankka wrote whole books about it. Direct Digital Synthesizers and transmitters for software radio Direct Digital Synthesizers: Theory, Design and Applications You might want to look at various Error Feedback/Error Filtering schemes which allow you to use a smaller cosine table and/or smaller DAC and have better spur performance. Vankka, J, A direct digital synthesizer with a tunable error feedback structure, IEEE Trans on Comm, V45, #4, pp416-420, 1997 Vankka's EF technique works quite well at suppressing spurs close to the carrier (at the expense of pushing them farther out). Reinhardt, V, Spur Reduction Techniques in Direct Digital Synthesizers, Proc Intl Freq Control Symp, 1993 Flanagan, M., Zimmerman, G., Spur-reduced digital sinusoid synthesis IEEE Trans on Comm, V43, #7, pp2254-2262, 1995 (this one is about using dither to spread the spurs out) O'Leary, P., Maloberti, F., A direct-digital synthesizer with improved spectral performance, IEEE Trans on Comm, V39, #7, 1991 You might also look at some of the spur cancellation things, such as the one implemented in some of AD's DDS parts.. Basically, it's a second NCO that generates a coherent signal that is subtracted/added to the primary signal to notch out the spur. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
With the coordic (yeah, sometimes cordic), you need to build it a few more bits wider than the DAC. Then it closely matches the lookup table. One of the best references for the coordic I found was a PhD dissertation at Stanford. The author's last name was Ahmed IIRC. It is a very versatile algorithm. You can vary the magnitude of the initial vector to AM the signal. PM is done by directly. The coordic can also multiply, divide, and compute inverse trig functions. It was used (and might still be) in scientific calculators. We did a FSK demod with the coordic. Basically unwrap the phase of the signal and least mean square fit the phase to a straight line, where the slope of the line relates to the frequency. -Original Message- From: Javier Herrero jherr...@hvsistemas.es Sender: time-nuts-boun...@febo.com Date: Mon, 20 Jun 2011 21:46:11 To: time-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS'ery Inside an FPGA, CORDIC can be implemented performing quite fast. An open-source implementation of CORDIC algorithm and a DDS using look-up table or CORDIC can be found in OpenCores, gh_vhdl_lib. Jim, thank you very much for all the excellent references, and particularly the last one about the CORDIC variation. The Altera simulations of its NCO showns significant more spurii for CORDIC (traditional one) than the other alternatives for same phase accumulator and magnitude precisions, and angular same angular resolution, but it is by far the most effective in terms of FPGA usage. Probably I will use the CORDIC approach in the implementation of my digital down-converter, but the OpenCores core instead of the Altera IP, if it is clean enough (the signal I need to downconvert is 8-bit quantized and with poor S/N ratio, so some -40dB spurious will not have significance). Regards, Javier El 20/06/2011 21:17, li...@lazygranch.com escribió: Just a FYI, you don't have to use sine lookup tables. You can generate sine and cosine on the fly with a coordic. Perhaps not easy at RF speed, but very common in audio DSP. -Original Message- From: Jim Luxjim...@earthlink.net Sender: time-nuts-boun...@febo.com Date: Mon, 20 Jun 2011 12:04:24 To:time-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS'ery On 6/20/11 9:46 AM, Luis Cupido wrote: Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. ... Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Tons.. Jouko Vankka wrote whole books about it. Direct Digital Synthesizers and transmitters for software radio Direct Digital Synthesizers: Theory, Design and Applications You might want to look at various Error Feedback/Error Filtering schemes which allow you to use a smaller cosine table and/or smaller DAC and have better spur performance. Vankka, J, A direct digital synthesizer with a tunable error feedback structure, IEEE Trans on Comm, V45, #4, pp416-420, 1997 Vankka's EF technique works quite well at suppressing spurs close to the carrier (at the expense of pushing them farther out). Reinhardt, V, Spur Reduction Techniques in Direct Digital Synthesizers, Proc Intl Freq Control Symp, 1993 Flanagan, M., Zimmerman, G., Spur-reduced digital sinusoid synthesis IEEE Trans on Comm, V43, #7, pp2254-2262, 1995 (this one is about using dither to spread the spurs out) O'Leary, P., Maloberti, F., A direct-digital synthesizer with improved spectral performance, IEEE Trans on Comm, V39, #7, 1991 You might also look at some of the spur cancellation things, such as the one implemented in some of AD's DDS parts.. Basically, it's a second NCO that generates a coherent signal that is subtracted/added to the primary signal to notch out the spur. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list
Re: [time-nuts] DDS'ery
On Mon, 20 Jun 2011 20:26:46 + li...@lazygranch.com wrote: With the coordic (yeah, sometimes cordic), you need to build it a few more bits wider than the DAC. Then it closely matches the lookup table. One of the best references for the coordic I found was a PhD dissertation at Stanford. The author's last name was Ahmed IIRC. This seems to be Signal processing algorithms and architectures by Hassan Masud Ahmed, 1982. Unfortunately, my google skills fail me to locate a digital copy of this dissertation. I'm even unable to locate a paper version in any of the university libraries. Does anyone have this as PS or PDF? Attila Kinali -- Why does it take years to find the answers to the questions one should have asked long ago? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Not even remotely. Try it. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Poul-Henning Kamp Sent: Monday, June 20, 2011 8:04 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery In message 4dff5f2f.7050...@hvsistemas.es, Javier Herrero writes: No, it is not the same. If you just use the MSB of the accumulator, it = has a lot of period jitter. It can be unnoticeable if the ration between = reference frequency and output frequency is very high. In practice, this jitter is a lot lower than you get from squaring the sinewave. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
You did a good job just finding the title. Socrates search? I looked at it in the flesh in the Terman library. I suppose the dissertation can be purchased. I left out hyperbolic functions. I'm not sure if it can compute logs. I had need once to compute a log and found an old paper from IBM for a log algorithm. We did a DTMF with a coordic. This was all part of a DSP based modem, unique for its time, routine to the point of boredom today. The DTMF accuracy was of course spot on. Basically once you have the algorithm in the box, you might as well use it, even if the quality is overkill. I don't have Marvin's Frerking's book on DSP comms because I left that field before it was published, but I am told it covers cordic and similar algorithms. If you google Marvin Frerking cordic, some of his book is digitized in google books. --Original Message-- From: Attila Kinali To: li...@lazygranch.com To: Discussion of precise time and frequencymeasurement Subject: Re: [time-nuts] DDS'ery Sent: Jun 20, 2011 2:35 PM On Mon, 20 Jun 2011 20:26:46 + li...@lazygranch.com wrote: With the coordic (yeah, sometimes cordic), you need to build it a few more bits wider than the DAC. Then it closely matches the lookup table. One of the best references for the coordic I found was a PhD dissertation at Stanford. The author's last name was Ahmed IIRC. This seems to be Signal processing algorithms and architectures by Hassan Masud Ahmed, 1982. Unfortunately, my google skills fail me to locate a digital copy of this dissertation. I'm even unable to locate a paper version in any of the university libraries. Does anyone have this as PS or PDF? Attila Kinali -- Why does it take years to find the answers to the questions one should have asked long ago? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Unfortunately, my google skills fail me to locate a digital copy of this dissertation. My Google-fu is pretty decent. You can apparently order a PDF for web download for $37 from: http://proquest.umi.com/pqdlink?did=753152421Fmt=7clientId =79356RQT=309VName=PQD I say apparently because I haven't actually TRIED it... but there it is. Peter K1PGV ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On 6/20/11 12:17 PM, li...@lazygranch.com wrote: Just a FYI, you don't have to use sine lookup tables. You can generate sine and cosine on the fly with a coordic. Perhaps not easy at RF speed, but very common in audio DSP. It's a tradeoff.. To do CORDIC you need four multiplies and 2 adds, which might be a lot of gates, if you have a fair number of bits, compared to an adder and some lookup tables. If you have a fast multiply instruction on a processor, then CORDIC gets very attractive. The other problem with CORDIC is that roundoff errors accumulate, the longer you run the generator for, because it's basically a difference equation/numerical integration sort of scheme. That said, some of AD's latest DDSes use a monolithic CORDIC generator. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
I don't have the algorithm in front of me, but I don't recall any multiplication, just addition and magnitude comparison. -Original Message- From: Jim Lux jim...@earthlink.net Sender: time-nuts-boun...@febo.com Date: Mon, 20 Jun 2011 17:14:44 To: Discussion of precise time and frequency measurementtime-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS'ery On 6/20/11 12:17 PM, li...@lazygranch.com wrote: Just a FYI, you don't have to use sine lookup tables. You can generate sine and cosine on the fly with a coordic. Perhaps not easy at RF speed, but very common in audio DSP. It's a tradeoff.. To do CORDIC you need four multiplies and 2 adds, which might be a lot of gates, if you have a fair number of bits, compared to an adder and some lookup tables. If you have a fast multiply instruction on a processor, then CORDIC gets very attractive. The other problem with CORDIC is that roundoff errors accumulate, the longer you run the generator for, because it's basically a difference equation/numerical integration sort of scheme. That said, some of AD's latest DDSes use a monolithic CORDIC generator. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Correct, CORDIC doesn't require a multiplier, only adds and shifts. That's the whole idea. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of li...@lazygranch.com Sent: Monday, June 20, 2011 5:24 PM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery I don't have the algorithm in front of me, but I don't recall any multiplication, just addition and magnitude comparison. -Original Message- From: Jim Lux jim...@earthlink.net Sender: time-nuts-boun...@febo.com Date: Mon, 20 Jun 2011 17:14:44 To: Discussion of precise time and frequency measurementtime- n...@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS'ery On 6/20/11 12:17 PM, li...@lazygranch.com wrote: Just a FYI, you don't have to use sine lookup tables. You can generate sine and cosine on the fly with a coordic. Perhaps not easy at RF speed, but very common in audio DSP. It's a tradeoff.. To do CORDIC you need four multiplies and 2 adds, which might be a lot of gates, if you have a fair number of bits, compared to an adder and some lookup tables. If you have a fast multiply instruction on a processor, then CORDIC gets very attractive. The other problem with CORDIC is that roundoff errors accumulate, the longer you run the generator for, because it's basically a difference equation/numerical integration sort of scheme. That said, some of AD's latest DDSes use a monolithic CORDIC generator. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
That is maybe interesting to you: http://www.holmea.demon.co.uk/Projects.htm#Frac - Henry -- ehydra.dyndns.info Luis Cupido schrieb: P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
