Dear Vivek,
(Please follow the mailing list etiquette and use interleaved style,
when replying.)
Am 21.07.20 um 04:09 schrieb Vivek Gupta:
Actually I am not able to find Gem5 simulation environment as listed
option in kconfig.
It’s the first time I am hearing of the “Gem5 simulation
Dear coreboot folks,
I’d like to run upstream coreboot on the MEDION AKOYA S2013
(google/veyron_jaq) [1].
As I have access to a DediProg EM100Pro [1] including a 10-Pin Split
Cable with a grabber on the hold pin [2], and a clip, I was wondering if
I can hook it up without soldering to boot
Dear Vivek,
Am 16.07.20 um 00:46 schrieb Vivek Gupta via coreboot:
I am currently looking to setup AARCH64 platform simulation
verification of coreboot on Gem5 simulation environment. Do we have
any document/wikipage to understand the compilation and configuration
process?
The tutorial [1]
Dear Kyösti, dear coreboot folks,
Am 11.02.20 um 16:11 schrieb Paul Menzel:
On 2020-01-25 00:56, Kyösti Mälkki wrote:
System *boots* with one of:
1. maxcpus=0 (equivalent nosmp)
2. maxcpus=1
3. nolapic (with e1000 warning about missing MSI-X
System does *not* boot with one of:
1
Dear Nico,
Am 28.06.20 um 13:21 schrieb Nico Huber:
On 28.06.20 11:35, Paul Menzel wrote:
The only remarkable difference in the logs is:
-PCI: 06:00.0 bridge ctrl <- 016b
this seems very suspicious. Bit 3 enables VGA decoding. It shouldn't
matter because it's behind another bri
Dear coreboot folks,
On the Lenovo T60p (with external AMD/ATI graphics) there was
unfortunately a regression in the master branch. As it is bricked now, I
am only able to provide logs, and won’t be able to test or bisect for
quite some time.
I successfully tested 4.11-1593-g49111cd2ba [1]
Dear coreboot folks,
Next to the Coverity Scan reports, sent to the list again [1], I wanted
to remind everybody, that the Clang static analyzer scan-build is also
checking the coreboot code, and the results are available online [2].
There are probably some false positives in there [3], but
Dear coreboot folks,
Elyes is working on upgrading the coreboot crossgcc toolchain,
especially to GCC 10.1.0, and wants to test the results with the QEMU
emulation.
Unfortunately, for ARM devices – and probably all other non-x86 one –
there seems to no simple payload to test with.
It was
Dear HacKurx,
Am 04.06.20 um 12:49 schrieb Paul Menzel:
Am 04.06.20 um 11:26 schrieb HacKurx:
Good morning, everyone,
I hadn't updated my coreboot version for a long time on my Asrock
E350M1 card because of lack of time and because this one was on a very
I guess you mean *board
Dear Stéphane,
Am 06.06.20 um 14:45 schrieb Stéphane Delaunay via coreboot:
On Monday, May 25, 2020 1:45 PM, Christian Walter
wrote:
currently following x11 Supermicro boards are supported:
* x11ssh-tf
* x11ssm-f
[..]
Let me know if you need to know more.
Sorry for replying so late.
Dear HacKurx,
Thank you for the report.
Am 04.06.20 um 11:26 schrieb HacKurx:
Good morning, everyone,
I hadn't updated my coreboot version for a long time on my Asrock
E350M1 card because of lack of time and because this one was on a very
I guess you mean *board* and not *card*?
stable
Dear Jeremy,
Am 01.06.20 um 15:16 schrieb Jeremy Jackson:
I am looking at upgrading a Lenovo T60 that has a 4 year old Libreboot
installed.
Just a quick heads-up in case the Linux kernel does not start anymore.
You should be able to work around it by adding `maxcpus=1` to the Linux
Dear Keith,
Am 25.05.20 um 02:05 schrieb Keith Hui:
I am attempting to build SCMI [1] support for the DSDT for asus/p3b-f
to get around a PCI<->ACPI resource conflict that renders the whole
SMBus and the hardware monitor inoperative. The board has ACPI AML
hooks that run before and after
Dear Furquan, dear Aaron,
Am 14.05.20 um 12:02 schrieb Paul Menzel:
Commit 3b02006afe (device: Enable resource allocator to use multiple
ranges) [1] also breaks the qemu-i440fx, that SeaBIOS does not show any
graphics. Please find the logs attached.
Sorry, I missed that Furquan already
Dear Furquan, dear Aaron,
Commit 3b02006afe (device: Enable resource allocator to use multiple
ranges) [1] also breaks the qemu-i440fx, that SeaBIOS does not show any
graphics. Please find the logs attached.
Kind regards,
Paul
[1]: https://review.coreboot.org/c/coreboot/+/39486
$
Dear coreboot users,
Several users reported regressions with commit 3b02006afe (device:
Enable resource allocator to use multiple ranges) [1] on their devices.
$ git describe 3b02006afe8a85477dafa1bd149f1f0dba02afc7
4.12-9-g3b02006afe
It is my understanding that the change exposes
Dear Keith,
Am 13.05.20 um 05:21 schrieb Keith Hui:
I am still refining the P2B family of boards, now including the
infamous P3B-F with an unusual appetite for hacks to make work.
That said, I'm now finding that, on P3B-F, SeaBIOS hangs when it tries
to relocate itself as part of its usual
Dear Jan, dear Nico,
Just some additions.
Am 08.05.20 um 21:38 schrieb Nico Huber:
On 08.05.20 11:25, JPT wrote:
Sorry, I assumed the 11 branch was the branch for the soon to come
release. I built with master again, but there isn't much difference.
but, was there a difference? I've looked
Dear JPT,
Welcome to coreboot and congratulations for successfully running
coreboot on a device. Thank you for your report.
Am 07.05.20 um 17:38 schrieb JPT:
I got several problems with coreboot on X220.
I report them for you to improve coreboot.
I's not important for me.
If you need more
Dear coreboot folks,
Despite ever increasing flash ROM chip sizes, small images are still
desired for faster boot times, faster flash times, and more space for
payloads, which is sometimes needed for adding several payloads
(including GRUB/TianoCore) or Linux payloads.
Jacob Garber did great
Dear Nitin,
Am 24.04.20 um 11:53 schrieb nitin.ramesh.si...@gmail.com:
I have tried different measures to increase the load on CPU, but
still the frequency reflects the same value ie. 800Mz.
My question is why this behavior is different w.r.t the one when
system boots up with BIOS.
If you
Dear Nitin,
Am 23.04.20 um 14:35 schrieb nitin.ramesh.si...@gmail.com:
I am using coreboot to boot Denverton cpu (CPU C3558) based board.
Nice. Are you going to send it upstream?
I can see that the cpu frequency is set to the correct value i.e. "2200 Mhz"
under the coreboot logs.
.
"
CPU
Dear Max,
Am 23.04.20 um 12:34 schrieb Max Zim:
On 23/04/2020 12:07, Paul Menzel wrote:
So, coreboot master with Memtest86+ Stable does *not* work. coreboot
master with Memtest86+ Master *does* work?
Correct.
The Memtest86+ stable tag was changed to v002 in coreboot 4.10 in commit
Dear Max,
Am 23.04.20 um 11:28 schrieb Max Zim:
On 23/04/2020 09:24, Paul Menzel wrote:
1. How do you build the Memtest86+ payload?
2. What version do you choose? I believe there is *Stable* and *Master*?
I just checked the box in the nconfig menu, so it should be Stable as
defined
Dear Max,
Am 22.04.20 um 23:11 schrieb Max Zim:
I discovered the issue with Memtest86+ stuck on my Thinkpad x230 on the
very first tests. Always on the same point, 52%. Every release since 4.8
works this way, coreboot 4.7 works fine. Is this a known bug?
Thank you for your report. I cannot
Dear JPT,
Am 22.04.20 um 18:20 schrieb JPT:
I successfully built coreboot for my X220.
Great. Congratulations and welcome to coreboot.
For the beginning, please write one message per problem with a
descriptive subject line.
Now I got a few questions:
- tiano and grub payloads fail
Dear Matt,
Am 09.04.20 um 23:19 schrieb Matt Judell via coreboot:
It looks like QEMU supports TPM emulation via swtpm. The KConfig
menu for the QEMU "boards" doesn't allow us to toggle TPM support as
it does for say, the Chell board. Are there any blockers that would
prevent the use of
Dear AreYouLoco,
Am 08.04.20 um 10:59 schrieb AreYouLoco?:
I am in the same situation. Same board and same controller. Still
didn't flash coreboot but I also want to make FW work with coreboot.
Could you please share your coreboot build config? Did you build
master repo?
Thanks. I am also
Dear Matt,
Am 25.03.20 um 03:36 schrieb Matt B:
Noticed someone running a GA-B75M-D3V with coreboot but that it
hadn't had a status report since 2017. I did notice that GA-B75M-D3H
is still around though with a status from may of 2019.
Is the GA-B75M-D3H supported in the latest master?
Dear coreboot folks,
I’d like to draw your attention the change-set 37762 [1].
Documentation/Intel: s5 charging applet design document
This document describes design details of s5 charging applet which we
are proposing for Intel based chromebook designs. We can take advantage
of FSP utility
Dear Kyösti,
On 2020-01-25 00:56, Kyösti Mälkki wrote:
>>
>> System *boots* with one of:
>>
>> 1. maxcpus=0 (equivalent nosmp)
>> 2. maxcpus=1
>> 3. nolapic (with e1000 warning about missing MSI-X
>>
>> System does *not* boot with one of:
>>
>> 1. maxcpus=2
>> 2. noapic
Booting with
[Your plain text email part of the mail is strangely indented.]
Dear David,
Am 01.02.20 um 19:16 schrieb dhendrix--- via coreboot:
Recently there was some unpleasant activity on Gerrit which violated
the guidelines [1] regarding respectful conduct. Unfortunately this has
directly
Dear Mogens,
Am 25.01.20 um 08:15 schrieb Mogens Jensen via coreboot:
[…]
Thanks for your help. Both the suggestions you provided made video
output work. I prefer to use the open-source libgfxinit option so I
need one blob less.
My Intense PC is now running latest coreboot, I can use the
Dear coreboot folks,
On 2019-12-15 11:54, Paul Menzel wrote:
> On the Lenovo T60 (with AMD/ATI graphics) the Linux kernel (4.9,
> 4.19, 5.3, 5.4) hangs after starting user space. As SeaBIOS, GRUB,
> payloads and FreeDOS work, I tried to limit the number of CPUs, and
> booting Linux
Dear coreboot folks,
My coreboot test S-ATA hard disk had `nosmp` on the Linux command line
configured so that Linux boots on the Lenovo T60. Now, testing this on the
AGESA board ASRock E350M1, Linux failed to detect the disk (/dev/sda), and
was unable to boot (USB and AHCI devices got error
Dear Angel,
On 2020-01-12 10:50, Angel Pons wrote:
> On Sun, Jan 12, 2020 at 1:25 AM Paul Menzel wrote:
>>
>> Dear Keith,
>>
>> Am 11.01.20 um 06:35 schrieb Keith Hui:
>>
>>> As I am still chasing how to enable SCSI termination on the board,
>&g
Dear Keith,
Am 11.01.20 um 06:35 schrieb Keith Hui:
As I am still chasing how to enable SCSI termination on the board,
Due to the conversion, please always write if that worked with romcc,
that means, a regression with C environment bootblock.
I've recompiled a few more times. Therefore I
Dear Keith,
Thank you for uploading the logs of the Asus P2B-LS to coreboot’s board
status repository [1].
asus/p2b-ls/4.11-711-gd913036e18/2020-01-05T00_12_56Z
Two notes:
1. The version in the logs unfortunately contain the *dirty* tag. Could
you run `git status` or `git diff` to
Dear coreboot folks,
For those, who have missed it, Ron was interviewed on *On the Metal* [1].
Kind regards,
Paul
[1]: https://oxide.computer/blog/on-the-metal-3-ron-minnich/
smime.p7s
Description: S/MIME Cryptographic Signature
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coreboot
Dear coreboot folks,
On the Lenovo T60 (with AMD/ATI graphics) the Linux kernel (4.9, 4.19,
5.3, 5.4) hangs after starting user space. As SeaBIOS, GRUB, payloads
and FreeDOS work, I tried to limit the number of CPUs, and booting Linux
with `nosmp` gave me a booting system. It worked with
Dear Jorge,
On 2019-12-10 10:29, Jorge Fernandez Monteagudo wrote:
>> I've been able to push a Bettong board status (commit
>> 31848f291a5f9b8ed0cf5e7c2f6651d1b56a1086)
>
> Sorry, commit edab74e8f3bddbab50fe6160da324fecf0fed329
>
> commit edab74e8f3bddbab50fe6160da324fecf0fed329
> Author:
Dear Jorge,
On 2019-11-12 15:55, Jorge Fernandez Monteagudo wrote:
>> I do not understand that sentence. Do you see anything at all on
>> the monitor before Linux starts? If so, what payload? But judging
>> from the payload size, you are using the Linux kernel payload.
>
> No, the monitor is
Dear Jorge,
On 2019-11-12 15:12, Jorge Fernandez Monteagudo wrote:
> I have a little problem trying to get a vesa framebuffer when booting my
> system.
What board with what graphics device is it?
> I have the system with the original bios and the vesa fb working. These are
> the
> relevant
Dear coreboot folks,
Those of you, who missed it in #coreb...@irc.freenode.net and do
not monitor the TianoCore bug tracker, Greg (myfreeweb) posted
instructions on how to get PS/2 working in UefiPayloadPkg [1].
Kind regards,
Paul
[1]: https://bugzilla.tianocore.org/show_bug.cgi?id=2241#c1
Dear Senthil,
On 2019-10-04 16:19, Senthil Kumar G via coreboot wrote:
> Is there any way to configure all uart of the processor. I am getting
> only one serial controller in list of lspci. Coffeelake has three
> uart ports but only one is getting listed.
Please start a separate thread by
[CC: +affected coreboot folks, +coreboot mailing list]
Dear Thomas,
More affected people discussed this issue on the coreboot mailing list [1].
On 2019-01-14 18:37, Lendacky, Thomas wrote:
> On 1/14/19 11:09 AM, Paul Menzel wrote:
>> On 01/14/19 18:00, Lendacky, Thomas wrote:
>&
Dear Jief, dear Michał,
On 25.09.19 14:39, Michal Zygowski wrote:
[…]
DVMT... this terminology is so confusing. I think it refers to the UMA
memory which is configured here for x220:
https://github.com/coreboot/coreboot/blob/master/src/northbridge/intel/sandybridge/early_init.c#L116
Also,
Dear Timothy,
On 9/2/19 10:17 AM, Timothy Pearson wrote:
> - Original Message -
>> Sent: Monday, September 2, 2019 2:56:21 AM
>
>>> What about following proposal:
>>> coreboot is an extended firmware platform that delivers a lightning
>>> fast and secure boot experience on modern
Dear Kinky,
On 7/30/19 11:18 AM, Kinky Nekoboi wrote:
> loading the microcode via Linux Kernel works.
>
> including it via coreboot causes General Protection Faults.
>
> See included bootlog.
We hit the same issue on our board, and reported it to the Linux kernel
developers [1].
Dear Martin,
First, please try to use interleaved style for quoting.
On 05.06.19 13:47, Martin Kepplinger wrote:
Am 05.06.2019 07:58 schrieb Martin Kepplinger:
I can test later but I think I can see what happens. It fixes the issue,
but still prints "ERROR: Keyboard set scancode failed!".
Dear coreboot folks,
On 06/04/19 12:15, Paul Menzel wrote:
> On 06/04/19 12:01, Paul Menzel wrote:
>
>> On 06/04/19 07:10, Martin Kepplinger wrote:
>>
>>> Just tested a build using this config:
>>> https://github.com/merge/skulls/blob/master/x230/nonfree-de
Dear Martin,
On 06/04/19 12:01, Paul Menzel wrote:
> On 06/04/19 07:10, Martin Kepplinger wrote:
>
>> Just tested a build using this config:
>> https://github.com/merge/skulls/blob/master/x230/nonfree-defconfig-139b3cef03
>> with a recent coreboot (my master bran
Dear Martin,
On 06/04/19 07:10, Martin Kepplinger wrote:
> Just tested a build using this config:
> https://github.com/merge/skulls/blob/master/x230/nonfree-defconfig-139b3cef03
> with a recent coreboot (my master branch HEAD is at 0da3a8a91b
> soc/intel/baytrail: set default VBIOS filename
Currently, the time-out is cancelled/cleared. With the commit, it is not.
With a small GRUB payload, this the problem is also reproducible on the
ASRock E350M1.
Link: http://lists.gnu.org/archive/html/grub-devel/2019-01/msg00037.html
Signed-off-by: Paul Menzel
---
grub-core/normal/menu.c | 3 ++-
1
Dear GRUB folks,
When the module `at_keyboard` is directly into the GRUB image
(`--modules`), and GRUB is loaded really quickly, then the timer, which,
after counting down to 0 (`GRUB_TIMEOUT`), starts the selected entry, is
not shown.
I noticed this issue on the ASRock E350M1 with
Dear Jay,
Am Freitag, den 23.11.2018, 19:20 -0700 schrieb Jay Talbott:
> I know I don't post much here, but I feel like I need to chime in on
> this thread... Perhaps it's time that SysPro becomes a louder voice
> in the community.
>
> Bay Trail and Broadwell DE are both still very popular
Dear Nico, dear coreboot folks,
Am Freitag, den 25.05.2018, 18:40 +0200 schrieb Nico Huber:
> On 25.05.2018 10:15, Patrick Georgi via coreboot wrote:
> > That is, who would unbearably suffer from 132 characters gper line of code?
>
> Humans. Code quality.
>
> Eyes get too tired too fast. The
Dear Patrick,
Am Mittwoch, den 16.05.2018, 17:15 +0200 schrieb Patrick Georgi:
> after just running into an issue on the EC code base, I hereby propose that
> going forward, we should always wrap conditional blocks in braces, even
> one-liners.
> That is:
>
> if (foo) {
>bar();
> }
>
>
Dear Martin,
Am Donnerstag, den 03.05.2018, 20:21 -0500 schrieb Martin Roth:
> The coreboot 4.8 release is planned for May 15. That's the day that we'll
> choose the commit to base the release on and create the release tag in
> git. The tarballs will be available on the website shortly
Dear coreboot folks,
Arthur did great work and unified and improved a lot of code under the
topic *common_smm_smihandler* [1].
To avoid regressions, could everyone with the appropriate hardware
please test [2], and comment on the change-set with the test result?
The instructions below should
Dear coreboot users,
There is some uncertainty about the state of latest coreboot on the
Lenovo X201. Does the most recent commit from coreboot work on it, or
are there problems or regressions?
Kind regards,
Paul
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Dear coreboot folks,
Looking through the board status uploads, the AMD Family 15h and 16h
uploads contain lines with *ASSERTION ERROR*. For example:
asrock/imb-a180/4.6-812-g4a1d450/2017-07-22T05_25_01Z/coreboot_console.txt:ASSERTION
ERROR: file
Dear coreboot folks,
Looking through the board status uploads, the AMD Family 15h and 16h
uploads contain lines with *ASSERTION ERROR*. For example:
asrock/imb-a180/4.6-812-g4a1d450/2017-07-22T05_25_01Z/coreboot_console.txt:ASSERTION
ERROR: file
Dear coreboot folks,
Could somebody please test if on the Asus KGPE-D16 the PS/2 keyboard
still works after resume from ACPI S3 with the change-set
*winbond/w83667hg-a: Disable mouse controller also during resume* [1]
applied?
Kind regards,
Paul
[1]
Dear Eli,
Am Montag, den 12.02.2018, 11:55 +0100 schrieb Elisenda Cuadros:
> Sure, I will be happy to do it :-)
Thank you very much for uploading the data to the board status
repository [1].
I noticed, that the serial console is enabled in your run, which causes
the boot time to be quite slow
Dear coreboot folks,
I’d be great, if you took a few minutes to upload the status of your
board to the board status repository [1].
Please make sure, that in the coreboot repository `git describe --
dirty` doesn’t return a string with *dirty* in it. Often it is caused
by changes in the
Dear coreboot folks,
TLDR; If coreboot wants to *make use of the undefined baviour sanitizer
(UBSAN)* a solution needs to be found for left shift errors like in `1
<< 31`, where the sign bit is ignored. The proposal is to adapt the
code accordingly, that means `1U << 31`, although it’s not so
Dear Timothy,
Am Samstag, den 10.02.2018, 18:32 -0600 schrieb REACTS:
> The QEMU x86_64 Q35 fails verification for branch master as of commit
> 1b64ae1119fc7891b043d5d29bf93859ef9dbfa1
>
> The following tests failed:
> BOOT_FAILURE
>
> Commits since last successful test:
> 1b64ae1
Dear Gergely, dear Elisenda,
Welcome to coreboot and thank you for making and using the port for the
Asus AM1I-A.
Could one of you, please upload the current status to the board status
repository? See the file `README` in `util/board_status/`.
Please make sure, that you build from a non-dirty
Dear coreboot folks,
Martin said, that the missing/unwritten release notes are the reason
holding up the coreboot 4.7 release.
Could the maintainers, developers, and users please jump in and help
write them. Please use the pad [1]. Some coreboot folks already
contributed. Big thank you to them.
Dear Branden,
Thank you for uploading the results for your ASUS P2-99 to the board
status repository [1].
You configured your board as below.
```
# This image was built using coreboot 4.6-2379-g0cc28d7e61
CONFIG_VENDOR_ASUS=y
CONFIG_BOARD_ASUS_P2B=y
CONFIG_DRIVERS_PS2_KEYBOARD=y
Dear Ron,
Am Montag, den 04.12.2017, 15:58 + schrieb ron minnich:
> On Mon, Dec 4, 2017 at 12:37 AM Paul Menzel wrote:
> >
> > I can’t find the mailing list. Could you please share the URL (and put
> > the list in CC)?
>
> https://groups.google.com/forum
Dear Ron,
Am Samstag, den 02.12.2017, 21:26 + schrieb ron minnich:
> Over the last few months I discussed reviving the LinuxBIOS name with a
> number of folks inside and outside the coreboot community. I still pretty
> much own the name: for old times's sake I kept the LinuxBIOS Inc.
>
Dear coreboot folks,
As you all heard of NERF [1], Heads [2] and u-root [3], they try to get
the Linux kernel into the flash ROM chip also without coreboot, by
stripping down the UEFI firmware.
Trammell is going to give a talk about it at 34C3 [4], and already uses
the word *LinuxBIOS* there,
Dear Chinmoy,
Am Donnerstag, den 16.11.2017, 17:48 +0530 schrieb chinmoy ghosh:
> I am new to coreboot.
Welcome!
> I am able to clone the coreboot and able to compile for x86 arch.
> I am not able to select any drivers in the menuconfig. I want compile some
> coreboot/src/drivers/i2c drivers.
Dear Ron,
Am Freitag, den 06.10.2017, 16:10 + schrieb ron minnich:
> 2 weeks ago I started an OCP winterfell node booting this way. This was
> NERF with linux and u-root in flash. it was about 20 seconds for a full
> cycle of linux in flash, dhclient, wget, kexec. I ran it 10,000 times, got
Dear Patrick,
Am Freitag, den 06.10.2017, 15:03 +0200 schrieb Patrick Georgi:
> 2017-10-06 9:43 GMT+02:00 Paul Menzel:
> > Having the code base compatible with future toolchains is quite
> > important and convenient in my opinion.
>
> That's a great argument to switch out t
Dear coreboot folks,
Clang 5.0 shows the warnings below. I don’t know if Clang 4.0 also
warns about these.
```
CCfirmware/lib/vboot_api_kernel.o
firmware/lib/vboot_api_kernel.c:334:26: error: taking address of packed member
'kernel_version_tpm' of class or structure
Dear Martin,
Am Dienstag, den 03.10.2017, 08:07 -0600 schrieb Martin Roth:
> I'd say that it doesn't make sense to require that coreboot builds
> with anything other than the coreboot toolchain.
> Additionally, It isn't reasonable to introduce a new requirement this
> close to the release.
Dear coreboot folks,
A friend gave me four (old) systems, but I do not need them. All have a
CPU plugged in, but no memory. If you would like some of them, please
tell me. Otherwise, I’ll throw them away.
1. Asus M2A-VM (patch for coreboot v2 from Carl-Daniel exists in the
mailing list
Dear coreboot folks,
It’s October and coreboot 4.7 is supposed to be tagged in this month.
Are there more specific plans already, when the release will happen?
Thanks,
Paul
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Dear coreboot folks,
I’d like to inform you that the schedule for the European coreboot
conference was published and the speakers were announced [1].
A big thanks to everybody sending in proposals and to the program
committee.
Now, please spread the word, buy tickets, and plan your trip. I am
Dear coreboot folks,
Am Mittwoch, den 20.09.2017, 08:17 +0200 schrieb Paul Menzel:
> I’d like to propose the following goal for the upcoming coreboot 4.7
> release.
>
> All boards have to build with GCC 7.2 [1] and IASL 20170831 [2].
>
> For the latter, several Intel board
Dear coreboot folks,
Do you have any suggestions on how to get an efficient development
setup for Google Chromebooks, which I’d describe as laptops with
soldered flash ROM chip. In my case, it’s a Medion AKOYA S2013
(google/veyron_jaq), and an Acer Chromebook R 13 (google/elm).
I have access to
Dear Shaunak,
First, please just send plain text messages to mailing lists.
Am Montag, den 25.09.2017, 19:36 -0700 schrieb shaunak saha:
> I started seeing this issue today and was unable to fetch commits from
> coreboot server.
Please also provide the output of `LANG=C git fetch -vv
Dear 17299,
Am Montag, den 25.09.2017, 20:37 -0400 schrieb One7two99 via coreboot:
> Original Message
> Subject: Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot
> Screen
> Local Time: 25 September 2017 9:17 AM
> From: paulepan...@users.sourceforge.net
>
> >
Dear 17299,
First, please just sent plain text messages to mailing lists.
Am Sonntag, den 24.09.2017, 17:32 -0400 schrieb One7two99 via coreboot:
> Booting to my Grub Selection screen takes ~12sec on my X230, loosing lots of
> second from pressing the Power Button to the "Hit Escape Key"
Dear coreboot folks,
The European coreboot conference 2017 is around the corner and starts
on October 26th [1].
Are there developers who need funding of their travel costs? Kyösti,
Arthur, Patrick, …? Please tell the community and note the amount.
Until we know for sure, it’d be great if the
Dear coreboot folks,
I’d like to propose the following goal for the upcoming coreboot 4.7
release.
All boards have to build with GCC 7.2 [1] and IASL 20170831 [2].
For the latter, several Intel boards fail to build [3]. It’d be great
if the maintainers looked into it.
Thanks,
Paul
[1]
Dear coreboot users,
Keith is doing a tremendous job adding support for early CBMEM to
boards with the Intel 440BX chipset [1]. Understandably, he can only do
tests on the few boards he has access to, so it’s up to us, the
community, to do the tests on the other boards on upload the results to
Dear coreboot folks,
Am Mittwoch, den 23.08.2017, 20:42 -0600 schrieb Aaron Durbin:
> On Wed, Aug 23, 2017 at 8:31 PM, Kyösti Mälkki
> wrote:
> > On Thu, Aug 24, 2017 at 12:29 AM, Taiidan at gmx.com
> > wrote:
> > > Ah I see thanks for explaining.
> > >
> > > I had read all the AGESA boards
Dear Ian,
Am Samstag, den 09.09.2017, 16:31 -0700 schrieb Ian Kelling:
[…]
> 2. built from git master (588ccaa9),
That commit is from April, isn’t it. So it’s pretty outdated.
> crossgcc without -b this time as the build didn't complain about it.
> SeaBIOS doesn't detect my hard drive. I
Dear Ian,
Welcome to coreboot!
Am Samstag, den 09.09.2017, 16:31 -0700 schrieb Ian Kelling:
> 1. building 4.6 gives build erro
>
> $ make crossgcc-x64 BUILDGCC_OPTIONS=-b CPUS=16
> $ make
> […]
> HOSTCC cbfstool/lz4hc.o
> HOSTCC cbfstool/lz4frame.o
>
Dear Paul,
Am Donnerstag, den 31.08.2017, 09:36 +0300 schrieb Paul Kocialkowski:
> Le jeudi 31 août 2017 à 09:30 +0300, Paul Kocialkowski a écrit :
> > Le jeudi 31 août 2017 à 08:13 +0200, Paul Menzel a écrit :
> > > I haven’t tested this yet with a 64-bit userspace, but assum
Dear coreboot folks,
Trying to run `make test-abuild` on my system with a 32-bit userspace,
it looks like quite some boards require the program futility from
`util/futility`, but that fails to build with the error below.
```
/dev/shm/coreboot/util/futility(master) $ git describe
Dear coreboot folks,
Thanks to Nico’s introduction of “timeless”/“comparable” builds in
commit 566dd357 (Add option for "timeless" builds) [1], it’s for
example possible to find out, if a commit changed something for a
certain board.
> Builds with BUILD_TIMELESS=1 shall always give a bit
Dear coreboot folks,
As some of us still use Intel 945 devices, this is a heads-up, that the
Linux Intel graphics driver was cleaned up in Linux 4.13 [1], whose
first release candidate was published yesterday.
There was at least one regression [2], so I encourage everyone to test
the Linux 4.13
Dear coreboot administrators,
Currently, I am unable to fetch the newest commits/objects(?) from the
coreboot git server.
```
$ LANG=C git fetch -vv origin
[…]
have ccbaabe5cf6b7eaa20fc323858680a404383537b
got ack 3 dee643a360ad75787f2982a013c62a4d49352121
got ack 3
Dear Keith,
Am Sonntag, den 09.07.2017, 10:38 +0200 schrieb Paul Menzel:
> Am Freitag, den 07.07.2017, 21:55 -0400 schrieb Keith Hui:
> > My original question got lost in the list probably because of a bad
> > subject, so I'm asking again with a better one.
>
> Indeed
Dear Keith,
Am Freitag, den 07.07.2017, 21:55 -0400 schrieb Keith Hui:
> Hi (again) coreboot:
Welcome back!
> My original question got lost in the list probably because of a bad
> subject, so I'm asking again with a better one.
Indeed, a good, descriptive subject line is useful.
> I read
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