Yep.. the permissions were wrong. Give it a try now.
Ali
> On Nov 2, 2017, at 5:54 PM, Gabe Black wrote:
>
> I think I saw an email from Ali recently that he updated the wiki? Maybe it
> has something to do with that? Maybe some file or directory permissions
> were
The wiki has been updated to the latest version of mediawiki. Everything
appears to be working, but if you run into issues please let me know.
Ali
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It’s been fixed, sorry about that.
Ali
> On Apr 27, 2017, at 8:21 AM, Ali Saidi <gem5@overt.org> wrote:
>
> I upgraded the wiki about a week ago to address some security issues and
> something much have gone wrong, I’ll take a look at what is happening.
>
> A
I upgraded the wiki about a week ago to address some security issues and
something much have gone wrong, I’ll take a look at what is happening.
Ali
> On Apr 27, 2017, at 5:53 AM, Andreas Sandberg
> wrote:
>
> I had a quick look at the MediaWiki config and it seems
988>
I like Andreas' comments, but actually I don't think the original is
negative either. Andreas 1,2 is probably a good reason to do it and the current
1,2 are the carrots of why you should.
- Ali Saidi
On Feb. 21, 2017, 5:34 p.m., Jason Lowe-Power
688/#comment7787>
Both Linux and Tru64 use the same callpal to trigger a system call.
- Ali Saidi
On Oct. 27, 2016, 7:45 a.m., Andreas Hansson wrote:
>
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> On Nov. 2, 2016, 7:38 p.m., Alec Roelke wrote:
> > This doesn't work with the O3 CPU model; I wrote a simple program that
> > performs a lr.w followed by sc.w that works with the atomic-simple,
> > timing-simple, and minor CPU models, but with the O3 model I get this error:
> >
> >
Hi Everyone,
The wiki has just been upgraded. Please let us know if there are any problems.
Thanks,
Ali
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> On Nov. 25, 2015, 6:42 p.m., Andreas Hansson wrote:
> > Traditionally, it's not reset, as it accounting for all instructions
> > executed. Perhaps hostSeconds shouldn't be reset as well and then the
> > calculation would be correct? sim_insts isn't supposed to be used for
> > anything other
ng, we probably shouldn't repeat it
here.
- Ali Saidi
On Nov. 19, 2015, 5:44 p.m., Curtis Dunham wrote:
>
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On Nov. 7, 2015, 9:22 p.m., Palle
> On Oct. 12, 2015, 4:58 p.m., Nilay Vaish wrote:
> > Can you explain why it is no longer necessary?
>
> Curtis Dunham wrote:
> Empirically, all regressions still pass. :-)
>
> It might be easier to explain why it was ever necessary, which is
> definitely before my time with gem5.
> On Sep 4, 2015, at 12:54 PM, Steve Reinhardt wrote:
>
> To answer Jason's question: it would be nice to have an automation system
> where someone with sufficient permissions could just click on a patch on
> reviewboard and the patch would automatically be committed; with
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On Aug. 12, 2015, 9:19 p.m., Brandon
Much like the comment says, the virtual memory layer in the operating system
lazily allocates pages. If they're zero they'll get lazily allocated so there
isn't any reason for us to use up a lot of extra system memory storing 0s.
Ali
Sent from my ARM powered mobile device
On Aug 12, 2015, at
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On April 24, 2015, 5:45 p.m., Ruslan
if(!FreeBSD) is added to a few of the lines?
Thanks Ruslan. This is getting a lot closer, and it will be great to have
FreeBSD support in gem5. I have a couple questions above about code duplication
between FreeBSD/Linux.
Thanks again,
Ali
- Ali Saidi
On April 19, 2015, 10:12 a.m., Ruslan Bukin wrote
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On April 9, 2015, 9:29 a.m., Ruslan
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On April 9, 2015, 9:07 a.m., Ruslan
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On April 9, 2015, 9:37 a.m., Ruslan
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On April 9, 2015, 9:51 a.m., Ruslan
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On April 9, 2015, 4:42 p.m., Ruslan Bukin wrote
On April 9, 2015, 6:06 p.m., Ali Saidi wrote:
Sorry, my comments disappeared somewhere.
Does this change allow for gem5 to compile on FreeBSD? gem5 to run a FreeBSD
binary? Both?
If it's the prior, it would be good to allow any type of binary to run on any
host OS. If it's the latter, I
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On March 27, 2015, 2 p.m., Ruslan
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Thanks for the change!
- Ali Saidi
On March 25, 2015, 11:10
Hi Marcus,
Option 1 is probably the most preferred route as the code is much more
likely to say in-sync and compatible if it¹s in the same repository and
tested along side gem5. The best way to proceed with that option is to
post your patches to the gem5 review board http://reviews.gem5.org. If
.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include cpu/inst_pb_trace.hh
+
+#include base/callback.hh
+#include base/output.hh
+#include config/the_isa.hh
+#include cpu/static_inst.hh
+#include cpu/thread_context.hh
+#include debug/ExecEnable.hh
+#include params/InstPBTrace.hh
+#include proto/inst.pb.h
changeset 61a0b02aa800 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=61a0b02aa800
description:
cpu: Remove all notion that we know when the cpu is misspeculating.
We have no way of knowing if a CPU model is on the wrong path with
our
changeset 3c42be107634 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3c42be107634
description:
arm: always set the IsFirstMicroop flag
While the IsFirstMicroop flag exists it was only occasionally used in
the ARM
instructions that gem5 microOps and
changeset aef704eaedd2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aef704eaedd2
description:
sim: Clean up InstRecord
Track memory size and flags as well as add some comments and consts.
diffstat:
src/cpu/base_dyn_inst.hh| 10 +-
changeset fae54a666162 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fae54a666162
description:
cpu: Put all CPU instruction tracers in a single file
diffstat:
src/arch/arm/ArmNativeTrace.py | 2 +-
src/arch/sparc/SparcNativeTrace.py | 2 +-
changeset c3fd4c020e49 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c3fd4c020e49
description:
cpu: remove legion tracer
If someone wants to debug with legion again they can restore the
code from the repository, but no need to have it hang around
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On Jan. 14, 2015, 6:13 p.m., Nikos
That is doable. You can created checkpoints, there is just no way to
instrument every basic-block.
Ali
On 1/13/15, 3:13 PM, mike upton via gem5-dev gem5-dev@gem5.org wrote:
Oh, Bummer.
I was hoping to be able to get simpoints out of a KvmCPU run.
It seems like that is not possible.
Is it
It should probably be /usr/bin/env python
Ali
On 1/9/15, 1:12 PM, mike upton via gem5-dev gem5-dev@gem5.org wrote:
OK, thanks.
I don't understand what is going on, but blindly following the suggestion
made it work.
I needed to do:
python /usr/bin/scons gem5 options
Oh, I see what is going
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On July 24, 2014, 7:44 p.m., Anthony
are the
other files?
- Ali Saidi
On Dec. 17, 2014, 7:08 a.m., Gabe Black wrote:
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On Dec. 26, 2014, 9:32 p.m., Gabe
- Ali Saidi
On Dec. 17, 2014, 7:35 a.m., Gabe Black wrote:
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Seems fine... Anyone who deals with Ruby OK?
- Ali Saidi
The in-order cpu model is deprecated and will soon be removed from the tree. Id
you'd like an in order cpu model use the minor cpu model which supports ARM.
Ali
Sent from my ARM powered mobile device
On Dec 17, 2014, at 2:18 PM, Anastasiia via gem5-dev gem5-dev@gem5.org
wrote:
Hi,
/2558/diff/
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/cpu/CPUTracers.py PRE-CREATION
src/cpu/ExeTracer.py 4e09ae443c96
src/cpu/IntelTrace.py 4e09ae443c96
src/cpu/NativeTrace.py 4e09ae443c96
src/cpu/SConscript 4e09ae443c96
Diff: http://reviews.gem5.org/r/2559/diff/
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/
Testing
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/minor/lsq.cc 4e09ae443c96
src/cpu/simple/atomic.cc 4e09ae443c96
src/cpu/simple/timing.cc 4e09ae443c96
src/sim/insttracer.hh 4e09ae443c96
Diff: http://reviews.gem5.org/r/2561/diff/
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src/arch/arm/isa/templates/mem.isa 4e09ae443c96
src/arch/arm/isa/templates/mem64.isa 4e09ae443c96
src/cpu/static_inst.hh 4e09ae443c96
Diff: http://reviews.gem5.org/r/2562/diff/
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src/proto/inst.proto PRE-CREATION
util/decode_inst_trace.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2563/diff/
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I think it’s fine that a device wants to do this, I’d just like it to use an
thin interface on the System object as a matter of clean interfaces in the
object hierarchy, so unrelated objects don’t have to know about each other.
Ali
On Dec 3, 2014, at 11:54 AM, Gabe Black via gem5-dev
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On Dec. 5, 2014, 10 a.m., Gabe Black
/#comment5044
can these be doxygen comment? (e.g. /// or /***
one minor request, no need to repost
- Ali Saidi
On Dec. 5, 2014, 10:36 a.m., Gabe Black wrote:
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but I haven't had a
chance to actually test it yet.
- Ali Saidi
On Dec. 5, 2014, 11:15 a.m., Gabe Black wrote:
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On Dec. 3, 2014, 7:10 p.m., mike upton
Hi Gabe/Steve,
As Steve mentioned I¹ve been working on a new take on the regression
system in my spare-time.
I want to get it a bit more complete before I show it to the world, but
some of the goals I set out with align with yours.
In particular I¹m targeting the following:
(1) Success/Failure
On Dec. 4, 2014, 3:03 p.m., Nilay Vaish wrote:
src/sim/syscall_emul.hh, line 201
http://reviews.gem5.org/r/2548/diff/1/?file=42865#file42865line201
How will the compiler choose between the two versions of unlinkFunc? I
think we should either drop the default argument or drop the
daystrom is very low on ram at the moment with the various services we’re
running. We have a new machine that has substantially more ram that we’ll be
switching to in the near term which should address the issue. For the moment
I’ve restarted tomcat and it seems to be working.
Ali
On Nov 28,
There are functions that correspond to this functionality although they’re
poorly named for the purpose, but memWriteback() - beginning of KVM
simulation; memInvalidate - end of KVM simulation. Another option would be to
check for the memory time atomic_noncaching which I believe only KVM uses.
On Nov 26, 2014, at 12:11 PM, Steve Reinhardt via gem5-dev gem5-dev@gem5.org
wrote:
On Wed, Nov 26, 2014 at 4:30 AM, Gabe Black via gem5-dev gem5-dev@gem5.org
wrote:
Just to make sure we're all on the same page, I removed the spaces here
because these are default values for arguments.
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On Nov. 22, 2014, 1:36 p.m., Gabe
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On Nov. 22, 2014, 11:39 a.m., Gabe
On Nov. 25, 2014, 10:02 p.m., Nilay Vaish wrote:
configs/common/Options.py, line 155
http://reviews.gem5.org/r/2516/diff/1/?file=42704#file42704line155
Can you explain why we need this separate option for restoring from a
checkpoint taken using the take-simpoint-checkpoints?
The
Looking at the code it looks like it would be possible for there to be 12
bytes in the socket, so the read will return less that 12 bytes (because
you got very unlucky and the bytes were split across two packets).
Looking at the code fixing that assumption will be a bit of a pain.
Ali
On
What compiler and version are you using?
Ali
On 11/17/14, 2:37 PM, Urmish Ajit Thakker via gem5-dev
gem5-dev@gem5.org wrote:
Hi,
I pulled up the latest copy of gem5 and got the following error while
building gem5.fast.
build/ARM/proto/protoio.fo (symbol from plugin): warning: memset used
be used in case !USE_KVM, but as you
allude to this is very ugly.
Off the top of my head the way I'd prefer to see it done is let objects
register ranges with the System object and then the KVM code could iterate that
list if it was compiled in. Sound reasonable?
- Ali Saidi
On Nov. 18, 2014, 2:27
changeset d1dce0b728b6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1dce0b728b6
description:
arm: Fix timing wakeup with LLSC
diffstat:
src/cpu/simple/timing.cc | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diffs (29 lines):
diff -r
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On Nov. 10, 2014, 5:20 p.m., Andrew
would need to
comment on the other one.
- Ali Saidi
On Nov. 7, 2014, 9:35 p.m., Alberto Javier Naranjo Carmona wrote:
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or
some other checkpoint restore functionality for X86.
Ali Saidi wrote:
I assume it's working for you without restoring from checkpoints?
The code looks like state is being restored, but we've only ever tested
it with ARM although I'm not sure why there would be a difference
On Nov. 6, 2014, 7:48 p.m., Cagdas Dirik wrote:
This patch seems to be broken for X86 when restoring from checkpoints. A
sample test crashes with segmentation fault. Here are the steps:
0. Sample test program does int array manipulation and creates a checkpoint
before computation.
changeset ba51f8572571 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ba51f8572571
description:
tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
diffstat:
These should now be fixed.
Thanks,
Ali
On 11/2/14, 3:20 PM, Cron Daemon via gem5-dev gem5-dev@gem5.org wrote:
*
build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-a
tomic CHANGED!
*
build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
CHANGED!
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On Oct. 29, 2014, 3:01 p.m., Andrew
changeset aa46a8ae3487 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa46a8ae3487
description:
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
changeset aa23216161fa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa23216161fa
description:
arm: Mark some miscregs (timer counter) registers at unverifiable.
The checker can't verify timer registers, so it should just grab the
version
from the
changeset 38c7a9ea7729 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=38c7a9ea7729
description:
cpu: Add support to checker for CACHE_BLOCK_ZERO commands.
The checker didn't know how to properly validate these new commands.
diffstat:
changeset d5554f97c451 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d5554f97c451
description:
arm, mem: Fix drain bug and provide drain prints for more components.
diffstat:
src/arch/arm/table_walker.cc | 5 ++---
src/mem/cache/mshr_queue.cc | 3 +++
changeset b423e1d0735e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b423e1d0735e
description:
arm, tests: Update config files to more recent kernels and create
64-bit regressions.
This changes the default ARM system to a Versatile Express-like system
changeset 2b416ef3b400 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2b416ef3b400
description:
automated merge
diffstat:
src/arch/alpha/linux/process.cc |4 +-
src/arch/arm/linux/process.cc|4 +-
src/arch/mips/linux/process.cc |4 +-
changeset f33fab6214c4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f33fab6214c4
description:
arm: fix bare-metal memory setup.
The bare-metal configuration option still configured memory with the
old scheme
that no-longer works. This change
changeset ca4438b6e39a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ca4438b6e39a
description:
tests: Update regressions for the new kernels and various preceeding
fixes.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
changeset bd7c2aa12122 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bd7c2aa12122
description:
arm, tests: Add 64-bit ARM regression tests
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
| 2431 +++
changeset cae494887847 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cae494887847
description:
arm, tests: Forgot the system.terminal files for the new regressions.
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
it
supposed to be in there. otherwise I think it's good to go.
src/mem/ruby/system/RubyMemoryControl.cc
http://reviews.gem5.org/r/2468/#comment4911
is this change supposed to be in here?
- Ali Saidi
On Oct. 26, 2014, 5:16 p.m., Alberto Javier Naranjo Carmona wrote
I'm not sure which version of gem5 you're using, but in the latest dev
repository it looks like this if block is completely gone. I'm not sure if that
is because the check has been moved elsewhere or otherwise.
- Ali Saidi
On Oct. 26, 2014, 5:16 p.m., Alberto Javier Naranjo Carmona
If you have a chance to test the dev repository that would be great.
- Ali Saidi
On Oct. 26, 2014, 5:16 p.m., Alberto Javier Naranjo Carmona wrote:
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Hi Everyone,
We've noticed an issue with the WriteInvalidate patch where the cpu
reads or writes the same cache line that is being write invalidated.
We're working on a fix and hope to have it out next week. If not we'll
disable the code for the time being.
Thanks,
Ali
space. This change
allows the extended PCI config space to be accessed by
sysfs properly.
Diffs
-
src/dev/pcidev.hh d96740732a61
src/dev/pcidev.cc d96740732a61
src/dev/pcireg.h d96740732a61
Diff: http://reviews.gem5.org/r/2463/diff/
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On Sept. 23, 2014, 7:46 p.m., Steve
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On Sept. 23, 2014, 7:47 p.m., Steve
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On Sept. 23, 2014, 7:47 p.m., Steve
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On Sept. 15, 2014, 6:29 p.m., Andrew
On Sept. 15, 2014, 8:34 p.m., Ali Saidi wrote:
Ship It!
Thanks for making the change Andrew.
Ali
- Ali
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of the PQ
(e.g. std::priority_queueunsigned, vectorunsigned, std::greaterunsigned
PQ) which will sort it the other way. I think that would be a bit clearer than
the multiplication by -1.
Ali
- Ali Saidi
On Sept. 10, 2014, 7:09 p.m., Andrew Lukefahr wrote
changeset 1aff1376921e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1aff1376921e
description:
arm: Assume we have a kernel that supports pci devices
Change the default kernel for AArch64 and since it supports PCI devices
remove the hack that made
changeset 1e2f39859382 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1e2f39859382
description:
dev: seperate legacy io offsets from PCI offset
The PC platform has a single IO range that is used both legacy IO and
PCI IO
while other platforms may
changeset 644b615fbe6a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=644b615fbe6a
description:
arm: Support 2GB of memory for AArch64 systems
diffstat:
configs/common/FSConfig.py | 27 +++
src/dev/arm/RealView.py| 9 +
2
changeset 198dfef33403 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=198dfef33403
description:
dev, arm: Add support for linux generic pci host driver
This change adds support for a generic pci host bus driver that
has been included in recent Linux
of this? I personally prefer keeping a buffer of about 2-3 months
between gem5-dev and gem5-stable.
--
Nilay
On Tue, 19 Aug 2014, Ali Saidi via gem5-dev wrote:
Looking through the change sets between now and 10231 there are a number
of compiler and bug fixes along with a few big changes
A patch would absolutely be welcomed. AArch32 mode still exists and gdb
should still work for 32-bit code. This was just an oversight. To be
clear gem5 will support ARMv8 going forward but we plan to support both
AArch32 and AArch64 code.
Thanks,
Ali
On 19.08.2014 18:19, Anthony Gutierrez
Looking through the change sets between now and 10231 there are a number
of compiler and bug fixes along with a few big changes. I think the big
changes are quite contained, so I'd be in favor for making changeset
10283 79fde1c67ed8 the new stable if others were ok with that.
Ali
On
for extract set?
otherwise ship it
- Ali Saidi
On July 21, 2014, 6:45 p.m., Anthony Gutierrez wrote:
---
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http://reviews.gem5.org/r/2167
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