Re: [gem5-dev] Removing ExtMachInst concept

eliminating ExtMachInst vs. just defining > ExtMachInst == MachInst for that ISA? > > Steve > > On Wed, Feb 11, 2015 at 4:52 PM, Gabe Black via gem5-dev < > gem5-dev@gem5.org> > wrote: > > > I'd like to remove the ExtMachInst concept from gem5, or

[gem5-dev] Removing ExtMachInst concept

I'd like to remove the ExtMachInst concept from gem5, or at least hide it within the ISAs that need it. The only place where it isn't obvious how to do that is in the "Minor" cpu where it treats the ExtMachInst as a 64 bit integer (!) and masks it against a bit mask (!) to see when certain addition

Re: [gem5-dev] Review Request 2642: syscall_emul: fix warning with wrong syscall name and nix extra whitespace

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2642/#review5862 --- Ship it! Ship It! - Gabe Black On Feb. 6, 2015, 10:07 p.m., Brandon P

Re: [gem5-dev] Decoding using decoder state

I realize the context for this might not be something everybody is familiar with. If you need me to explain what this is about more I can do that. Gabe On Wed, Feb 4, 2015 at 2:23 PM, Gabe Black wrote: > In the x86 decoder, some architectural state (CPU mode, a couple other > things) is used to

[gem5-dev] Decoding using decoder state

In the x86 decoder, some architectural state (CPU mode, a couple other things) is used to pick an active decode cache from a hash map of caches. That state could then be used when decoding instructions since we'd still always get the same thing for a particular ExtMachInst given a particular cache.

[gem5-dev] fxsave and fxrstor assume 64 bit mode

I just noticed that the fxsave and fxrstor implementations Andreas did (going by the copyright header in the file) incorrectly assume that the CPU is in 64 bit mode and save XMM8-15 unconditionally. I'll likely put together a patch to fix that, but I wanted to mention it here so it didn't slip into

Re: [gem5-dev] windows fs boot and simulation

; something that you'd be far less likely to be able to contribute back to > the public code base). > > Steve > > On Thu, Jan 29, 2015 at 1:38 AM, Gabe Black via gem5-dev < > gem5-dev@gem5.org> > wrote: > > > Hi Mike. When we boot Linux on gem5, the simulato

Re: [gem5-dev] windows fs boot and simulation

Hi Mike. When we boot Linux on gem5, the simulator acts as the bootloader. It unpacks the kernel, provides various tables in memory that would normally be provided by the BIOS/firmware, does some setup of machine state, and then jumps to the kernel. On a real system, the components that get you to

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

> On Jan. 21, 2015, 9:22 p.m., mike upton wrote: > > src/arch/x86/process.cc, lines 218-237 > > > > > > For AMD systems, the sys descriptors need to come first. On intel > > systems they need to come second. > > > >

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

> On Jan. 21, 2015, 9:22 p.m., mike upton wrote: > > src/arch/x86/process.cc, lines 218-237 > > > > > > For AMD systems, the sys descriptors need to come first. On intel > > systems they need to come second. > > > >

Re: [gem5-dev] Bug With Thread Suspend Instructions, Interrupts, x86 O3 CPU?

It sounds like a bug/race condition in the O3 CPU, which I think you already knew. You could try moving the suspend call into a fault returned by the MicroHalt microop instead of the instruction itself. That might break the race, although it's not really fixing the issue with O3. Gabe On Tue, Jan

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

> On Jan. 16, 2015, 11:56 p.m., mike upton wrote: > > src/arch/x86/process.cc, lines 212-213 > > > > > > when limitHigh and limitLow get set by dataSegDesc(), it seems that > > limitHigh and limitLow get reversed. > > This

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

> On Jan. 16, 2015, 11:28 p.m., mike upton wrote: > > src/arch/x86/utility.hh, line 219 > > > > > > Is there a reason the desc.l does not get set for the dataSegDesc()? > > code sets p,l,d,g,s. Yes. The long mode bit only

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

> On Jan. 16, 2015, 12:44 a.m., mike upton wrote: > > src/arch/x86/regs/misc.hh, line 922 > > > > > > really <32, 0> in the new code? Yeah, I think that should be 31, 0 - Gabe ---

Re: [gem5-dev] Review Request 2604: cpu: commit probe notification on every microop or macroop

> On Jan. 14, 2015, 8:52 p.m., Gabe Black wrote: > > This will break GDB single stepping. > > Nikos Nikoleris wrote: > If I undestand correctly, it won't be affected. When set, the GDB single > step schedules the corresponding event at the comInstEventQueue. The > comInstEventQueue service

Re: [gem5-dev] Review Request 2604: cpu: commit probe notification on every microop or macroop

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2604/#review5755 --- This will break GDB single stepping. - Gabe Black On Jan. 14, 2015, 6:

Re: [gem5-dev] Review Request 2546: scons: Avoid implicit command dependencies

> On Jan. 13, 2015, 10:53 p.m., Andreas Hansson wrote: > > I suspect I am the only one annoyed by this...unless someone else feels the > > same I will discard the patch. If this is what I think it is, it can be pretty annoying when running regressions. The param stuff swamps the console and it

Re: [gem5-dev] SMT with x86

t0 must always return 0, and writes to it must always be ignored (or overwritten before the next instruction). You're corrupted program counter might be because you're using physical registers which aren't actually there, accessing beyond the end of an array and reading/writing something random. T

Re: [gem5-dev] Review Request 2553: dev: Prevent intel 8254 timer events firing before startup

Unless you're using the KVM CPU or human input (neither should be true for regressions), gem5 is supposed to be entirely deterministic. If you're worried about last nights regressions, the x86 problem was because I pushed a CPUID related change but hadn't generated a stats CL to go with it. While I

[gem5-dev] changeset in gem5: test: Add a unittest for the BitUnion types.

changeset 04923a93f2b5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=04923a93f2b5 description: test: Add a unittest for the BitUnion types. diffstat: src/unittest/SConscript |1 + src/unittest/bituniontest.cc | 182 +++

[gem5-dev] changeset in gem5: base: Fix assigning between identical bitfields.

changeset edbc52a43cd8 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=edbc52a43cd8 description: base: Fix assigning between identical bitfields. If two bitfields are of the same type, also implying that they have the same first and last bit positions

[gem5-dev] changeset in gem5: stats: x86: Update stats for the CPUID change.

changeset 469cf1ea40f5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=469cf1ea40f5 description: stats: x86: Update stats for the CPUID change. diffstat: tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini | 6 + tests/long/fs/

[gem5-dev] changeset in gem5: x86: Enable three bits in the FamilyModelStep...

changeset 5d119a460f15 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5d119a460f15 description: x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield. These are for the monitor/mwait instructions, SSSE3, and XSAVE. diffstat: src/arch/x86/cpu

[gem5-dev] changeset in gem5: cpuid, x86: Revert "Enabling more features in...

changeset e9bc4cde5d8e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e9bc4cde5d8e description: cpuid, x86: Revert "Enabling more features in CPUid" That change enables CPUID bits for features that aren't implemented in gem5. If a simulated system tr

Re: [gem5-dev] Review Request 2595: x86: Delay X86 table walk on receiving walker response

On Jan. 5, 2015, 10:48 p.m., Andreas Hansson wrote: > > Can you explain the sequence of events that result in bad behavior? If > > possible (which is not necessarily the case), it would be best to fix this > > without adding arbitrary delays. > > Andreas Hansson wrote: > The crossbar is pr

Re: [gem5-dev] Review Request 2590: cpuid, x86: Revert "Enabling more features in CPUid"

> On Jan. 6, 2015, 7:21 p.m., Steve Reinhardt wrote: > > Can you be more specific about what doesn't work? Do we really need to > > back out all of the enabled features? > > > > Also, it would be nice to replace the comments with different comments, > > rather than just getting rid of them.

Re: [gem5-dev] Review Request 2595: x86: Delay X86 table walk on receiving walker response

On Jan. 5, 2015, 10:48 p.m., Andreas Hansson wrote: > > Can you explain the sequence of events that result in bad behavior? If > > possible (which is not necessarily the case), it would be best to fix this > > without adding arbitrary delays. > > Andreas Hansson wrote: > The crossbar is pr

Re: [gem5-dev] bitunion and unittest CLs (and broken unittest)

Hey folks. Hopefully you're back from various holidays now. Ali reviewed my bitunion unit test, but the actual fix still needs to be reviewed, as does my fix for the circletest uinttest. cprintftest still doesn't compile. Gabe On Wed, Dec 24, 2014 at 4:47 PM, Gabe Black wrote: > I'm still waiti

Re: [gem5-dev] Review Request 2595: x86: Delay X86 table walk on receiving walker response

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2595/#review5724 --- src/arch/x86/pagetable_walker.cc

Re: [gem5-dev] Review Request 2585: test: Add a unittest for the BitUnion types.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2585/ --- (Updated Dec. 26, 2014, 9:32 p.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2511/ --- (Updated Dec. 25, 2014, 1:11 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.

> On Dec. 23, 2014, 10:25 a.m., Andreas Hansson wrote: > > Looks fine. Could you mark the issues that are fixed as fixed (or dropped > > for that matter)? > > > > Thanks. > > > > I am still not sure if I like the USE_KVM better, or perhaps having a > > NullKvm object. Yeah. There was one oth

[gem5-dev] bitunion and unittest CLs (and broken unittest)

I'm still waiting for reviews on my bituion fix, unittest, and my fix compilation fix for the circletest unittest. Also the cprintftest unittest still won't compile, unless someone slipped in a fix while I wasn't looking. I think that's likely from a change Andreas did changing how varargs are imp

Re: [gem5-dev] Review Request 2590: cpuid, x86: Revert "Enabling more features in CPUid"

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2590/#review5712 --- bump - Gabe Black On Dec. 23, 2014, 12:37 a.m., Gabe Black wrote: > >

Re: [gem5-dev] Review Request 2593: syscall emulation: Return correct writev value

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2593/#review5710 --- Ship it! Ship It! - Gabe Black On Dec. 23, 2014, 2:51 p.m., Joel Hest

Re: [gem5-dev] Review Request 2591: x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield.

> On Dec. 23, 2014, 5:19 a.m., Steve Reinhardt wrote: > > Fine with me, assuming that our implementations of those features are > > indeed complete. They aren't, but I think the bits that are missing will trigger warnings. - Gabe --- T

Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2511/ --- (Updated Dec. 23, 2014, 1:04 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.

> On Dec. 18, 2014, 10:39 a.m., Gabe Black wrote: > > src/dev/cirrus.hh, line 48 > > > > > > They probably shouldn't be. I'll fix that. These default to private, but I'll make that explicit. - Gabe --

Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2511/ --- (Updated Dec. 23, 2014, 12:55 a.m.) Review request for Default. Repository: gem5

[gem5-dev] changeset in gem5: scons: Make the USE_KVM variable available in...

changeset b3ea7444f466 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b3ea7444f466 description: scons: Make the USE_KVM variable available in C++. We need it to determine whether we should expect KVM related parameters exist in the cirrus graphics dev

[gem5-dev] Review Request 2591: x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2591/ --- Review request for Default. Repository: gem5 Description --- Changeset 10608

[gem5-dev] Review Request 2590: cpuid, x86: Revert "Enabling more features in CPUid"

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2590/ --- Review request for Default. Repository: gem5 Description --- Changeset 10607

Re: [gem5-dev] Improved regression categorisation

I mean quick, medium, slow, not quick, medium, fast. On Mon, Dec 22, 2014 at 12:44 PM, Gabe Black wrote: > I complained about those names a long time ago, and I still think they > aren't very good. "quick" and "long" aren't really on the same scale, to > start with. Something can be quick (a rat

Re: [gem5-dev] Improved regression categorisation

I complained about those names a long time ago, and I still think they aren't very good. "quick" and "long" aren't really on the same scale, to start with. Something can be quick (a rate) and still take a long time. Medium is very generic and so isn't on a different axis, but since the others aren'

Re: [gem5-dev] Review Request 2565: arm: Clean up and document decoder API

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2565/#review5703 --- I added a comment to this review, but since the issue had been marked res

Re: [gem5-dev] Review Request 2588: tests: Remove deprecated InOrderCPU tests

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2588/#review5699 --- Ship it! Ship It! - Gabe Black On Dec. 19, 2014, 1:18 p.m., Andreas H

Re: [gem5-dev] Review Request 2589: scons: Do not build the InOrderCPU

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2589/#review5698 --- Ship it! Ship It! - Gabe Black On Dec. 19, 2014, 1:20 p.m., Andreas H

Re: [gem5-dev] Review Request 2518: x86: i8042: Add VNC mouse support, and flesh out the mouse model.

> On Dec. 17, 2014, 1:53 p.m., Andreas Hansson wrote: > > src/dev/x86/i8042.hh, line 118 > > > > > > I know it is not changed, but could you elaborate on the unit? I'll have to look at it again to figure out what the unit i

Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2511/#review5696 --- src/dev/Cirrus.py Rem

[gem5-dev] KVM and CPUID

Hi folks. I was just thinking about how that CPUID change caused problems when running ChromeOS, and it occurred to me that it doesn't matter what gem5 supports when CPUID is run if the host system doesn't support the features it claims. To be really safe, when running with KVM, we should report at

[gem5-dev] review board not working, CPUID fix

I tried to upload these patches to review board but it kept giving me this: abort: The file was not found in the repository (207) stat: fail file: src/arch/x86/cpuid.cc One is a revert of the original CPUID patch, and the second is a new patch which enables just a few feature bits to make SE mode

Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2511/ --- (Updated Dec. 17, 2014, 7:39 a.m.) Review request for Default. Repository: gem5

[gem5-dev] VNC/KVM changes

These VNC/KVM changes are still pending: http://reviews.gem5.org/r/2514/ http://reviews.gem5.org/r/2511/ http://reviews.gem5.org/r/2517/ (marked ship it) http://reviews.gem5.org/r/2518/ http://reviews.gem5.org/r/2519/ http://reviews.gem5.org/r/2520/ (marked ship it) http://reviews.gem5.org/r/2526/

Re: [gem5-dev] Review Request 2519: x86: i8042: Give the keyboard controller a little TLC.

> On Nov. 25, 2014, 10:23 p.m., Nilay Vaish wrote: > > src/dev/x86/i8042.cc, line 418 > > > > > > We don't need this nack(). I changed the panic to a warn and left the nack in. > On Nov. 25, 2014, 10:23 p.m., Nilay Vaish

Re: [gem5-dev] Review Request 2519: x86: i8042: Give the keyboard controller a little TLC.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2519/ --- (Updated Dec. 17, 2014, 7:35 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2511/ --- (Updated Dec. 17, 2014, 7:27 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2519: x86: i8042: Give the keyboard controller a little TLC.

> On Nov. 25, 2014, 10:31 p.m., Nilay Vaish wrote: > > What's TLC and CL? "tender loving care" and "change list" - Gabe --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2519/#review5547 -

[gem5-dev] bituion/unittest CLs

I went to add a bitunion unit test, and I found that two of the unittests don't compile, circletest and cprintftest. I fixed circletest, but cprintftest still doesn't build. circletest fix: http://reviews.gem5.org/r/2583/ bitunion fix: http://reviews.gem5.org/r/2584/ bitunion unit test: http://r

[gem5-dev] Review Request 2585: test: Add a unittest for the BitUnion types.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2585/ --- Review request for Default. Repository: gem5 Description --- Changeset 10609

[gem5-dev] Review Request 2584: base: Fix assigning between identical bitfields.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2584/ --- Review request for Default. Repository: gem5 Description --- Changeset 10608

[gem5-dev] Review Request 2583: tests: Fix building the circletest unittest.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2583/ --- Review request for Default. Repository: gem5 Description --- Changeset 10607

Re: [gem5-dev] Review Request 2567: arm: Merge ISA files with pseudo instructions

Yeah, I'm not sure which way to go. I think broadening the definition of a pseudo instruction makes sense, but there's a reasonable amount of existing usage we'd want to update to keep things from being confusing. You might call the file util_inst? Or if it's in a directory of just instruction defi

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

s. > Getting the intel functionality is what I needed. > > > > > On Sun, Dec 14, 2014 at 9:53 PM, Gabe Black via gem5-dev < > gem5-dev@gem5.org> > wrote: > > > > I just tried running bzip2 approximately like the regressions would but > > with the KVM CPU,

Re: [gem5-dev] Kernel panic caused by changeset 10552

I tried reverting this change and it fixes the undefined instruction exceptions I was seeing. It does break KVM in SE mode though, so we probably shouldn't yank it out entirely. We need to find a minimal version of that change which makes KVM in SE work without breaking other things. Gabe On Wed,

Re: [gem5-dev] Review Request 2563: cpu: add support for outputing a protobuf formatted CPU trace

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2563/#review5685 --- I didn't see anything that seemed wrong, but I don't know anything about

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

platforms. > >> > >>The new code does seem to work for Intel platforms. > >> > >>The new code also seems to clean up a bunch of runtime warnings I was > >>getting on AMD platforms. > >> > >>However the new code on AMD is either much slow

Re: [gem5-dev] Possible to fix bitunion now?

It sounds like from this: http://www.informit.com/guides/content.aspx?g=cplusplus&seqNum=556 and this: http://stackoverflow.com/questions/10693913/c11-anonymous-union-with-non-trivial-members it might now be fixable if we're using C++11. Are we? Gabe On Fri, Dec 12, 2014 at 12:41 AM, Gabe Bla

Re: [gem5-dev] Review Request 2567: arm: Merge ISA files with pseudo instructions

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2567/#review5684 --- While it's definitely nice to get these into regular C++ instead of the I

Re: [gem5-dev] Review Request 2565: arm: Clean up and document decoder API

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2565/#review5683 --- src/arch/arm/decoder.hh

[gem5-dev] Possible to fix bitunion now?

Hi folks. This is mostly addressed to people up on fancy new language features. Back when I implemented the BitUnion stuff, I discovered that there was an annoying and serious bug which resulted from a limitation of C++. At the time, I think I saw that the missing feature would become available in

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

> On Dec. 10, 2014, 10:30 p.m., mike upton wrote: > > There is some issue with AMD platforms. A test that used to run in 30 sec > > is not finishing. > > > > > > mike upton wrote: > hello world passes. SPEC apps hang. > > > Gabe Black wrote: > Can you identify where it's getting stuck

Re: [gem5-dev] ELF image loader in x86 multiboot

Hi Randolf. I'm not familiar with the multiboot patches, but yes, secondary (AP) CPUs make a brief trip through real mode and 32 bit mode on their way to 64 bit mode, and we simulate that. The ELF loader in SE mode predates me, but I've always thought it tried too hard to identify what was what in

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

> On Dec. 10, 2014, 10:30 p.m., mike upton wrote: > > There is some issue with AMD platforms. A test that used to run in 30 sec > > is not finishing. > > > > > > mike upton wrote: > hello world passes. SPEC apps hang. > Can you identify where it's getting stuck? It could be there's someth

Re: [gem5-dev] Review Request 2562: arm: always set the IsFirstMicroop flag

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2562/#review5668 --- Ship it! Ship It! - Gabe Black On Dec. 10, 2014, 5:56 p.m., Ali Saidi

Re: [gem5-dev] Review Request 2561: sim: Clean up InstRecord

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2561/#review5666 --- src/sim/insttracer.hh

Re: [gem5-dev] Review Request 2559: cpu: Put all CPU instruction tracers in a single file

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2559/#review5667 --- Ship it! Ship It! - Gabe Black On Dec. 10, 2014, 5:54 p.m., Ali Saidi

Re: [gem5-dev] Review Request 2558: cpu: remove legion tracer

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2558/#review5665 --- Ship it! Ship It! - Gabe Black On Dec. 10, 2014, 5:54 p.m., Ali Saidi

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

_EFF_BASE. It seems that the contents of TR > register (which gets passed to kvm) are the same if with or without > *_EFF_BASE registers set. > > Thank you, > Alex > > -Original Message- > From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Gabe Black >

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2557/#review5663 --- Ok, now it's for real. Review away. - Gabe Black On Dec. 10, 2014, 10:

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2557/ --- (Updated Dec. 10, 2014, 10:11 a.m.) Review request for Default. Summary (updated)

Re: [gem5-dev] Kernel panic caused by changeset 10552

Yeah, I was going to say something about that. CPUID shouldn't advertise features that we don't support. For instance, that change tells CPUID to say we support AVX, but the decoder has no idea what to do with those instructions and will trigger an exception if one is executed. I noticed a bunch of

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

>> >> Gabe >> >> On Tue, Dec 9, 2014 at 4:51 PM, Dutu, Alexandru via gem5-dev < >> gem5-dev@gem5.org> wrote: >> >>> I haven't received any attachment to your email. So I don't have your >>> patch. >>> >>> Alex >>&

Re: [gem5-dev] Review Request 2514: scons: Make the USE_KVM variable available in C++.

> On Nov. 19, 2014, 3:33 p.m., Andreas Sandberg wrote: > > The change itself makes sense, but I'd really prefer if we could avoid > > conditional compilation and use a kvm-agnostic interface to handle device > > memory. See my reply in the email thread for RB #2513. > > > > Consider this a "sh

Re: [gem5-dev] Review Request 2510: Let other objects set up memory like regions in a KVM VM.

> On Dec. 8, 2014, 2:36 p.m., Andreas Hansson wrote: > > src/cpu/kvm/vm.cc, line 374 > > > > > > I think this causes problems with some of the officially supported > > compilers. It's just a hunch, but please check. > > Ga

[gem5-dev] changeset in gem5: Let other objects set up memory like regions ...

changeset 8fc6e7a835d1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=8fc6e7a835d1 description: Let other objects set up memory like regions in a KVM VM. diffstat: src/cpu/kvm/vm.cc | 80 -- src/cpu/kvm/vm.hh |

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

ail. So I don't have your >> patch. >> >> Alex >> >> -----Original Message- >> From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Gabe >> Black via gem5-dev >> Sent: Tuesday, December 09, 2014 6:42 PM >> To: gem5 Developer List &g

Re: [gem5-dev] Review Request 2557: imported patch wip.patch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2557/#review5659 --- Posted for reference, don't review yet. - Gabe Black On Dec. 10, 2014,

[gem5-dev] Review Request 2557: imported patch wip.patch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2557/ --- Review request for Default. Repository: gem5 Description --- Changeset 10605

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

lt; gem5-dev@gem5.org> wrote: > I haven't received any attachment to your email. So I don't have your > patch. > > Alex > > -Original Message- > From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Gabe Black > via gem5-dev > Sent: Tuesda

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

ng into virtualized mode. However, in FS I get an early >>> exception while the kernel is booting. This seems a bit different from what >>> Nilay and Adrian observed for FS. Could you please share the diffs that got >>> FS working? >>> >>> Thank

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

ifferent from what >> Nilay and Adrian observed for FS. Could you please share the diffs that got >> FS working? >> >> Thanks, >> Alex >> >> -Original Message- >> From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Gabe >> Blac

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

Could you please share the diffs that got > FS working? > > Thanks, > Alex > > -Original Message- > From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Gabe Black > via gem5-dev > Sent: Tuesday, December 09, 2014 6:07 PM > To: gem5 Developer List &

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

roblem in getting KVM CPU to run in FS mode. I figured >> that >> > the following changeset causes problems: >> > >> > authorAlexandru Dutu >> > Sun Nov 23 18:01:08 2014 -0800 (2 weeks ago) >> > changeset 10554 fe2e2f06a7c8 &g

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

n in FS mode. I figured > that > > the following changeset causes problems: > > > > authorAlexandru Dutu > > Sun Nov 23 18:01:08 2014 -0800 (2 weeks ago) > > changeset 10554 fe2e2f06a7c8 > > > > I saw the hardware reason 0x8021,

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

ed > > that > > > the following changeset causes problems: > > > > > > authorAlexandru Dutu > > > Sun Nov 23 18:01:08 2014 -0800 (2 weeks ago) > > > changeset 10554 fe2e2f06a7c8 > > > > > > I saw the hardware

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

ng manual and making sure gem5 gets all the bits > right as there is not much the KVM kernel model will tell about the cause > of failure. > > Best regards, > Alex > ____________ > From: gem5-dev [gem5-dev-boun...@gem5.org] on behalf of Gabe Black v

Re: [gem5-dev] Review Request 2510: Let other objects set up memory like regions in a KVM VM.

> On Dec. 8, 2014, 2:36 p.m., Andreas Hansson wrote: > > src/cpu/kvm/vm.cc, line 374 > > > > > > I think this causes problems with some of the officially supported > > compilers. It's just a hunch, but please check. Ugh. Y

Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)

I'm not an expert either, but I did have problems running KVM in SE mode on an Intel CPU. I didn't look into it that much, but I think things failed in the kernel somewhere. What might be happening is that the different vendors hardware virtualization mechanisms are more or less picky about various

[gem5-dev] changeset in gem5: misc: Generalize GDB single stepping.

changeset 6efb37480d87 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6efb37480d87 description: misc: Generalize GDB single stepping. The new single stepping implementation for x86 doesn't rely on any ISA specific properties or functionality. This cha

[gem5-dev] changeset in gem5: x86: Implement a remote GDB stub.

changeset e60c7758cf69 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e60c7758cf69 description: x86: Implement a remote GDB stub. This stub should allow remote debugging of 32 bit and 64 bit targets. Single stepping seems to work, as do breakpoints.

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