eviews.m5sim.org/r/529/
> ---
>
> (Updated 2011-03-01 13:49:24)
>
>
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
> Nathan Binkert.
>
>
> Summary
> ---
>
> cpu: split o3-specific parts out of BaseDynInst
> The bi
I just manually started a new set of regressions that should run this time.
Ali
On Mar 7, 2011, at 2:00 AM, Cron Daemon wrote:
>
> See /z/m5/regression/regress-2011-03-07-03:00:01 for details.
>
> ___
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> m5-dev@m5sim.org
> http:/
zilla/show_bug.cgi?id=42674
>>>
>>> I tried the provided codes. For the first one, 4.2.2 raises a warning
>>> but
>>> 4.4.0 does not. For the second one, 4.4.0 raises a warning but 4.2.2
>>> does
>>> not.
>>>
>>> --
>
Everyone,
I've just added math captcha to the wiki to prevent spam. Please let me know if
you run into any issues.
Thanks,
Ali
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fetched and put in the pred_hist.
src/cpu/o3/bpred_unit_impl.hh
<http://reviews.m5sim.org/r/570/#comment1314>
Yea, we could panic here instead of asserting.
- Ali
On 2011-03-11 15:21:28, Ali Saidi wrote:
>
> ---
>
called.
well, it's the most logical place for the code given what it does.
- Ali
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ok, but I'm not sure that it does. I'm pretty sure it still causes a
mispredict without it.
- Ali
On 2011-03-11 15:21:28, Ali Saidi wrote:
>
> ---
> This is an automatically generated e-mai
tive. If O3
> > is basing its behavior off of the instruction's flags instead of its
> > behavior (ie. if it actually called quiesce), I'd argue it shouldn't be
> > doing that.
>
> Ali Saidi wrote:
> Because for the CPU to quiesce it needs to stall
31>
Yea i was, that is why I changed it, but I can verify that it wasn't some
other bug
- Ali
On 2011-03-11 15:21:28, Ali Saidi wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
&
> On 2011-03-11 20:10:44, Ali Saidi wrote:
> > src/cpu/o3/bpred_unit_impl.hh, line 354
> > <http://reviews.m5sim.org/r/570/diff/1/?file=10843#file10843line354>
> >
> > Yea i was, that is why I changed it, but I can verify that it wasn't
> > some
I think we should just use /dist. The automounter is flaky.
Ali
On Mar 13, 2011, at 5:58 PM, Gabe Black wrote:
> These failed because M5 looked for the disk image on /n/poolfs/... and
> I'd only put it on /dist/... on zizzer. I copied it over so this should
> work next time, hopefully, and that
Looks like the parser x86 o3 regression fails without any changes in
the head. Anyone seen this?
Ali
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you've already rerun parser at least. If your stats
differences sound like what I'm describing, please go ahead and
update
them. I should have run them again myself, but I must have either
forgotten to or assumed they wouldn't affect SE.
Gabe
On 03/16/11 12:40, Ali Saidi wrote:
I don't know that gzip is still broken.
Ali
On Wed, 16 Mar 2011 17:52:22 -0700, Gabe Black
wrote:
Ok, I'll get gzip.
Gabe
On 03/16/11 14:50, Ali Saidi wrote:
Ok... I'll commit the update to parser shortly.
Ali
On Wed, 16 Mar 2011 17:44:25 -0700, Gabe Black
wrote:
It
changeset 2af262e73961 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2af262e73961
description:
X86: Update the stats for parser on x86 O3.
diffstat:
tests/long/20.parser/ref/x86/linux/o3-timing/simout| 9 +--
tests/long/20.parser/ref/x86/linux/o3-timing/stats.t
changeset 9f704aa10eb4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9f704aa10eb4
description:
O3: Fix unaligned stores when cache blocked
Without this change the a store can be issued to the cache multiple
times.
If this case occurs when the l1 cache
changeset b01a51ff05fa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b01a51ff05fa
description:
Mem: Fix issue with dirty block being lost when entire block
transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you
want
changeset bb2d04f0b8fb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bb2d04f0b8fb
description:
O3: Update regressions for mem block caching change.
diffstat:
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |18 +-
tests/long/10.linux-boot/ref/
changeset 48371b9fb929 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=48371b9fb929
description:
O3: Cleanup the commitInfo comm struct.
Get rid of unused members and use base types rather than derrived values
where possible to limit amount of state.
dif
changeset f08692f2932e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f08692f2932e
description:
O3: Send instruction back to fetch on squash to seed predecoder
correctly.
diffstat:
src/arch/alpha/predecoder.hh | 6 ++
src/arch/arm/predecoder.hh | 6 ++
changeset ce34f14c1f43 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ce34f14c1f43
description:
Stats: Update the statistics for rfe patch.
diffstat:
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini|2 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
changeset e08035e1a1f6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e08035e1a1f6
description:
ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefini
changeset db0663be3f31 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=db0663be3f31
description:
ARM: Fix small bug with VLDM/VSTM instructions.
diffstat:
src/arch/arm/isa/formats/fp.isa | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff
changeset afcb66f4b964 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=afcb66f4b964
description:
ARM: Previous change didn't end up setting instFlags, this does.
diffstat:
src/arch/arm/isa/insts/str.isa | 14 --
1 files changed, 8 insertions(+), 6 deletion
changeset 21e4f3a569fb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=21e4f3a569fb
description:
ARM: Bare metal system should have 256MB of RAM.
diffstat:
configs/common/FSConfig.py | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
diffs (37 lines):
changeset b0b94a7b7c1f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b0b94a7b7c1f
description:
ARM: Detect and skip udelay() functions in linux kernel.
This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but inst
changeset 18368caa8489 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=18368caa8489
description:
ARM: Identify branches as conditional or unconditional and direct or
indirect.
diffstat:
src/arch/arm/insts/branch.hh | 1 +
src/arch/arm/isa/insts/branch.isa
changeset ac8ef72e9700 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ac8ef72e9700
description:
ARM: Implement the Instruction Set Attribute Registers (ISAR).
The ISAR registers describe which features the processor supports.
Transcribe the values listed
changeset 93982cb5044c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=93982cb5044c
description:
ARM: Fix subtle bug in LDM.
If the instruction faults mid-op the base register shouldn't be written
back.
diffstat:
src/arch/arm/insts/macromem.cc | 77
changeset d062791aad69 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d062791aad69
description:
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
diffstat:
tests/SConscript
|3 +-
changeset ed9c6b16e977 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ed9c6b16e977
description:
Automated merge with ssh://h...@repo.m5sim.org/m5
diffstat:
configs/common/Caches.py
| 3 +
configs/common/FSConf
> > go faster, slower, etc.?
Not major changes, but things usually sped up a little bit.
- Ali
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:
>
> ---
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> http://reviews.m5sim.org/r/587/
> ---
>
> (Updated 2011-03-17 14:51:31)
>
>
> Review reques
:
>
> ---
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> ---
>
> (Updated 2011-03-17 17:39:34)
>
>
> Review
> On 2011-03-03 20:41:09, Ali Saidi wrote:
> > Please don't ship this until I have a chance to try it, I just want to make
> > sure it doesn't break ARM_FS/O3.
>
> Korey Sewell wrote:
> Sure, I'd welcome a go of things from some other folks to te
--
>
> (Updated 2011-03-11 15:09:54)
>
>
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
> Nathan Binkert.
>
>
> Summary
> ---
>
> sim: Fixes Simulation.py to allow more than 1 core for standard switching.
:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
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> ---
>
> (Updated 2011-03-17 16:06:13)
>
>
> Review request for
:
>
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> ---
>
> (Updated 2011-03-17 16:05:56)
>
>
> Review request for
We
> > might have an access that spans from one 16 byte chunk to the next. These
> > aren't really problems with this change, but it might make them easier to
> > hit.
> >
> > I'm assuming this had some effect on the regressions. Did things generally
- Ali
On 2011-03-18 16:06:35, Lisa Hsu wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
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> ---
>
> (Updated 2011-03-18 16:06:35)
>
>
> Review reques
> On 2011-03-03 20:41:09, Ali Saidi wrote:
> > Please don't ship this until I have a chance to try it, I just want to make
> > sure it doesn't break ARM_FS/O3.
>
> Korey Sewell wrote:
> Sure, I'd welcome a go of things from some other folks to te
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/603/
> ---
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> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
> Nathan Binkert.
>
>
>
lt; X is always
false
"
Basically, the curTick() + 1 line in pseudo_inst.cc and the
subsequent
"assert" from eventq.hh aren't playing nice together.
On Mon, Mar 21, 2011 at 9:43 AM, Ali Saidi
wrote:
What is the exact problem you're trying to solve here? Why can
I just did some searching and found this.
http://comments.gmane.org/gmane.comp.programming.tools.scons.user/20816
Have you tried scons 1.3? Maybe it's fixed.
Ali
Sent from my ARM powered device
On Mar 23, 2011, at 11:39 PM, Steve Reinhardt wrote:
> I think many of us have noticed that sc
Is there any reason to have a serialize function in the timing and o3 cpus?
Creating a checkpoint from them will be broken since if you're using cache the
dirty data won't be saved? Shouldn't we change their implementation to fatal()?
Thanks,
Ali
___
On Mar 26, 2011, at 4:48 PM, Korey Sewell wrote:
> I'm bumping the below e-mail from the users lists to dev. I believe it
> is a legit problem with decode not actually passing back the correct
> value for taken/not taken to the branch predictor when it detects a
> pc-relative, unconditional contr
On Mar 27, 2011, at 3:19 PM, Gabe Black wrote:
> On 03/27/11 13:13, Ali Saidi wrote:
>> On Mar 26, 2011, at 4:48 PM, Korey Sewell wrote:
>>
>>> I'm bumping the below e-mail from the users lists to dev. I believe it
>>> is a legit problem with decode
You could do that, but there is no guarentee you'd pick a non-broken version to
push. We wouldn't want to push anything from the last week with all the
compilation issues.
Ali
On Mar 29, 2011, at 6:19 PM, Korey Sewell wrote:
>> I'd prefer to see us just start updating m5-stable more regularly
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it during some miss
speculation.
- Ali
On 2011-03-30 08:41:48, Ali Saidi wrote:
>
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520/#review1034
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>
> ---
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this the branch case
added. Seems like that is way messier.
- Ali
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t does still catch some cases.
- Ali
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>
> -
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>
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On 2011-03-30 09:05:10, Ali Saidi wrote:
>
> -
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On 2011-03-30 14:55:05, Ali Saidi wrote:
>
> ---
> This is an autom
> On 2011-03-30 15:38:14, Gabe Black wrote:
> > I'm not sure this is right yet. Won't it only copy the USR registers now
> > and leave out all the other modes? Also, is there anything wrong with
> > reading the CPSR, changing the mode, and then writing it back?
Everyone, this change alters the way that the O3 cpu switches registers from
the atomic cpu. If you use checkpoint/switchover and m5 please test this
(specifically the change to src/cpu/o3/thread_context_impl.hh)
Thanks,
Ali
On Mar 30, 2011, at 4:55 PM, Ali Saidi wrote
I just realized today that m5 can automatically compress the trace
output generated by traceflags. Since I didn't realize this worked I've
added to the documentation, but I thought I would also share it with the
list:
Trace file can become rather large quickly, but they do
compress very well
None of those benchmarks probably push the memory system with multiple
cores like fft. Why don't you give Nilay your fft benchmark?
Ali
On Fri, 1 Apr 2011 16:42:48 -0400, Korey Sewell
wrote:
Hi Nilay,
I think I've located the images for those benchmarks so I'll test a
couple
of these over
http://reviews.m5sim.org/r/588/
> -------
>
> (Updated 2011-03-17 16:05:56)
>
>
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
> Nathan Binkert.
>
>
> Summary
> ---
>
> X8
changeset c6302ef82244 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c6302ef82244
description:
ARM: Fix multiplication error in udelay
diffstat:
src/kern/linux/events.cc | 3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diffs (13 lines):
diff -r aeec9e157d
changeset e46d051c35be in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e46d051c35be
description:
ARM: Remove debugging warn that was accidently left in.
diffstat:
src/arch/arm/insts/macromem.cc | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diffs (12 lines)
changeset bd40568644f3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bd40568644f3
description:
ARM: Fix checkpointing case where PL111 is powered off.
diffstat:
src/dev/arm/pl111.cc | 8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diffs (18 lines):
d
changeset 7b6983f2787a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7b6983f2787a
description:
IDE: Support x86, Alpha, and ARM use of the IDE controller.
diffstat:
src/dev/ide_ctrl.cc | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diffs (17 lines):
di
changeset 3d6c08c877a9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3d6c08c877a9
description:
O3: Tighten memory order violation checking to 16 bytes.
The comment in the code suggests that the checking granularity should
be 16
bytes, however in realit
changeset 89221928d131 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=89221928d131
description:
CPU: Remove references to memory copy operations
diffstat:
src/cpu/base_dyn_inst.hh| 7 ---
src/cpu/inorder/inorder_dyn_inst.hh | 1 -
src/cpu/o3/commit
changeset 5806937a7c67 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5806937a7c67
description:
O3: Update stats for memory order violation checking patch.
diffstat:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini |
3 +
tests/long/00
changeset 1b63e9afeafc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1b63e9afeafc
description:
ARM: Fix table walk going on while ASID changes error
diffstat:
src/arch/arm/faults.cc | 14 ++
src/arch/arm/faults.hh | 10 ++
src/arch/a
changeset 78b9f056d58a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=78b9f056d58a
description:
ARM: Tag appropriate instructions as IsReturn
diffstat:
src/arch/arm/isa/insts/branch.isa | 6 --
src/arch/arm/isa/insts/data.isa | 19 ---
changeset 6c051a8df26a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6c051a8df26a
description:
ARM: Fix m5op parameters bug.
All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specifie
changeset 7ecbffb674aa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7ecbffb674aa
description:
ARM: Cleanup implementation of ITSTATE and put important code in
PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a
changeset cad97f04eb91 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cad97f04eb91
description:
ARM: Fix bug in MicroLdrNeon templates for initiateAcc().
diffstat:
src/arch/arm/isa/templates/mem.isa | 8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff
changeset 45331a355c38 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=45331a355c38
description:
ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu
works.
This change fixes a small bug in the arm copyRegs() code where some
registers
wo
r 04 11:42:29 2011 -0500
@@ -26,7 +26,8 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Steve Reinhardt
+ * Authors: Ali Saidi
+ * Steve Reinhardt
* Stephen Hines
changeset 20362a3a1540 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=20362a3a1540
description:
ARM: Update stats for previous changes.
diffstat:
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
| 6 +-
tests/long/00.gzip/ref/arm/lin
changeset 54a65799e4c1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=54a65799e4c1
description:
ARM: Update stats for default inclusion of CF adapter.
diffstat:
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 104 +-
tests/long/10.li
changeset 134bd699967a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=134bd699967a
description:
ARM: Include IDE/CF controller by default in PBX model.
Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py
--benchmark=ArmLinuxFrameBuf
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http://reviews.m5sim.org/r/631/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
it was this change which was directly after the one I
> pointed out before.
>
> changeset: 8134:b01a51ff05fa
> user:Ali Saidi
> date:Thu Mar 17 19:20:19 2011 -0500
> summary: Mem: Fix issue with dirty block being lost when entire
> block transferred to non
Jumping in somewhat randomly here, uint64_t even on a 32bit machine is
reasonably fast. It's not going to be as fast, but it will be correct.
My vote would be to just switch all that Set code that uses long to
explicitly use uint64_t and if it's slower on a 32bit machine so be it.
At least it's
And actually, couldn't you use an stl bitset for this?
Thanks,
Ali
On Wed, 06 Apr 2011 15:34:01 -0500, Ali Saidi wrote:
Jumping in somewhat randomly here, uint64_t even on a 32bit machine
is reasonably fast. It's not going to be as fast, but it will be
correct. My vote would be to j
6 Apr 2011, Ali Saidi wrote:
And actually, couldn't you use an stl bitset for this?
Thanks,
Ali
On Wed, 06 Apr 2011 15:34:01 -0500, Ali Saidi
wrote:
Jumping in somewhat randomly here, uint64_t even on a 32bit machine
is reasonably fast. It's not going to be as fast, but it will
Wed, Apr 6, 2011 at 5:12 PM, Nilay Vaish wrote:
>> I believe even popcount is portable. I am not opposed to using bitset, just
>> that it would probably require lot more changes.
>>
>> --
>> Nilay
>>
>> On Wed, 6 Apr 2011, Ali Saidi wrote:
>>
Assuming the store had it's address available it might not be complete, things
can stay in the store buffer a while, but it would still be able to forward its
data to the load, which it sounds like what is going on.
Ali
Sent from my ARM powered device
On Apr 7, 2011, at 8:50 AM, Eberle wrote
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(Updated 2011-04-10 16:50:13.497059)
Review request for Default, Ali Saidi, Gabe
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(Updated 2011-04-10 16:52:32.283655)
Review request for Default, Ali Saidi, Gabe
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