[gem5-users] Re: Dirty blocks in L1I cache

On 4/23/2024 3:51 AM, Theodoros Papavasiliou via gem5-users wrote: Hello everyone, I'm running some spec2017 benchmarks on gem5 and I noticed there are some dirty blocks inside the L1 instruction cache. These blocks are also shared with the L1 data cache. So, what is a possible explanation

[gem5-users] Wondering about PCIe ATS PRI support / ARM SMMU

Dear gem5-ers: While I'm not working on it just at the moment, I was hoping there might be support for dynamic page mapping for I/O devices via the PCIe ATS (Address Translation Services) PRI (Page Request Interface) facility. My reading of the ARM SMMU code is that it is not *quite* there, and

[gem5-users] Re: warn: MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!

On 3/19/2024 4:54 AM, Sasi Kiran Reddy via gem5-users wrote: Hi Guys, When i am simulating some of the spec2006 benchmarks like bzip2, libq,namd etc in x86. The simulation is getting stuck in the middle. with the warning message as "warn: MOVNTDQ: Ignoring non-temporal hint, modeling as

[gem5-users] Re: Dual load cause xbar busy

On 2/21/2024 5:04 AM, chengyong zhong via gem5-users wrote: Thanks for the clarification. IMP, it is a common scenario for modeling a HPC core, can anyone provide some tips or sample programs? On the other hand, I found that multi-bank is supported in the RUBY cache

[gem5-users] Re: Dual load cause xbar busy

On 2/20/2024 9:29 PM, chengyong zhong wrote: Hi Eliot, Thanks for your kind reply. Are there any sample to implement the feature in the Gem5 code repository? I wrote: Unless I've missed something, gem5 does not provide dual / multi port caches at present. Hence, no example (that I am aware

[gem5-users] Re: Dual load cause xbar busy

On 2/20/2024 8:18 AM, chengyong zhong via gem5-users wrote: Hi all, I'm using the O3CPU model for performance evaluation, we have two LoadUnit, I find that if dual load issued same time, the second load will be blocked and rescheduled after a few cycles of latency. The O3CPUAll and Xbar trace

[gem5-users] Re: Architectural state of registers - O3CPU

On 2/14/2024 1:14 PM, Eliot Moss via gem5-users wrote: On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote: I would like to add some additional information. The register number does vary in each iteration, sometimes it is above 100. So I think it should be the physical register value

[gem5-users] Re: Architectural state of registers - O3CPU

On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote: I would like to add some additional information. The register number does vary in each iteration, sometimes it is above 100. So I think it should be the physical register value. If my understanding is correct, the physical register

[gem5-users] Re: Architectural state of registers - O3CPU

On 2/14/2024 12:26 PM, reverent.green--- via gem5-users wrote: Hey Eliot, thank you for your answer. I have a follow-up question. I know, that there are more physical registers than architectural ones and that the achitectural state should be set in the final commit state. So if the debug

[gem5-users] Re: Architectural state of registers - O3CPU

On 2/14/2024 11:19 AM, reverent.green--- via gem5-users wrote: Hello everyone, can someone give me a hint, where exactly in the code the architectural state of (load) instructions is getting set and becomes visible? I tried to trace instructions during the execution via log outputs, but got a

[gem5-users] Re: Effective address and ISA

On 2/6/2024 11:13 AM, Nazmus Sakib via gem5-users wrote: I think gem5 has this SplitDataRequest() method that breaks the request if it would need more than one cacheline. In fact, the page fault is occurring before it goes to the cache. The panic message says the address is 0x400. By looking

[gem5-users] Re: Effective address and ISA

On 2/5/2024 1:39 PM, Nazmus Sakib wrote: I am trying to see how small I can set the cacheline size (gem5 ARM, test binary is aarch64) When I set it to 4 bytes, I get a page fault for address 0x400c00. By going through bunch of debugging (using print of my own and debug flags), I think the

[gem5-users] Re: Effective address and ISA

On 2/5/2024 10:41 AM, Nazmus Sakib via gem5-users wrote: Hello. I was trying to find how the virtual (logical) addresses are calculated and passed on to cpu. In the load/store queee, after a request object is created, then the corresponding instruction is assigned a effective address from this

[gem5-users] Re: How Can I Save the output file-Full System Simulation

On 1/16/2024 1:15 AM, sun2k23 via gem5-users wrote: I think maybe you can try /sbin/m5  utility, using the writefile option. Then you can redirect the virtual OS environment files to local Hosts. The command format is like below: S2K At 2024-01-16 11:41:57, "hu miao via gem5-users"

[gem5-users] Re: About gem5 stats granularity

On 1/12/2024 7:57 AM, elio.vinciguerra--- via gem5-users wrote: Hi everybody, I should have the statistics provided by gem5 in stats.txt with an instruction level granularity. I noticed that by default gem5 provides them global, from the beginning of execution to the end. Is it possible to

[gem5-users] Re: importing packages like numpy

On 1/2/2024 9:28 AM, saras nanda via gem5-users wrote: Hi Everyone , I am doing a full system simulation on ARM using fs_bigLITTLE.py and fs_power.py , I am trying to import numpy library in my python script but it takes 3-4 days and is still running but the library is not imported , how can I

[gem5-users] Re: config.dot generation fails

On 12/28/2023 9:24 PM, Arka Maity via gem5-users wrote: Hi Eliot, Thanks for your response. Yes, the above issue is just a warning and does not seem to affect the actual simulation runs. I was just worried, that something could be wrong with my configuration, which might cause issues later.

[gem5-users] Re: config.dot generation fails

On 12/27/2023 9:53 PM, Arka Maity via gem5-users wrote: Hi All, My ruby configuration instantiates multiple ruby networks, Memtesters, and CHI controllers. When I start, the simulation, I encounter the following warning. Warning: flat edge between adjacent nodes one of which has a record

[gem5-users] Re: Read Miss Operation at Last Level Cache (LLC)

On 12/8/2023 1:31 AM, zahra moein via gem5-users wrote: Hello, Thank you very much for your response. I appreciate your assistance, and I made an effort to understand the code, which provided me with a better understanding. However, I couldn't determine the exact origin of the packet sent by

[gem5-users] Re: Read Miss Operation at Last Level Cache (LLC)

On 12/1/2023 6:24 PM, zahra moein via gem5-users wrote: Thank you for your response. I would like to seek further clarification regarding the parameter RecvTimingResp: void BaseCache::recvTimingResp(PacketPtr pkt) Could you please confirm if this parameter represents a packet that is

[gem5-users] Re: Read Miss Operation at Last Level Cache (LLC)

On 11/30/2023 2:07 PM, zahra moein via gem5-users wrote: Hi everyone, As we already know, a "Read miss" at the last cache level (LLC) means that the desired block in the LLC for reading was not found. Consequently, it is necessary to locate a victim block and copy the desired block from the

[gem5-users] Re: Understanding Squashed Loads/Stores

On 11/21/2023 12:16 PM, Arth Shah via gem5-users wrote: Hi everyone, I'm running a benchmark on the O3CPU model (aarch64) and see something strange that I wasn't able to understand. I see a lot of Squashed loads and stores in the LSQ but it doesn't seem like it is due to branch misprediction

[gem5-users] Re: Is SMT Supported in ARM Full System Simulation

On 10/10/2023 4:04 AM, Abdelrahman S. Hussein via gem5-users wrote: Hello, I am considering using ARM ISA for simulation on gem5. I understand that SMT is NOT supported for Full System Simulation for x86. I just would like to know if gem5 supports SMT for Full System simulation in ARM ISA.

[gem5-users] Re: Squashing Instructions after Page Table Fault

You observed that the check on line 471 in tlb.cc did not seem to be the one causing the fault in the case you were looking at. It occurs to me that the line 471 check is for a *resident* page. If the page is *not* resident, some other check would apply, and the fault might be raised when the

[gem5-users] Re: Squashing Instructions after Page Table Fault

On 10/4/2023 10:03 AM, reverent.green--- via gem5-users wrote: Hi Yuan, thank you very much for your detailed response. My understanding of the fault handling in gem5 is getting better and better. Using debug flags, I can trace the control flow during the execution of my code. I am

[gem5-users] Re: Accessing dependent memory locations in a single instruction

On 9/25/2023 4:59 PM, Leonard Peterson via gem5-users wrote: Hello, I'm trying to implement an instruction "myinst" that accesses dependent memory locations (similar to pointer chasing) using the TimingCPU model (initiateAcc() and completeAcc()). For example: myinst r0,0x14000

[gem5-users] Re: Counters for # DRAM reads, writes, page hits, and page misses

On 9/8/2023 2:55 AM, Aritra Bagchi via gem5-users wrote: Hi all, Can anyone indicate how to extract performance counters such as the number of DRAM read operations, the number of DRAM write operations, the number of times a page miss occurs, etc.? Inside src/mem/mem_ctrl.cc, 

[gem5-users] Re: Latency or speed

On 9/5/2023 9:30 AM, 中国石油大学张天 via gem5-users wrote: Hello, I would like to ask, in Gem5, will differences in the order of magnitude of operations such as Add affect factors such as latency or execution speed? I'm not sure how to answer that. Things depend so much on processor model and

[gem5-users] Re: can't run riscv simulation with any CPU model except Atomic

On 8/24/2023 1:35 AM, oe-fans via gem5-users wrote: After 2 hours, message appear in m5term. My CPU is xeon e5 2687w v3, I think the boot time is too long, are there any way to accelerate it? I have seen it take longer if the number of cpus told to gem5 does not match the number of cpus in the

[gem5-users] Re: How to connected CpuSidePort and MemSidePort within a simobject ( not in config file)

On 8/14/2023 3:47 PM, Khan Shaikhul Hadi wrote: Instead of directly connecting all level 1 caches ( icache, dcache etc) to CPU and next level bus, I want to create a controller module that will have all those caches . This controller module will receive all cpu requests and distribute them to

[gem5-users] Re: How to connected CpuSidePort and MemSidePort within a simobject ( not in config file)

On 8/14/2023 1:42 PM, Khan Shaikhul Hadi wrote: Initially I was thinking doing something like this as you suggested: CpuSidePort cacheMemSidePortConnection = cache.memSidePort; MemSidePort cacheCpuSidePortConnection = cache.cpuSidePort; problem is when I looked into how python code

[gem5-users] Re: How to connected CpuSidePort and MemSidePort within a simobject ( not in config file)

On 8/14/2023 11:58 AM, Khan Shaikhul Hadi via gem5-users wrote: In my code I'll have a simobject which has its own cache. As classical cache use CpuSidePort and MemSidePort to receive and respond to request, I want to create some internal CpuSidePort and MemSidePort in my simobject like below

[gem5-users] Re: Build Error 134

On 8/6/2023 1:50 AM, Kaiwen Xue via gem5-users wrote: On Sat, Aug 5, 2023 at 5:13 AM Eliot Moss via gem5-users wrote: On 8/5/2023 2:16 AM, Kaiwen Xue via gem5-users wrote: Hi, I'm new to gem5 and trying to follow the official tutorial [1] to build an x86 opt target from commit hash 48b4788

[gem5-users] Re: Build Error 134

On 8/5/2023 2:16 AM, Kaiwen Xue via gem5-users wrote: Hi, I'm new to gem5 and trying to follow the official tutorial [1] to build an x86 opt target from commit hash 48b4788. The compilation failed with Error 134. Outputs didn't seem to be meaningful - they are just normal building messages and

[gem5-users] Re: how clflush is simulated in classic cache ( not ruby ) ?

On 8/3/2023 11:56 AM, Khan Shaikhul Hadi wrote: I'm not sure about silent suppression as that flush instruction is called write after write happens to that memory. Fault should arise when a write request is issued. . This would happen during address translation, which comes before putting

[gem5-users] Re: how clflush is simulated in classic cache ( not ruby ) ?

On 8/2/2023 3:20 PM, Khan Shaikhul Hadi via gem5-users wrote: But my gdb traces showing that request->isMemAccessRequired() is returning false. That's where I'm confused. I'm running this simulation in SE mode. I always deal with FS mode, but I don't think that matters. I wonder if the

[gem5-users] Re: how clflush is simulated in classic cache ( not ruby ) ?

On 8/1/2023 5:15 PM, Khan Shaikhul Hadi via gem5-users wrote: As far as I understand, gem5 simulates functionality of clflush instruction for classic cache. Can anyone explain how it do that ? I traced Clflushopt::initiateAcc() function call which eventually calls LSQ::pushRequest() function

[gem5-users] Possible bug in cache/base.cc

Dear gem5-ers - I've run across something, which unfortunately I cannot reliably repeat, that suggests an oversight in the code of src/mem/cache/base.cc. In particular, it appears that a HardPFResp can arrive where the MSHR remembered in the packet's senderState no longer has any targets. This

[gem5-users] Re: Can't explain timing result for flush and fence in classical cache hierarchy

On 7/6/2023 1:47 PM, Khan Shaikhul Hadi via gem5-users wrote: In my configuration I used CPUTypes.O3 and PrivateL1SharedL2CacheHeirarchy to check how clflush and fence impacts the timing of workload. In my workload I run 10,000 iteration to update an array value, 200 updates per thread. In

[gem5-users] Re: Analyzing instruction cycle count

On 7/11/2023 9:13 PM, Nick F via gem5-users wrote: Good afternoon, I have been trying to use Gem5 to research and study the performance of several different computer architectures. However, I have been noticing that I may be unable to accurately model the differences in cycle length for

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

On 7/11/2023 5:46 PM, Ayaz Akram via gem5-users wrote: Hi Eliot, Based on my understanding, when pkt->makeResponse() is called it updates the "cmd" of the pkt with the appropriate responseCommand (this line of code: cmd = cmd.responseCommand();) . If you look at "MemCmd::commandInfo[]"  in

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

On 7/11/2023 3:03 PM, John Smith wrote: Thanks for responding, Elliot. I somewhat understand that after the write is accomplished, the returning packet won't have the data. But still, why is the returned value 0 in that case? Shouldn't it still be equal to the memory access latency. In the

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

On 7/11/2023 3:20 PM, Ayaz Akram via gem5-users wrote: Hi John, If you are checking if the pkt is write when pkt->hasData() condition is true in recvAtomicLogic() function, the check (pkt_is_write) will always be false. The reason is that a write pkt would have already written its data to the

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

On 7/11/2023 1:28 PM, John Smith via gem5-users wrote: So, I used the function pkt->isWrite() to check if the packet is a write request. And I observed that inside the pkt->hasData() if condition, pkt->isWrite() returned false. Hence only the read packets were entering the if(pkt->hasData())

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

On 7/11/2023 1:01 PM, Eliot Moss wrote: On 7/11/2023 12:52 PM, John Smith wrote: Okay, but I've also noticed that a WriteReq generally carries no data. Why exactly is that? Cause if we are writing to memory, then the memory access latency shouldn't be 0 right? I believe that happens if the

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

On 7/11/2023 12:52 PM, John Smith wrote: Okay, but I've also noticed that a WriteReq generally carries no data. Why exactly is that? Cause if we are writing to memory, then the memory access latency shouldn't be 0 right? I believe that happens if the write got its data by snooping a cache. The

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

On 7/11/2023 12:37 PM, John Smith via gem5-users wrote: Hi everyone, Could someone please help me with explaining what's happening in the below code snippet? It's the receiveAtomicLogic() function in mem_ctrl.cc. Why are we returning the latency as 0 if the packet doesn't have any data? And

[gem5-users] Re: Error: snoop filter exceeded capacity

On 7/10/2023 5:17 PM, John Smith wrote: I understood how to pass it. However, --param='system.membus.snoop_filter=NULL' doesn't seem to work. I'm getting the following error: NameError: name 'NULL' is not defined I see. Well, this line was in an older version of XBar.py: snoop_filter =

[gem5-users] Re: Error: snoop filter exceeded capacity

On 7/10/2023 3:59 PM, John Smith via gem5-users wrote: I'm sorry. Here's the error message I got: build/X86/mem/snoop_filter.cc:197: panic: panic condition !is_hit && (cachedLocations.size() >= maxEntryCount) occurred: snoop filter exceeded capacity of 131072 cache blocks That snoop filter

[gem5-users] Re: Adding a delay of certain ticks in gem5

On 7/6/2023 12:48 PM, John Smith via gem5-users wrote: I've looked into the schedule() function which is used to schedule events. But can this function be used to simulate delays? Not by itself. You schedule an event at something like curTick() + 100. When the event happens, a function gets

[gem5-users] Re: Adding a delay of certain ticks in gem5

On 7/6/2023 11:12 AM, John Smith via gem5-users wrote: Greetings, If I want to, for example, add a delay of 100 ticks before a line of code executes in the function handleTimingReqMiss() in cache.cc, how do I go about doing that? Generally speaking, you'll have to schedule an event and then

[gem5-users] Re: Question about InOrder cpu models

On 7/4/2023 7:17 PM, Eliot Moss via gem5-users wrote: Dear gem5-ers -- I am thinking of trying to put together something that roughly models ARM's R82, which is an 8-stage, width 3, in order cpu. (It's also not a single thing, but has numerous options you choose, and then set up RTL and can

[gem5-users] Question about InOrder cpu models

Dear gem5-ers -- I am thinking of trying to put together something that roughly models ARM's R82, which is an 8-stage, width 3, in order cpu. (It's also not a single thing, but has numerous options you choose, and then set up RTL and can have your design manufactured.) I see that there are

[gem5-users] Re: Shared variables between multi-core RISCV CPUs

On 7/1/2023 11:38 PM, Abdlerhman Abotaleb via gem5-users wrote: How can I share a variable between multicores in GEM5. (I'm simulating RISCV- Cores) I can see that each core allocates different VPN to PFN translation. So even if I explicitly assign a memory address to a variable (i.e. char*arr

[gem5-users] Re: bit-slice processors?

On 6/28/2023 9:42 AM, 中国石油大学张天 via gem5-users wrote: Can gem5 be used to simulate bit-slice processors? If you're up for defining a new cpu model - not a light undertaking - then I see no reason why not. If you're not already aware, gem5 is not a circuit level model. Its modules are written

[gem5-users] Re: Fatal error for when clflush is included in workload for O3 system simulation

On 6/22/2023 8:19 PM, Khan Shaikhul Hadi via gem5-users wrote: Hi, Thank you for your response with the patch link. It helped me a lot to understand what's going on and limitations with clflush. Do you have any idea if clflush alternative for arm isa is implemented in gem5 properly or not. I

[gem5-users] Re: Persistent memory in gem5: How to test persistent memory workload properly.

On 6/22/2023 5:47 PM, Khan Shaikhul Hadi wrote: Hi Eliot, Thank you for your detailed answer. For my current work, I need "CLFLUSH" and "MFENCE" to work properly. For clflush, I was planning to modify the instructions execution to issue a flush request to the cache and handle the rest using

[gem5-users] Re: Persistent memory in gem5: How to test persistent memory workload properly.

On 6/22/2023 4:54 PM, Khan Shaikhul Hadi via gem5-users wrote: Hi, I want to simulate a Persistent Memory machine in gem5. Gem5 has an NVMe module but at instruction level ,for most part, it does not simulate CLFLUSH ( specially for MESI cache coherence protocol ). I am also not sure if it

[gem5-users] Re: simulate a multi-core processor with Gem5

On 6/20/2023 10:41 AM, 中国石油大学张天 via gem5-users wrote: How to simulate a multi-core processor with Gem5, such as how to write configuration files? For example, in the following form: You don't write config files. You write python code that creates instances of python classes. The gem5 system

[gem5-users] Re: How clflush execution works in gem5 ?

On 6/16/2023 11:39 AM, Khan Shaikhul Hadi via gem5-users wrote: Hi, I'm trying to figure out how "clflush" instruction works in gem5. Specially, how it issues a signal to the cache controller to evict the block from cache hierarchy throughout the system and how it receives confirmation to

[gem5-users] Re: Request for Guidance: Extracting Detailed Information for Floating-Point Instructions

On 6/16/2023 3:07 AM, Alexandra-Nicoleta DAVID via gem5-users wrote: Dear gem5 Community, I am currently using the gem5 simulator for my research work and I find it a powerful and insightful tool for studying and understanding the inner workings of computer architectures. I am particularly

[gem5-users] Re: Writing a script to run multiple simulations at once

On 6/14/2023 11:30 AM, Derek Christ wrote: Hello Eliot Moss, [one ell please] a shared Python file with parameter settings sounds useful. What I meant with running gem5 without the gem5 executable was to use the compiled library directly from the Python configuration script. From

[gem5-users] Re: Writing a script to run multiple simulations at once

On 6/14/2023 2:32 AM, Derek Christ via gem5-users wrote: Hello, maybe I have missed something in the official docs, but I'm not sure how to run multiple simulations with different parameters concurrently to speed up the process. What I have done is I created a Python script that sets

[gem5-users] Re: Modeling DRAM memory latencies

On 6/13/2023 9:07 AM, Vincent Abraham wrote: Sure, I'm using the 22.1.0.0 version and the memory controller files (MemCtrl.py, mem_ctrl.cc, mem_ctrl.hh) are located in src/mem/. On Tue, Jun 13, 2023 at 8:32 AM Eliot Moss mailto:m...@cs.umass.edu>> wrote: On 6/13/2023 7:10 AM, Vincent

[gem5-users] Re: Modeling DRAM memory latencies

On 6/13/2023 7:10 AM, Vincent Abraham wrote: Hi, I'm afraid just changing the parameters doesn't do the job for me. I want to add a delay at the memory controller level, when it sends the requests to the memory. Could anyone point me to a function where I should do the changes? Also, how

[gem5-users] Re: Modeling DRAM memory latencies

Yes, adjusting some parameters in the memory controller may be the easiest then - though Id have to analyze the parameters and their meanings to see whether you'd need to add new parameter(s) and code. EM ___ gem5-users mailing list --

[gem5-users] Re: Modeling DRAM memory latencies

On 6/10/2023 2:32 PM, Vincent Abraham via gem5-users wrote: I'm extremely sorry if I worded my question incorrectly. I'm actually trying to introduce a delay whenever a read/write request happens in the main memory. For example, in a memory write, the data would only be flagged as dirty after a

[gem5-users] Re: Modeling DRAM memory latencies

On 6/10/2023 11:12 AM, Vincent Abraham via gem5-users wrote: Hi everyone, I'm trying to model additional latencies in the main memory while performing write/read operations. Could anyone tell me how I could go about doing it? Of course the dram module has a gazillion timing and energy

[gem5-users] Re: Changing Parameters in NVMInterface subclasses

On 6/10/2023 7:47 AM, Vincent Abraham via gem5-users wrote: Hi everyone, I want to change some of the parameters like tREAD, tWRITE, etc. in the NVM_2400_1x64 class. I tried to create a new subclass for it but I wasn't able to pass the class by name in the mem-type parameter in fs.py. And even

[gem5-users] Re: Custom cache memory

On 5/20/2023 6:39 PM, Pavitra bhade via gem5-users wrote: Dear all, I am looking to create a cache memory with  different structure and mapping algorithm. For eg an additional bit for each cache memory location, different mapping algorithm based on the value of that bit etc. I want a to

[gem5-users] Re: How to use more CPU for running FS model?

On 5/7/2023 9:15 PM, Xiang Li via gem5-users wrote: Hi, I'm running X86 FS model, it would take me a long time for starting a FS model. I find it just using one CPU, can gem5 use more CPU when running FS model? No. It's modeling a whole complex system at the level of individual small steps

[gem5-users] Re: 回复：Re: 回复：Re: 回复：gem5& execute&

On 5/7/2023 10:50 AM, 中国石油大学张天 via gem5-users wrote: Sorry for taking so long to reply to you. The goal I want to achieve is a simple reproduction of this article (Extending Moore's Law via Computationally Error Tolrant Computing), ultimately completing such a system. I believe the core goal

[gem5-users] Re: Different latencies

On 5/2/2023 1:01 PM, Shen, Fangjia wrote: Regarding the data latency, I think it depends on whether the cache is sequential access (access cache tags, then data) or parallel access (access tags and data at the same time - common optimization for the L1 cache).  See the code for

[gem5-users] Re: Different latencies

On 4/30/2023 11:33 PM, Inderjit singh via gem5-users wrote: Any ideas. Inderjit Singh On Wed, May 11, 2022 at 10:08 PM Inderjit singh > wrote: 1. What is the difference between data/tag/response latency? 2. How can I add write latency (for NVM

[gem5-users] Re: CXL (Compute Express Link) in gem5?

On 3/27/2023 6:13 AM, gabriel.busnot--- via gem5-users wrote: Thanks, Gabriel, for your response, now a month ago. I want to turn my attention back to this ... :-) I can’t provide you with an assertive answer but I’ve also been looking at CXL recently so here is what I understand so far.

[gem5-users] Re: 回复：Re: 回复：gem5& execute&

On 4/20/2023 12:20 PM, 中国石油大学张天 via gem5-users wrote: Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already midnight here, so I'll go to bed first 。 Thank you again. By the way, it seems that every time I send you an email, you always reject it. If

[gem5-users] Re: 回复：gem5& execute&

On 4/20/2023 11:56 AM, 中国石油大学张天 via gem5-users wrote: Thank you for your reply again, hahahaha. I have been thinking recently whether it is possible to design ALU through Verilog, translate it through Verilator or other tools, and ultimately use it in Gem5. I'm not sure if it's feasible. I am

[gem5-users] Re: gem5& execute&

On 4/20/2023 11:33 AM, Eliot Moss via gem5-users wrote: On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote: Hello everyone, I would like to ask, when executing non memory access instructions in Gem5, shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented

[gem5-users] Re: gem5& execute&

On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote: Hello everyone, I would like to ask, when executing non memory access instructions in Gem5, shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how is this instruction executed? gem5 does not model

[gem5-users] Re: SPEC2017 Calculating CPI

On 4/13/2023 6:24 AM, Farbin Fayza via gem5-users wrote: Hi Heng, Thanks for your reply. Do you mean something like this? I changed atomic.cc like this: void AtomicSimpleCPU::drainResume() {     assert(!tickEvent.scheduled());     if (switchedOut())         return;     DPRINTF(SimpleCPU,

[gem5-users] Re: 回复：the definition of IntAlu

On 4/12/2023 8:12 AM, 中国石油大学张天 via gem5-users wrote: So my current understanding is that there is no specific implementation of the ALU in gem5, but some required attributes are set, such as delay, number of functional units, power consumption, etc. So to design the ALU, it doesn't work. The

[gem5-users] Re: the definition of IntAlu

On 4/12/2023 7:17 AM, Eliot Moss wrote: On 4/11/2023 11:50 PM, 中国石油大学张天 via gem5-users wrote: In gem5, where are the actual definitions of various functional units? For example, where is the definition of IntAlu? src/cpu/o3/FuncUnitConfig.py Typed too fast: Not to be snarky, but I found

[gem5-users] Re: the definition of IntAlu

On 4/11/2023 11:50 PM, 中国石油大学张天 via gem5-users wrote: In gem5, where are the actual definitions of various functional units? For example, where is the definition of IntAlu? src/cpu/o3/FuncUnitConfig.py No to be narky, but I found this in less than 30 seconds using grep over the sources.

[gem5-users] Re: CPU&

On 4/9/2023 9:33 PM, 中国石油大学张天 via gem5-users wrote: Hi everyone, I'm new to gem5. I wonder if it is possible to make changes to the ALU with Gem5? For example, I want to implement the addition of two numbers through the Residue Number System instead of binary. Or is there any way to implement

[gem5-users] Re: SPEC2017 - Most of the metrics in m5.out/stats.txt are 0 or undefined

On 4/7/2023 10:05 PM, Farbin Fayza via gem5-users wrote: Could you kindly tell me if there's any way to run the gem5 simulation faster using multiple cores? Is it possible while we run SPEC? The only way is to run multiple distinct simulations in parallel. This can be done by directing their

[gem5-users] Re: Error in loading libprotobuf9

On 4/5/2023 1:25 PM, Ponda, Esha Ashish via gem5-users wrote: I tried to look into it and found that my OS has libprotobuf17 installed ./build/ARM/gem5.opt configs/example/arm/starter_se.py --cpu="minor" tests/test-progs/hello/bin/arm/linux/hello I am trying to run the above command and

[gem5-users] Re: Error in loading libprotobuf9

On 4/5/2023 9:59 AM, Ponda, Esha Ashish via gem5-users wrote: Hello, I have tried to install the libprotobuf9 package multiple times, yet it is showing this same error. Can anyone help me with this please? I think you need to research the right name for the *package* under whatever Linux

[gem5-users] Re: debugging python code inside GEM5

On 3/31/2023 3:26 AM, G via gem5-users wrote: Hello, GEM5 seems C++ wrapping Python, means C++ is on top. I can easily debug with gdb setting in VSCODE, but anyone knows how to debug into those emeded python codes? Such as se.py? Personally, I have found adding in print statements to do

[gem5-users] Re: what is the significance of hostMemory parameter in stats.txt file

On 3/30/2023 7:13 AM, Sadhana . via gem5-users wrote:   Can hostMemory parameter value be considered as the memory foot print size of an application. Does it include the memory occupied by the entire application. I believe it is the total memory of the simulated machine, and has nothing to

[gem5-users] CXL (Compute Express Link) in gem5?

I'm wondering what work has been done to model CXL in gem5. Is it something that can be modeled with existing gem5 components by adjusting their timing and other parameters, or would modeling it well require new components? From a quick high-level review of what CXL is (Wikipedia), I *think*

[gem5-users] Re: Retired instructions versus ticks

On 3/22/2023 12:09 PM, Priyanka Ankolekar via gem5-users wrote: Regarding the other part of your email: Let me begin by saying I am a novice to both RISCV and gem5. I have a RISCV RTL with a certain config. I have set up gem5 to match that configuration. I want to make sure that they are

[gem5-users] Re: Retired instructions versus ticks

On 3/22/2023 11:11 AM, Priyanka Ankolekar wrote: Sorry, I should have clarified. I am using the RISCV ISA in gem5. (As you could have done,) I checked the gem5 sources, and it *does* model that register, returning totalInsts as gem5 calculates that. Presumably that is the same as statistics

[gem5-users] Re: Retired instructions versus ticks

On 3/22/2023 8:37 AM, Priyanka Ankolekar via gem5-users wrote: Thank you, Eliot. Is there a way to probe minstret CSR to get the retired instructions? ?? What ISA are you talking about? I doubt that gem5 would model such details of a processor architecture. Maybe you should back up a

[gem5-users] Re: Retired instructions versus ticks

On 3/20/2023 5:05 PM, Priyanka Ankolekar via gem5-users wrote: Hi Eliot, (Picking this up again after a while.) :-) Thank you for your detailed answer. I was able to get a lot of useful data points from these statistics. Is there a way to get what instruction was retired/committed and when

[gem5-users] Re: Question about setting up to use NVM

On 3/18/2023 10:40 PM, Ayaz Akram via gem5-users wrote: Hi Eliot, MemCtrl() memory controller in gem5 can control a single DRAM interface or a single NVM interface at a time. I think one way to verify that things are set-up correctly is to confirm this from the "m5out/config.ini". If

[gem5-users] Question about setting up to use NVM

Dear gem5-ers - I wanted to set up to use NVM only, so I tried this on the command line: --nvm-type=NVM_2400_1x64 This had no effect. Digging into configs/common/MemConfig.py was not directly enlightening. However, it seems that Options.py sets mem-type to a particular DRAM by default.

[gem5-users] Re: Error: Can't find a working Python installation redux

On 3/15/2023 8:57 AM, Kar, Anurag Arunkumar via gem5-users wrote: Hi, I tried following previous archived threads which said the solution to this problem was to provide the path to  PYTHON_CONFIG and not using a conda environment. I am not using a conda environment and am providing the path

[gem5-users] Re: SPEC CPU2017 X86 SE mode - instruction 'palignr_Vdq_Wdq_Ib' unimplemented

On 3/13/2023 5:33 PM, Abitha Thyagarajan via gem5-users wrote: Hi Eliot and Mirco, I had the same issue with `palignr_Vdq_Wdq_Ib` being unimplemented. I tried compiling my application binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains that

[gem5-users] Re: Slowness when running SAT Solver in gem5 SE mode

Umm, it's a simulator, and you requested the most detailed simulation mode (DerivO3CPU). I expect slowdown factors of *at least* 1000 with such a mode. That you are seeing perhaps 4000-5000 does not surprise me all that much. The simulator has to do a lot of work for each simulated instruction.

[gem5-users] Re: error when running Z3 in SE mode on gem5

I think the key thing here might be the: "Resource temporarily unavailable" You seem to have exceeded some limited resource, perhaps available memory, number of processes (forks), or something like that. You may also have more success booting an actual kernel as opposed to running with

  1   2   >