[PATCH v2 11/37] clk: rockchip: rk3588: Use GPLL rate for CLK_TSADC

[Jonas Karlman]

Use the GPLL rate instead of using a hardcoded 100 MHz parent rate when
GPLL is parent of the CLK_TSADC clock.

Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
Changes in v2:
- Split from "rk3588: Fix trivial clock configuration errors"
- Add fixes tag
---
 drivers/clk/rockchip/clk_rk3588.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3588.c 
b/drivers/clk/rockchip/clk_rk3588.c
index b9fd4bec311b..a4fd3a57ad7f 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -655,7 +655,7 @@ static ulong rk3588_adc_get_clk(struct rk3588_clk_priv 
*priv, ulong clk_id)
                if (sel == CLK_TSADC_SEL_24M)
                        prate = OSC_HZ;
                else
-                       prate = 100 * MHz;
+                       prate = priv->gpll_hz;
                return DIV_TO_RATE(prate, div);
        default:
                return -ENOENT;
-- 
2.55.0