Keep the PPLL entry formatted in a similar way matching the other PLL entries for consistency.
Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Quentin Schulz <[email protected]> --- Changes in v2: - Split from "rk3528: Fix trivial clock configuration errors" - Collect r-b tag --- drivers/clk/rockchip/clk_rk3528.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index 82a1b6e85b5b..83e302dbc3c4 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -72,7 +72,8 @@ static struct rockchip_pll_clock rk3528_pll_clks[] = { RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates), [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32), - RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates), + RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, + rk3528_pll_rates), [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16), RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates), -- 2.55.0
