Re: [casper] fast serial communications: orientation to F-O options

Thanks Matt and John for your input. You have provided needed guidance for on the performance of copper cables. I may well give the Gore a try, I have no objection to paying less. I do wonder, though, if our good experience with 3 m lengths might be related to our use of Fujitsu (??).

[casper] approximate cost of next gen CASPER hardware

Can someone please advise rough numbers (which one might use in a funding proposal), for the cost to fabricate, assemble and test Roach PCBs? Please assume donated FPGAs, or break out their cost). This application does not not use large volumes, so assume a run of say 10 boards. Also,

Re: [casper] approximate cost of next gen CASPER hardware

same ADC, but it will have on board programmable gain/attenuator, and optional frequency synthesizer. we are also talking to agilent about using their 20 Gsps ADC. best wishes, dan Jonathan Weintroub wrote: Can someone please advise rough numbers (which one might use in a funding proposal

[casper] Virtex 5 power measurements

We want to estimate the power consumption of the FPGA only on a ROACH board. The idea is to isolate the FPGA's rail currents by looking at differences with the FPGA in an active state, and then suspended (i.e. starting and then killing a borph hardware process). The Actel monitoring

[casper] 1st Announcement: CASPER 2010, 16-20 August, CfA

of astronomy instrumentation by promoting design reuse through the development of platform- independent, open-source hardware and software. Please feel free to forward this message to colleagues who may be interested. We look forward to seeing you in Cambridge. Jonathan Weintroub, Lincoln

[casper] CASPER Workshop 2010: 2nd announcement

of platform- independent, open-source hardware and software. Please feel free to forward this message to colleagues who may be interested. We look forward to seeing you in Cambridge. Jonathan Weintroub, Lincoln Greenhill, Jim Moran and the SOC

[casper] 2010 Workshop Hotel Block Rates

Sorry to use the mailing list for this non-technical purpose. We have noticed that there are relatively few people signed up for the block rates at the CASPER workshop hotels relative to those registered. Please note that the block rate at the Hotel Tria expires tomorrow, Friday 16

[casper] 2010 Workshop Program posted

A program for the August 16 to 20 workshop has been posted at casper.berkeley. edu. A direct link to the pdf is: http://casper.berkeley.edu/CasperWorkshop2010Program.pdf We were able to schedule everyone who contributed or was invited to give an oral presentation (15+5 contributed, 25+5

[casper] thermal design of ROACH 2

I think that the ROACH design team does fairly sophisticated thermal analysis using a model of enclosure, PCB and cooling fans. Is this analysis available yet for ROACH 2 and where might I find some data? Is it possible extrapolate from the models (or perhaps rerun the models) to predict

[casper] wideband conversion and correlation

on this topic of high demux factors, the tool flow largely chokes on demux factors of 32 or greater. Any tips here would also be appreciated. If anyone can cast light on this general topic and related concerns it would be very much appreciated. Jonathan Weintroub SAO

Re: [casper] wideband conversion and correlation

the routing complexity, probably reducing the overall speed. But this is only my best guess, I haven't actually tried. -Suraj On Dec 23, 2010, at 4:47 PM, Jonathan Weintroub wrote: Hi CASPERites, Here's a somewhat fluffy RFI which I hope might start a little thought and/or discussion over

Re: [casper] Correlator meeting Tuesday Dec 21 9am M340

it would be very much appreciated. Jonathan Weintroub SAO

Re: [casper] wideband conversion and correlation

Dear all who responded, First, I apologize for inadvertently cc'ing the entire list with a message to my internal team. A consequence of using autocomplete in the cc field to make sure I got the list address right. Thankfully I think I only said nice things ;) Second, I really

[casper] India visas for Workshop

Dear CASPERites, Apologies for a non-technical posting. I want to share what I have learned about visas to visit India, and encourage people who plan to attend the workshop to start this process soon, as it is quite detailed, and the administration of it can be time consuming. I believe the

Re: [casper] KatADC

Hi Matt (and maybe Tom who started this thread last June), Further to Kim's note, we are also using the ASIAA e2v based board on ROACH 2, and we have already demonstrated 8 bit 5 GS/s quad interleaved operation on ROACH 2. It has two IF inputs, and can run in a dual channel 2.5 GS/s mode. The

Re: [casper] 1-2 GHz sampler

For the ASIAA designed 8-bit ADC using e2v EV8AQ160 at 5GS/s we at CfA (chiefly Bob Wilson, Nimesh Patel and Rurik Primiani) have done a fair amount of testing using both swept sine waves and wideband noise as input. There are measurements of frequency response, SFDR, THD, noise power ratio,

Re: [casper] 1-2 GHz sampler

For the ASIAA designed 8-bit ADC using e2v EV8AQ160 at 5GS/s we at CfA (chiefly Bob Wilson, Nimesh Patel and Rurik Primiani) have done a fair amount of testing using both swept sine waves and wideband noise as input. There are measurements of frequency response, SFDR, THD, noise power ratio,

Re: [casper] 1-2 GHz sampler

Hi Bill, Can you clarify: when you say you need an ADC clocked at 2048 MHz do you mean a sampling rate of 4096 MS/s or 2048 MS/s? (The ADC sample rate for some parts is twice the clock rate.) I'm a bit confused as to what you are after, looking back at your original framing of your problem,

Re: [casper] 1-2 GHz sampler

Hi Bill, There are measurements of the PCB with EV8AQ160 installed near DC posted on our Wiki: https://www.cfa.harvard.edu/twiki/bin/view/SMAwideband/MeasuringAndSettingParametersOfTheFourCores The plots are in terms of SINAD, linearly transformed to ENOB as follows. ENOB = (SINAD-1.76)/6.02

Re: [casper] ADC1X5000-8 correlator question

characterization and our resource memo. Cheers, stay in touch. Jonathan Weintroub CfA +1-617-495-7319 On Feb 12, 2013, at 4:09 PM, Ross Williamson wrote: Hi Dan and Glenn, All sounds good - I think have the ROACH-1 design will help us out a lot here to get started. We really don't need a very high

Re: [casper] July 21 Deadline for Casper Workshop Registration

page. http://estore.manchester.ac.uk/browse/product.asp?catid=282modid=2compid=1 This page is up and running, which I demonstrated by registering at the last possible minute myself. Please plan to submit your registration and pay the fee on time, which means today. Regards, Jonathan Weintroub

[casper] CASPER Workshop Reg. extended 1 wk due to web outage

All, From Ben Stappers, who is hosting the 2013 CASPER workshop in Manchester: == 22 July 2013 To all potential CASPER participants, we had an unfortunate web outage over the weekend that may have meant that some of you were unable to register for the meeting in Manchester in

Re: [casper] DRAM (DDR3) ROACH-2

Hi JP, Wes, We need the DDR3 rather urgently (time scale of 1 to 2 months), and Rurik Primiani has recently been working on it. Laura Vertatschitsch will be joining our group in September and we had her in mind to help with this too though recently concluded her start date isn't soon enough.

[casper] Matlab components for toolflow

Hi fellow CASPERians, This is a question that comes up periodically. At SAO we are now paying full fare for Matlab licenses so the cost impact of an imperfect understanding can be significant. The latest MSSGE wiki page is:

[casper] instrument postdoc opportunity

Dear CASPERites We just listed a SAO / EHT postdoc opportunity on AAS Job Register, that CASPER members might consider interesting. https://jobregister.aas.org/job_view?JobID=48318 Thanks for considering this. Jonathan

Re: [casper] Problem calibrating ADC for ROACH2

Hi Tom (and Ricardo), Thanks for the clarification, there was initially some question here as to whether the “calibration” you refer to is MMCM clock calibration (which sets up the ADC to ZDOK interface), or the quad core calibration. Based on your response you mean quad core calibration. In

Re: [casper] Starburst, an open-source 10gsps low-N correlator for ROACH2

Hi Ryan, That does look cool! You don’t mention which ADC you plan to use. Is it this one? https://casper.berkeley.edu/wiki/ADC1x5000-8 Just to mention in case it proves useful that our group at Submillimeter Array (SMA) and Event Horizon Telescope (EHT) has been working on a correlator /

Re: [casper] Starburst, an open-source 10gsps low-N correlator for ROACH2

relevant prior work in your PhD. For sure! The ADC work is extremely relevant and we couldn't do it without you. Best of luck with it. Jonathan and SMA / EHT team On Wed, Oct 29, 2014 at 5:34 PM, Jonathan Weintroub jweintr...@cfa.harvard.edu wrote: Hi Ryan, That does look cool! You

[casper] acknowledging CASPER in journal articles

Is there a standard text posted on the wiki to use in the acknowledgement section of papers? Most facilities have this. I could not find anything on the web page or Wiki though may have missed it. If there isn’t a text provided, I think there should be. Be happy to draft it if it doesn’t

Re: [casper] acknowledging CASPER in journal articles

, if you could draft something, that would be great. best, dan On Thu, Oct 30, 2014 at 2:38 PM, Jonathan Weintroub jweintr...@cfa.harvard.edu wrote: Is there a standard text posted on the wiki to use in the acknowledgement section of papers? Most facilities have this. I could

Re: [casper] acknowledging CASPER in journal articles

, if you could draft something, that would be great. best, dan On Thu, Oct 30, 2014 at 2:38 PM, Jonathan Weintroub jweintr...@cfa.harvard.edu wrote: Is there a standard text posted on the wiki to use in the acknowledgement section of papers? Most facilities have this. I could

[casper] 20 GSa/s ADC Proof of concept

Dear Casperites, I just cross-linked memo number 53 from the CASPER wiki memo page https://casper.berkeley.edu/wiki/Memos This memo documents an ultra high speed ADC board development by Rick Raffanti. The board, based on the Hittite HMC5913 3-bit single core flash ADC chip has been tested

[casper] inverse PFB

Hello CASPERites, Has anyone implemented an _inverse_ PFB? That is a block taking channelized PFB data and reproducing the original time series. If so, is the code/mdl/yellow block available? Thanks, Jonathan

Re: [casper] inverse PFB

, Jonathan Weintroub wrote: Hello CASPERites, Has anyone implemented an _inverse_ PFB? That is a block taking channelized PFB data and reproducing the original time series. If so, is the code/mdl/yellow block available? Thanks, Jonathan

Re: [casper] inverse PFB

experience implementing an inverse FFT relevant to this case, as a real time FPGA bit code? Thanks again. Jonathan Weintroub SAO On Dec 8, 2014, at 9:50 PM, Richard Shaw jr...@cita.utoronto.ca wrote: Hi, I thought I'd comment as this is a problem we've been having to deal with recently

Re: [casper] ADC1X26G

Hi Michael, I think is worthwhile to augment Rick’s response by noting that the premise of this project was a direct interface to SERDES transceivers, which required GTH generation transceiver—not available in Virtex 6 family (ROACH2). Hence the choice of VC709 platform with Virtex 7 as the

Re: [casper] XAUI LINK IBOB to IBOB

the following version of mlib-devel to compile the design: https://github.com/sma-wideband/mlib_devel/tree/vlbi-devel If you have any questions about the system or need more detail please email myself, Jonathan Weintroub, and Dave MacMahon. You should be able to find their emails on the list

Re: [casper] Issue Of The 1PPS Sync Singnal

Hi Peter, I have no input on operation of the PAPER bit code, just some tips on 1PPS distribution. Are you using a passive power divider of the type used for RF signals? Mini circuits or similar? This, or cascaded BNC or SMA T-s are not well suited to distributing multiple copies of a 1PPS

[casper] HMCAD5831 26 Gsps ADC, Analog Devices, formerly Hittite

For those using or interested in the fast ADC listed above, perhaps you are interested in the below pasted email fragment. I had heard rumors via multiple paths about the part possibly going out of production, and asked Robbie (who helped Rick Raffanti with the interfacing to Virtex 7 GTH

[casper] one-year DSP fellowship at CfA

, there is a way to fund registered graduate students at other universities for a predoc position (slightly less generous stipend). If you have interest, please send me an informal note, and we can explore in more detail. Thanks very much. Jonathan Weintroub

[casper] FPGA Vendor to consider

For those of CASPERites, especially those in the US, looking to purchase FPGAs, you might share my frustration that the price quoted by the Xilinx franchised distributors in the US (Avnet and Digikey) doesn’t seem to decay with time or quantity, nor it is easy in my experience to negotiate

Re: [casper] ROACH2 Power supply issue

An addendum to Alec’s note on a power supply mounting idea: At SAO we adopted the FSP250-60FAG power supply for our latest build of ROACH2s currently in process at Digicom. We also had trouble with the iStar (sometimes labelled XEAL), and have had better experience with the FSP> We came up

[casper] EHT Project Manager Opportunity

contact Shep Doeleman directly with any questions. Regards, Jonathan Weintroub eht_project_manager_open_position.pdf Description: Adobe PDF document

Re: [casper] progdev fail

This may be a partially imperfect recollection in the details: Laura Vertatschitsch worked on a DDR3 to CPU interface at SAO. However, after substantial effort, she still saw irreducible bit errors at some low rate, detectable with write-readback testing for extended time periods. I vaguely

Re: [casper] qdr cal

Hi Kim, We actually followed a recipe recommended by Jack Hickish, which worked first time. It involved cherry picking newer QDR bitcodes and software, and dropping them in to our build which is based on older libraries. This is Jack’s email: > On Fri, Sep 16, 2016 at 9:00 AM, Jack Hickish

Re: [casper] Configuring 40GbE Yellow Block in JASPER

My thanks to SA SKA, Peralex, and CASPER community for the support. Combined with Mark’s diligent efforts, we are now in a position to build, load, and run bitcodes, and to move data on and off the SKARAB with 40GigE. This means we have all the key infrastructure in place to start to develop

[casper] a few questions re our SKARAB interpolation design

Hi CASPER, SKARAB, JASPER collaborators, As much prior traffic has documented we are bring up SKARABs at SAO, and working on a fast rate interpolator design. After teething troubles with the SKARAB and JASPER Mark Peryer is now successfully building, loading and running codes on SKARAB. A few

[casper] Re: Xilinx License

Nice. Soon you will have a tool flow. You can try the tutorials here: https://casper.berkeley.edu/wiki/Tutorials And get help from the community: casper@lists.berkeley.edu Jonathan > On Jun 1, 2017, at 1:06 PM, Peryer, Mark A. > wrote: > > Hi Jonathan, > > I

Re: [casper] Unable to Load Firmware Image onto SKARAB

/edit?usp=sharing>). > This is what Jack Hickish sent to me at the beginning of the year explaining > the new mlib_devel directory structure. This is useful for Mark and anyone > else who is new to CASPER. > > This will be placed on GitHub before the CASPER 2017 conference.

Re: [casper] Unable to Load Firmware Image onto SKARAB

er reconfiguration. If the end user SDRAM image is corrupted > and/or is incorrectly set up to support further reconfiguration, then a power > cycle will cause the unit to fall back to the bootloader image (boot the > flash), and wait for new application code to be uploaded. > > Finally,

Re: [casper] Unable to Load Firmware Image onto SKARAB

ng mention of this protocol in the docs Adam supplied, there are no details. We may need Peralex expert support here. We are time constrained on this project and need to get rolling. Please advise, thanks! Jonathan Weintroub SAO On Wed, Jun 14, 2017 at 5:11 PM Wesley New <wes...@ska.ac.za> w

Re: [casper] Unable to Load Firmware Image onto SKARAB

gt; If you do then let me know and I will add them to the repo. > 5) Configure the flash, verify and then power off the board and see if the > 1GbE comes up. > > If you are still struggling then I will generate a proper How To document > tomorrow with graphics etc. I will probably

[casper] Re: Application of SMA correlator design to a larger array

Hi Dale, I’ll offer a few bullets on SWARM, the new SMA system. 1. SWARM is all open source and shared via CASPER and you are welcome to use it as is, or develop it further to adapt it to a new application, indeed it would be very pleasing to see the design used in some other instrument. 2.

[casper] Senior DSP Opportunity at CfA

tts-103229544-d> This one is a federal position, open only to US citizens. We are shortly going to post a similar “Trust” position open to all nationalities. Please consider it, and refer colleagues you think might be suited. Thanks, Jonathan Weintroub CfA, Cambridge, MA -- You re

Re: [casper] Red Hat Enterprise Linux--is it needed?

workshop/busy weeks, to make new and up to date tool flow documentation. Best wishes, Jonathan Weintroub > On Aug 1, 2018, at 3:50 AM, Heystek Grobler wrote: > > Hey Jonathan > > I am running two setups. > > The first one is Ubuntu 14.04 LTS with Xilinx ISE

Re: [casper] Inverse of fft_wideband_real

serial FFTs on a wideland input. > > I think? I haven't had coffee yet. > > Jack > > On Mon, 13 Aug 2018, 11:36 pm Alexander Raymond, > <mailto:alexander.raym...@cfa.harvard.edu>> wrote: > Dear CASPER List, > > I am a postdoc working with Jonathan Weint

Re: [casper] Inverse of fft_wideband_real

Thanks, Dave for the tutorial, and thanks, Jack. Jack you say: > On Aug 14, 2018, at 6:01 PM, Jack Hickish wrote: > > The biplex FFT which Dave mentions does all the 2 x real = 1 x complex > tricks. However, in the fft_wideband_real block, this is followed by a > parallel FFT direct block

Re: [casper] New Wideband Spectrometer Designs

Hi John, Homin and CASPER lists,I think most of the useful content has been expressed already, I’ll only state that my interest in ultra-fast ADC work continues, and I look forward to discussions at the workshop.  I’ll trot out my venerable table of high speed ADCs again, many of you have seen

[casper] science result of interest to various CASPERites

https://www.nature.com/articles/nature25792 (it is paywalled, and one isn’t really meant to send pdfs, but the News and Views piece by CASPER colleague Lincoln Greenhill isn’t: https://www.nature.com/articles/d41586-018-02310-9

[casper] Computer Engineer opportunity at CfA

, if anyone is interested and wants to ask questions about it please feel free to get in touch with me. https://www.cfa.harvard.edu/hr/postings/18-15.html <https://www.cfa.harvard.edu/hr/postings/18-15.html> Best wishes, Jonathan Weintroub -- You received this message because you are subs

Re: [casper] temporary ROACH2 faults after power dips and spikes

ng istar/xeal supplies getting into > strange situations that always seem fixable with a new power supply. > > Cheers, > Jonathon > > On 17 April 2018 at 16:22, Jonathan Weintroub <jweintr...@cfa.harvard.edu > <mailto:jweintr...@cfa.harvard.edu>> wrote: > Hi

Re: [casper] temporary ROACH2 faults after power dips and spikes

the ROACH 10GigE NIC ports? Thanks again. Jonathan & crew > On Apr 18, 2018, at 10:13 AM, Jonathan Weintroub <jweintr...@cfa.harvard.edu> > wrote: > > Hi Jonathon, > > Your important input here warrants cc to the mailing list, hereby > accomplished. > &

[casper] temporary ROACH2 faults after power dips and spikes

Hi CASPERites, With experience on quite a few ROACH2s in the lab and in the field for some years, and a pattern has emerged which warrants a question to the ROACH2 experts on this list. The SAO team has seen strange faults happen on multiple ROACH2 units after power failures, dips and

[casper] any updates to this document?

that is the latest version? Or whether it has been superseded by subsequent documentation? Or whether perhaps there are any useful supplements to this document. Thanks, regards, Jonathan Weintroub -- You received this message because you are subscribed to the Google Groups "c

[casper] save the dates: 2019 CASPER workshop

eded assistance, to be confirmed. Instructions for applying will become available once we have that in place. Thanks for your interest, and look forward to hosting CASPER in the Boston area. Best wishes, Jonathan Weintroub obo the 2019 Workshop LOC -- You received this message because

Re: [casper] 2-and-a-halfth Call: Aug 2019 CASPER Workshop & PIRE Summer School

there, and ask if you have any specific suggestions or ideas? Do you plan to attend the workshop, Thanks for your interest again and best wishes. Jonathan Weintroub > On May 15, 2019, at 3:43 PM, Langston, Glen wrote: > > Hi Jonathan, > > Thanks for organizing the

[casper] CASPER 2019 12-16 August Arrangements Update

du <mailto:casper2...@cfa.harvard.edu> if you have any. In particular those needing personalized invitation letters for visas can request via this address. Kind regards, and thanks very much again for your interest. Jonathan Weintroub obo LOC and SOC Center for Astrophysics | Harvard an

[casper] Aug. 2019 Workshop @ CfA: Travel Support

available at that time. We will acknowledge applications, so let us know if you don’t receive such acknowledgment. As a heads up we plan posting block hotel recommendations and rates in the next couple of days. Thanks for your interest, and look forward to hearing from interested folks. Best wishes,

[casper] job opportunity at SAO/CfA

it is open to those who are NOT citizens of the United States. Please consider it, and if you have particular questions, please ask me. Regards, Jonathan Weintroub obo EHT -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group.

[casper] 2-and-a-halfth Call: Aug 2019 CASPER Workshop & PIRE Summer School

ne (Univ. Arizona PIRE) Alex Raymond Jonathan Weintroub -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.

[casper] 2nd Call: Aug 2019 CASPER Workshop & PIRE Summer School

ee Tina Arabadjis Shep Doeleman Lincoln Greenhill Jenine Humber Rosie Johnson (Univ. Arizona PIRE) Dan Marrone (Univ. Arizona PIRE) Alex Raymond Jonathan Weintroub -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe fr

[casper] EHT result announcement

?cntn_id=298155 (in all six there will press conferences simultaneously around the world) More on the EHT here: www.eventhorizontelescope.org <http://www.eventhorizontelescope.org/> Best wishes, Jonathan Weintroub -- You received this message because you are subscribed to the Google

Re: [casper] CASPER PIRE 2019 Workshop Slides/Video

their material posted. Just give it a couple weeks. I’ll be sure to let everyone know when the material goes up. Thanks very much, Jonathan Weintroub > On Aug 19, 2019, at 8:51 PM, Gustavo Guadalupe Rodriguez > wrote: > > Hello, > > I was wondering when/where one can access the

Re: [casper] Congrats to the Event Horizon Telescope Team!

a the wonderfully supportive and unselfish culture which seems to permeate CASPER. Sincere thanks to all of you, you helped make the EHT folks look good. Jonathan Weintroub > On Sep 5, 2019, at 2:19 PM, Jack Hickish wrote: > > Hi CASPERites, > > Some of you may have seen t

Re: [casper] casperites receive breakthough prize

casperites, >> >> several casper people received the breakthrough prize today for making the >> first image of a black hole, >> including jonathan weintroub, homin jiang, nimish patel, matt dexter, arash >> roshanineshat, laura vertaschitsch, and casper co-founder mel

[casper] collaboration meeting reminders

<https://www.cfa.harvard.edu/events/2019/casper/CASPER2019_files/agenda.html> and there is a link there to the block schedule. Thanks for your interest, and best wishes, Jonathan Weintroub obo CASPER 2019 LOC -- You received this message because you are subscribed to the Google Gro

Re: [casper] CASPER PIRE 2019 Workshop Slides/Video

Hi Talon, Gus, and all CASPERites We’re working on it. It seems clear my "couple weeks” was an underestimate. It’s more work than anticipated to put this all together. The push is appreciated, though, it will help get us moving. Best wishes, Jonathan Weintroub obo CASPER2019 LOC >

[casper] Project/System Engineering position at SAO

sition, this position is open to non-US citizens. Thanks for your interest. Jonathan Weintroub -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to

Re: [EXTERNAL] [casper] Intel/Altera 64GSps DAC/ADC

Hi Dave, Thanks for this great tip. Can Robert ask about ballpark pricing for this Intel SoC? Best wishes, Jonathan Weintroub > On Feb 3, 2021, at 4:40 PM, 'Hawkins, David W (US 334B)' via > casper@lists.berkeley.edu wrote: > > Hi All, > > Robert Jarnot will try to c

[casper] videos from CASPER W/S and BH PIRE DSP School 2019!

wishes, CASPER 2019 and BH PIRE DSP Summer School LOC Rosie Johnson, Dan Marrone, Alex Raymond, Arash Roshanineshat, Lincoln Greenhill, Shep Doeleman Tina Arabadjis, and Jonathan Weintroub https://www.cfa.harvard.edu/events/2019/casper/ <https://www.cfa.harvard.edu/events/2019/casper/> --

[casper] truly spectacular!

https://arxiv.org/pdf/2201.10541.pdf https://www.nytimes.com/2022/01/31/science/milky-way.html?auth=login-email=email Well done SARAO and CASPER and all involved.

Re: [casper] state of the art single bit correlators

Hi Neil, Dan, That would be the thesis of the brilliant Curtis Mead, downloadable here: https://dash.harvard.edu/handle/1/11158246 Jono > On Nov 13, 2023, at 8:56 AM, Dan Werthimer wrote: > > > hi neil, > > paul horowitz, at harvard, had a PhD student who characterized and used FPGA >

Re: [casper] viability of VCU128 eval board as production CASPER instrument

e put the HiTech Global HTG940 and HTG9200 boards into the CASPER >> library if either of those was useful. >> >> I would definitely recommend looking at Alpha Data as well - I've had good >> experiences with them so far, and I've recently put the ADA-SDEV-3 into &g

[casper] viability of VCU128 eval board as production CASPER instrument

rong. But I hope the intent here is clear, not to get into the nitty gritty right away, but rather to discuss the bigger picture of viability of use of eval boards. Thanks for reading and thinking about this, and best wishes, Jonathan Weintroub -- You received this message because

Re: [casper] RA Instruments using CASPER hardware and tools

Ciao Morag, It is not a full CASPER instrument, so maybe a marginal case: the ALMA Phasing System (APS) is a retrofit of a VLBI beam forming capability to the non-VLBI capable ALMA Correlator,

[casper] save the Holmdel CMB Horn

CASPERite, Greg Wright, doing a fine job. Thanks for considering, and thanks to Nimesh Patel for bringing the petition to my attention. I hope it works. Jonathan Weintroub https://actionnetwork.org/petitions/save-big-bang-antenna/ -- You received this message because you are subscribed

[casper] Ethernet speed interoperability interoperability

Hi CASPERites, I believe that 40 Gbps Ethernet interoperates rather transparently with 10 Gbps. Because the 40 Gbps is arranged as four x 10 G lanes, so its possibly to break a 40 QSFP port into four 10 SFP+ with a suitable breakout cable. Or with proper packet addressing via a network

Re: [casper] Ethernet speed interoperability

route if interested? But it is old technology and > probably hard to come by? > > Best, > > Mitch > >> On Nov 30, 2022, at 9:09 AM, 'Jonathan Weintroub' via >> casper@lists.berkeley.edu wrote: >> >> Hi CASPERites, >> >> I believe that 40 G

Re: [casper] Ethernet speed interoperability

Hi Jack, Thanks for weighing in. Actually your answer doesn’t read as the same one that Mitch gave. Further clarification: > On Nov 30, 2022, at 3:08 PM, Jack Hickish wrote: > > Yes, I think that's probably right. There are old standards which probably > allow you to passively convert a

Re: [casper] Ethernet speed interoperability

Thanks also for this information, Greg, also helps and I very much appreciate it. Best wishes, Jonathan > On Nov 30, 2022, at 7:16 PM, Greg Lindahl wrote: > > Jono, > > The secret is that none of this autonegotiates. You have to set the > link speed and the link width explicitly on the