On 03:50 PM 21/11/2001 -0500, [EMAIL PROTECTED] said: >Mr. Lomax >I would hesitate to let the pcb routing dictate the FPGA configuration. It >has been my experience in the past that this can result in disastrous >synthesis. I would suggest that unless you have full control over the FPGA >simulation, synthesis and layout, that it is best to let the FPGA >programming (Xilinx Foundation or fascimile) dictate what pins get connected >to what signal. >Regards, >Lloyd Good
I agree, Lloyd. It is rare to find a programmable logic architecture that is completely non-blocking or has no limits on product terms or expanders etc. So I always let the fitter do the initial pin allocation. Problem is I am not convinced that all the fitters will try to optimize resource usage once they have achieved a fit. So, the pin allocation given by the initial fit may not be the most optimum in terms of maximizing future expandability anyway. The above is especially true on fast deterministic CPLDs rather than the more flexible but less deterministic FPGAs - at least that is my experience, I am sure some experts will correct me. But all that said I let the fitter determine initial pin allocation and then carefully inspect the allocations and equations and used share-able expanders etc before locking down the PCB. Any change on the PCB pinning is done only after the effect on the timing and fit is evaluated by running the proposed change through the CPLD/FPGA tool first. Ian Wilson Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
