At 11:08 AM 7/2/2002 -0700, Tony Karavidas wrote:
>I was thinking about this for a moment and it occurred to me that if a 
>given CPU has a 90+ % level 2 cache hit
>success, that means <10% of the time there is a cache miss and the system 
>is forced to go out to the main memory for a piece of data/instruction

I'm just curious.  How did you arrive at these figures for L2 cache 
hits/misses?
Wouldn't you expect this ratio to be quite optimistic from the cache point 
of view?



Frank Gilley
Dell-Star Technologies
(918) 838-1973 Phone
(918) 838-8814 Fax
[EMAIL PROTECTED]
http://www.dellstar.com


************************************************************************
* Tracking #: 6CB85C9D631D724FA016D42BD7D2200C7EC421DF
*
************************************************************************

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to