At 04:35 PM 1/6/2004, you wrote:
   This is the way I usually work.  As discovered by some of the EDA
readers here a year or so back, my default clearance design rule is '0' by
default.  My silkscreen within my public online custom library exactly
defines the outer physical restrictions for it's component placement.  As
mentioned back then, I specialized in hand-held electronic devices where
super compact placement was the main goal.  It turns out that the 0
clearance rule ended up being useful with all of my design work.

From way back, I developed a habit of designing related sections at maximum density even if there was plenty of room on a PCB. Now, I didn't actually use true maximum density; typically axial leaded-components like quarter-watt and eighth-watt resistors would be on a 100 mil grid instead of really pressed together. There is rarely an advantage to spreading out components, and if you ever want to add something to the board, if you have spread components out, you may have a lot of work to do.... With components at maximum density, in sections with perhaps a little room between them, you can move a section over or move a component to the outside of the section to make room for something new.

I developed the habit in the tape-and-mylar days when redesign was even more of a pain....

If I'm placing a board, and there is room left over, it is not a problem. If I run out of room, it is very much a problem.... So I design dense. Then, when I'm done, and the client asks "Can we make the board smaller?", I can usually give a solid answer without any difficulty.

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