> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] 
> Sent: Tuesday, May 04, 2004 5:07 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Connectivity - Netlist issues
> 
> At 09:58 AM 5/4/2004, John A. Ross [Design] wrote:
> > snip <<

> You have Descend into Sheet Parts enabled. This is not what 
> you might expect from the name. A Sheet Part is a sub sheet 
> that descends from a component. I've never used one, and you 
> probably aren't either. But this setting can cause a number 
> of weird problems, depending perhaps on the components you have used.

I left "append sheet no to.." alone, I already tried that.

I had already tried unchecking 'Descend into sheet parts' before and it
made no difference either.

So I first tried committing the changes anyway and repeating the netlist
load again, no difference, after unchecking 'Descend into sheet parts' I
once again committed the changes anyway, despite the error, and on the
second netlist load it worked.

Seems 'Descend into sheet parts' being checked does produce
unpredictable behaviour.

I have never used sheet parts, I see them as an avoidable evil :-) and
the design does not use them, I would have expected this setting to be
benign.

But sheet parts seem to play a bigger role in 2004.....

> You might also enable Append Sheet Numbers to Local Nets. 
> With the connectivity you are using, you don't intend for any 
> local nets to be connected to a local net of the same name on 
> the other sheet. What Protel will do, as I recall, if such 
> nets exist, is to create separate nets in the netlist, with 
> the same name. This can also cause weird problems.... This 
> may be related, if for some reason Protel is not recognising 
> your power ports as global. At least you'll know!

I already guessed this was the case as although I have had issues with
the updater, the raw netlist load always seemed reliable as far as error
reporting goes.

A lot of the child sheets in this design are reuse blocks for me so each
net has its own name and each part has its own Cref (frozen across
designs) so I can pick up the pre-laid out PCB block and dump it in. For
these type designs I rarely use Protel assigned net name for a lot of
the child sheets.
 
John


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