> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] 
> Sent: Tuesday, May 04, 2004 8:28 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Connectivity - Netlist issues
> At 01:17 PM 5/4/2004, John A. Ross [Design] wrote:
> >I am still getting some ERC errors on some pins connected to power 
> >objects in the ERC. These errors now match up to 
> corresponding netlist 
> >import errors 'net already exists'
> >
> >The issue seems to be where there is only one power object 
> of the same 
> >net on a sheet. Its as if these pin/power port connections are being 
> >treated like single pin nets on a sheet level and not connected 
> >globally.
> Yes, looks like that.
> >See sheet contents
> >http://www.proteluser.com/bbs/showthread.php?p=72#post72
> >
> >#2 Error   Unconnected Passive Pin On Net 3V3A
> >    ID KEY.SCH(R400-2 @870,665)
> >#13 Error   Unconnected Power Pin On Net GND
> >    ID KEY.SCH(U402-1 @970,460)
> You aren't getting a floating power port error (I assume), 
> which is significant. This means that Protel is treating the 
> passive pins as connected to the power port, but the power 
> port is, as you suspect, not being treated globally.

No floating pport errors are reported, pin types are correct.

The ERC and netlist errors I have seen, definitely appear to be the
results of only having a single power object on the sheet.

If I add a 100n cap onto the same sheet and add 3v3a and gnd ports the
error goes away.

When the netlist is loaded, connectivity is broken on the PCB, which
using my previous OTT approach of breaking out power connectivity via
ports/sheet entries never occurred. I have a vague recollection that I
started connecting power rails via sheet entry/ports because of this but
P98 was so long ago now.

However I made a small test board, parent + 5 child sheets using the
same ID key.sch file in it and it does not show the error under the same
enviroment so the problem seems localised to the other design (or the
number of sheets).

If anyone has any more insights please let me know.


> Now, I'd never run an ERC report in DXP. What I ran into 
> trying to check all this out is typical of what happens to a 
> 99SE user. Do I need to go over all the gory details? First 
> of all, ERC is automatic, when a design is Compiled. I used 
> the example design 4 Port Serial Interface. When I do 
> Project/Compile Document 4 Port Serial Interface.SchDoc, I 
> get a pile of
> error: duplicate net name messages. There are 13 wires on the 
> top level, there are 12 duplicate net name messages. I don't 
> see any error markers created.
> If I place net names on the wires on the top level, then I 
> get no messages. 

I always place net labels on all wires & buses on the top level sheet

> That in itself is a problem: how do I know that Compile 
> executed? (But if I move a net label off of its wire, I do 
> get the appropriate errors). But no error markers. Why not?

> At this point, I'm out of time.... It can take *hours* to try 
> to figure out the simplest things in DXP:
> How to generate an error report (I still don't know how; I 
> see error Messages but not a report document.)
> How to create or control the creation of error markers (I 
> know where the error matrix is, but don't know why markers 
> are not being created when messages *are* being sent 
> regarding errors).
> How to get the Compile function to verify the whole project 
> (i.e., parent plus child sheets) instead of just checking the 
> parent sheet. (I created an error on a child sheet and ran 
> Compile on the top level, no error message was generated. 
> With net lists, there is an option to generate the net list 
> from the project or just from the current document.) And this 
> goes on and on....
> Yes, I do need a book: DXP, a Manual for the Compleat Idiot. 
> (All this stuff was *easy* in Protel 98/99. Yes, users often 
> had questions, but many of the questions were simply a matter 
> of overlooking what was relatively obvious; I don't recall 
> anything like this mind-boggling sense of helplessness when 
> learning Protel 98. Most of the questions in Protel 98/99 
> were about the ins and outs of connectivity, which can take 
> some time to understand, and there were some quirky behaviors.)
> On the other hand, there are some really great new 
> features.... and I mean that. Placing Net Labels on the top 
> level sheet was easier, because there is a look-ahead 
> analyzer of what is typed which means that if you type enough 
> characters of an existing net name, you don't need to 
> complete it; plus there is a pull down menu and a memory of 
> the last label placed, so it was easy to, for example, place 
> the series of names INTA, INTB, INTC, INTD, it was really 
> just a few mouse clicks.... (The memory was there before, but 
> not the lookahead and pull-down menus.)

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