> -----Original Message-----
> From: Ian Wilson [mailto:[EMAIL PROTECTED] 
> Sent: Thursday, May 06, 2004 12:21 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Connectivity - Netlist issues
> snip <

> John - I have been trying to follow this thread but I have 
> had little to offer.  Power ports not acting as simple global 
> nets is not something I have ever seen in P99SE.
> Just some random ideas ...
> Have you tried changing the names of the power nets? In 
> particular have you tried making your power nets something 
> like V5 rather than +5, that is not a valid looking number. 
> (This is a loooong shot and is not a problem I have ever 
> noticed in P99SE.)


I never use operators as part of net or power port names, always like 3V3A, 5D, 12V, 
12VV and so on.

It is habit as other tools I use do not like things like +5V etc. 
I guess from your comments Protel can have issues with this as well? 

> You say it seems to be specific to one design, suggesting 
> either that your simplified small test does not exactly 
> represent the problem case or it is something broken in the 
> original.  If you can track it down to the presence or 
> absence of one specific sheet or port or power object etc 
> that may offer some insight.

The error marker showed the error on the id key.sch sheet, but I reckon that's bogus. 
I made a small
5 sheet design and used the same sheet 'as is' and the design worked as expected, all 
power ports

I can remember some issues before on how the ERC engine marks errors, i.e. not always 
at the cause
of the error but at the first point of conflict it finds depending on the position in 
the netlist
when parsed. So if the object causing the error was in the list first, then a valid
connection/object would be flagged as the duplication error instead even although it 
is OK.
Hopefully I got this theory right.

> What happens if you do load it into P2004 and then use the 
> Navigator to inspect the netlist and hierarchy?  Does it look right?

More or less I was thinking along these lines as the sheets may have been re-ordered 
at some point
as other people have worked on the design as well.

The top sheet shows all the child sheets under it correctly after the first compile, 
but the amount
of errors is unacceptable, it should be cleaner than that. 
Hence reason I stopped and re-evaluated making the designs 'DXP import friendly' first.

There is a bit of pressure on me just now on other projects so I might be overlooking 
obvious, too much haste is usually counter productive. 

As I said in the other post, I am suspicious of an error on another sheet, perhaps 
some hidden
object or net label being existing with a POE landing on an existing net or pin (spot 
the junction
time) which is already connected to a power port somewhere and therefore trying to 
name the net


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