Re: [PEDA] Upgrade to DXP
In light of the recent thread on upgrading to DXP I would like to ask the question of those who have (and possibly those that didn't) regarding sharing your files with us Protel 99SE people i.e. Having done your DXP pcb/schematics you need to share them with us 99SE users. How confident can you/we be that ALL the important information is preserved. I would grossly resent being forced to pay AUS$10,000 for DXP just so that I can read the files created by other DXPers. This is a tactic that Microsoft use with stuff like their Office Suite and is not the way to keep good favour. I ask the question because my company supports a number of customers pcb designs (we are a pcb stuffer) and some are now using DXP whilst others use 99SE. We currently use 99SE internally and would prefer to stay with it for now but have had concern from the DXP customers as to the problems they have exporting and whether the 99SE files we get are reliable enough for us to work on. Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] CSV XLS Reports
Thanks Ian for what turned out to be a very simple and easy fix. Typical!, search the KB for something you want and you can't find it. Don't even bother looking and that is where the answer is!!! Once again thanks. Best Regards Laurie Biddulph http://www.elby-designs.com - Original Message - From: Ian Wilson To: Protel EDA Forum Sent: Thursday, May 13, 2004 8:06 PM Subject: Re: [PEDA] CSV XLS Reports On 05:53 PM 13/05/2004, Laurie Biddulph said: I have for some time now been using Protels own format for BOMs but need to re-create some in either CSV or XLS format. I used to do this in the past but now Protel 99SE SP6 reports a TIF1 license problem and virtually locks up. Has anyone come across this problem and/or has a resolution for it? Am running on Windows 2000 with Excel 97 which has worked fine in the past. See this KB item: http://www.altium.com/protel/kb/kb_item.asp?ID=1701 There are other ways of re-installing the specific server that are not talked about in this KB article that save re-installing the whole application. If you click the client menu (the arrow next to File) and click the Servers entry, you should be able to uninstall and the problem servers - not sure which one but probably SchBOM or something like that. Right click on the server you want to uninstall. The you can install it again. The servers will all (generally) be in the System folder og the P99Se install path. You will then need to work out what is the correct INS file. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] CSV XLS Reports
I have for some time now been using Protels own format for BOMs but need to re-create some in either CSV or XLS format. I used to do this in the past but now Protel 99SE SP6 reports a TIF1 license problem and virtually locks up. Has anyone come across this problem and/or has a resolution for it? Am running on Windows 2000 with Excel 97 which has worked fine in the past. Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] logo in template does not show
The problem is that the logo must be in the same folder as the DDB file(s). You will find that if you keep a common folder of all your DDB files along with the logo that it will load every time. If you then go and open a DDB in a different folder ten the next time Protel opens it will have been pointed to the new folder and as the logo is not there it will give the message you gave. This is one of the bugs in Protel that despite having been told where the logo is in your `Preferences' it still ends up looking in the current folder for the file. So either keep a common folder for all your DDB files (thats the way I do it) or put a copy of your logo in every folder where you have a DDB. This works with the Preferences fine. If you need to open/create a new DDB (even if it is only temporary) then make sure you create/place it in this common folder Best Regards Laurie Biddulph http://www.elby-designs.com - Original Message - From: Leo Potjewijd To: [EMAIL PROTECTED] Sent: Wednesday, May 12, 2004 2:09 AM Subject: [PEDA] logo in template does not show While experimenting with templates in P99SEsp6 I find that an included logo (BMP image) does not always show up. If the Ddb with the templates is open, all is well. If I close that Ddb and keep the design open the logo still shows, but when I open the design the next day (and keep the templates Ddb closed) the logo is replaced with the text Logo IE.bmp file not found. The rest of the template shows up just fine. I have imported the BMP file into the design Ddb: no success. Design-Template-Update produces a 'file format not recognised' error. When I use Design-Template-SetTemplateFilename and reselect the template from the templates Ddb the logo shows up again, even on sheets and Ddbs that are opened afterwards. Closing the templates Ddb makes no difference. The handbook is not really clear on this subject, nor is the online help so I suspect I missed something essential. Can any of you guys point me in the correct direction? Any input is greatly appreceated. Leo Potjewijd hardware designer Integrated Engineering B.V. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Auto router Can't Initialize error
I run Protel 99SE SP6 on Win2000, on the few occasion this has happened to me it was because I had a component outside the keepout boundary at the edge of the board (this occurs when you update the pcb with some new components, Protel dumps on the lower right-hand side outside the pcb area. Best Regards Laurie Biddulph http://www.elby-designs.com - Original Message - From: Ray Mitchell To: [EMAIL PROTECTED] Sent: Thursday, May 06, 2004 6:03 AM Subject: [PEDA] Auto router Can't Initialize error I'm running Protel 99SE SP6 on Windows XP. Sometimes when I try to start the auto router I get a Can't Initialize error. This most often occurs if I'm trying to autoroute a specific net, but I'm also now getting it when trying to autoroute All. I have a bunch of manual pre-routes I don't want to lose, otherwise I'd just unroute the whole thing and start over. Any suggestions? Thanks Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] reg deleting dcocuments
Hello Paresh, Firstly, make sure that none of the files in the project are open (i.e. there are no tabs for any of the schematics or pcbs in the right-hand windows). If there are then yo will get a similar message to the effect that the `documents are in use by xx'. On a single-user system is usually you. You should now only have one tab left in the right-hand window and this will be the main project tab. You can now right-click on the tab and select close. Best Regards Laurie Biddulph http://www.elby-designs.com - Original Message - From: Paresh Pai To: protel forum Sent: Sunday, March 21, 2004 3:23 AM Subject: [PEDA] reg deleting dcocuments Hi everybody. This is regarding Protel99SE SP6 on a single user PC. If I want to delete a document from the design database, I am unable to do so since after I right click on the document icon in the explorer , I do not get a delete option in the context menu that appears. I tried to give all rights to all members such as Guest etc. Also, if I try to drag the document to the Recycle bin, I get an error Cannot perform delete operation.Document is currently in use by Admin on MYPC.It looks as if the system is not recognising me as Admin. Thanks in advance. Paresh Pai * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Hardware
Hello, Following on from the recent thread on identifying components with Company part numbers etc I would like your feedback on how you handle hardware. A pcb/schematic may include, for example, some TO-220 voltage regulators that require a heatsink, a nut and a bolt. I would like Protel to include these automatically in its BOM which I currently do by creating a simple symbol for a `piece' of hardware and then put a description like M3 x 8mm bolt in the Part Type. This way all the parts are grouped together (10 x nuts, 10 x bolts etc) and this works well especially as each type has a Part Number associated with it. The only problem I have is how to present these parts on my schematics so that they are associated with a specific component (these nuts and bolts on U1 while those are on U2 etc) without cluttering the schematic with `simple symbols' and long-winded descriptions. Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Transparent footprints
Thanks to everyone who responded. Sat down this morning to test out the various suggestions. Before doing this I decided to make up the two component footprints and was surprised to find that I could place them on to a pcb AND place components `under' them without any problems at all. Wasn't sure why this was the case at first as I had based the assumption of the potential problem on the fact that you can't put two resistors or capacitors together without getting a conflict. Realised soon after that Protel ignores the component outline (which is on the Top Overlay Layer) taking note only of the pads. So you can freely place pads or components with in another component as long as you do not infringe the pad clearance rules. This works perfect for what I need (an LCD module with four fixing holes and a 16-way SIL connector, and a 4x4 keypad with four fixing holes and an 8-way SIL connector. I can appreciate that if the components had considerably more `pad content' that there would be a bigger problem in trying to position other components. The only drawback with this approach is that when selecting components within the footprint you get the `popup select component dialog' more an inconvenience than anything else. Once again thanks to all those who responded. Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Transparent footprints
Hi, I hope you all had a happy Xmas. I need to place two large components on a pcb that will actually be on spacers and connected to the main board by short wire links. As the items are relatively large (one of them is one of those standard 2- or 4-line LCD modules) the footprint for these will be quite large yet be basically empty - there will be four spacers, one for each corner, plus a short multi-way connector. Is there any way of creating this as a component footprint so that it may be correctly moved and position on the main board yet still allow Protel to freely place components and tracks in the free area under these components? As the position of the spacers relative to the connector is fairly critical it is preferable that this is one single component. Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Power supply pins
Hello and thank you for your extensive response.
I do apologise for not getting back to you earlier but have been fairly busy.
I think it is generally good practise to always have EVERY pin exposed even power
supply pins but I do feel that putting the power pins off to one side is a neater way
than having as part of a main component symbol. The only problem I have found so far,
and I can't explain why, is that putting the power parts on to a separate page
resulted in Protel wanting to add a complete extra chip to the pcb when I did an
update.
I will study your other comments but am often amazed at how much extra work one has to
do sometimes to achieve a basic feature - not bad for ASU$9000!
Best Regards
Laurie Biddulph
http://www.elby-designs.com
- Original Message -
From: Abd ul-Rahman Lomax
To: Protel EDA Forum
Sent: Friday, December 12, 2003 5:07 AM
Subject: Re: [PEDA] Power supply pins
{this message bounced first time, outgoing mail server couldn't find
techservinc.com)
At 06:10 AM 12/10/2003, Laurie Biddulph wrote:
I hate having power supply pins as part of schematic component symbols
(especially opamps and logic gate chips). I prefer to create an additional
`component part' in the chip purely for the power supply pins. This makes
it easier to assign decoupling components to the chip as well as reduce
clutter in the main part of the schematic.
This is a very legitimate way of dealing with the problem, as is having the
power pins be part of the symbol. Hidden pins have restricted application,
some say that they should never be used, but that goes too far. If you have
a digital design with standard logic, hiding the power pins may be acceptable.
However, if a technician is going to have any difficulty later figuring out
which pin on a part is, for example, ground, it is better to be explicit.
Making symbols with power pins as a separate part of the symbol, while it
is a little more complex -- in creating the symbols -- is really the best
of both worlds. All the power parts can be placed on a page -- or part of a
schematic page -- which shows power nets and bypass cap allocations. This
leaves the rest of the schematic for signal flow and logic, and not having
to deal with power connections and bypass on those pages saves both time
and space, and results in a schematic that is easier to read. The only
negative I can think of is that in a split-supply design the power
assignments are not necessarily on the same page so an error in assignment
might be less obvious.
I consider the improvement in general readability to outweight that; it
just requires a little more caution, since, so far, there is no ERC for this.
(If component classes could be set up in schematic and assigned power
supply classes, ERC would be possible, where a component was assigned the
incorrect power supply, i.e., an analog part gets a digital supply. This,
by the way, is a very common error in designs we receive as a service
bureau, and we do try to notice it and query the engineer.)
Problem is Protel 99 doesn't like annotating these as it treats the
power part as a real part and really gets messed up. I believe Protel DXP
lets you assign the power supply pins to Part 0 and so, presumably, gets
round the problem.
I haven't looked into that aspect of DXP yet. The problem in P99 (and
earlier) is only with automatic annotation. I think one could get around
the problem by having two libraries: one would be the components with no
power pins (or with them as part of the main symbols), the other would have
the same parts with power pins removed. The schematic would be drawn, at
first, with the parts from the first library, and annotated. Then the
symbols would all be updated from the second library, and then the power
page would be added to the schematic. There are some caveats with updating
symbols, but I'm a bit rusty on that topic
Beyond that, manually assigning parts is normally not such a huge task. If
there is a way in DXP to exclude a symbol part from the autoannotation
task, this would indeed be an improvement.
But there is usually manual attention needed to annotation, to cluster
logic functions, for example, on the same device so that signals remain
local instead of running across the board and back just to run through an
inverter. I'll often allow a few sections to be unused, more than the
absolute minimum, just to keep signals together. Logic functions are
generally cheap.
Hiding power pins is bad news especially if you use different power rails
from, say, VCC and GND which are the common defaults for logic chips and
so if you forget to unhide them you end up with a power net not going
anywhere near your real power supply.
Protel does not handle this probem as well as DOS Tango did. Tango allowed
sheet-wise net
[PEDA] GND planes
If a double-sided pcb has a very large DIGITAL GND net and a small ANALOG GND net would you connect the two GROUND planes created on the two layers to the DGND or AGND? Connecting DGND would mean better current handling and thus presumably reduce digital noise but would the large plane then act as an transmitter to the AGND? Connecting AGND would mean a cleaner audio path but would it then act as an aerial to all of the DGND nets on the board? The application is an audio synth using, fundamentally, digital components (for the VCOs, Noise and controllers) but linear devices for the final audio paths (VCF, VCA and audio output). Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Power supply pins
I hate having power supply pins as part of schematic component symbols (especially opamps and logic gate chips). I prefer to create an additional `component part' in the chip purely for the power supply pins. This makes it easier to assign decoupling components to the chip as well as reduce clutter in the main part of the schematic. Problem is Protel 99 doesn't like annotating these as it treats the power part as a real part and really gets messed up. I believe Protel DXP lets you assign the power supply pins to Part 0 and so, presumably, gets round the problem. Hiding power pins is bad news especially if you use different power rails from, say, VCC and GND which are the common defaults for logic chips and so if you forget to unhide them you end up with a power net not going anywhere near your real power supply. Is there any recommended method in Protel 99 of handling the power pins on logic chips similar to my first method above that Protel 99 can handle comfortably? Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] GND Planes
If a double-sided pcb has a very large DIGITAL GND net and a small ANALOG GND net would you connect the two GROUND planes created on the two layers to the DGND or AGND? Connecting DGND would mean better current handling and thus presumably reduce digital noise but would the large plane then act as an transmitter to the AGND? Connecting AGND would mean a cleaner audio path but would it then act as an aerial to all of the DGND nets on the board? The application is an audio synth using, fundamentally, digital components (for the VCOs, Noise and controllers) but linear devices for the final audio paths (VCF, VCA and audio output). Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Stock Components/Joining nets - now autorouting
I have spent a fair bit of time trying to `tweak' the rules but seem to reap very little improvement. When using 98 we often do several runs using the last run to make adjustments to component positions etc until we get a pretty good result that we then manually finish off (Have yet to see a Protel finished board that even comes close to being `clean' without manual intervention!). 99 for some reason has consistently taken many hours (and I mean anywhere from 5 to 20!!!) and not yet given us a single complete route even though 98 does so regularly. Today, DXP took over 2 hours to route two tracks on a board that has been previously routed to about 90% completion - that correlates to about 780 routed tracks out of a total of around 840 - and we have given it two empty layers (the pre-routed board is 4-layers and now we have made it a 6-layer board). Having said this. Running 99 in my home office (with considerably smaller boards) I have no, apparent, problems. Getting to the stage where we might throw the file at Protel and get them to explain the problem. We have just forked out our $9000 for DXP and would expect considerably better results than we are seeing at the moment. Anything on the site that tickles your fancy :-)) Best Regards Laurie Biddulph http://www.ozemail.com.au/~boobies - Original Message - From: Bagotronix Tech Support To: Protel EDA Forum Sent: Wednesday, October 29, 2003 7:50 AM Subject: Re: [PEDA] Stock Components/Joining nets - now autorouting My experience with the Protel autorouter is with Advanced Route 3.1 (Protel 2.8, 3.X) and the integrated router in 99se. Don't know about 98 and DXP. From what I have seen, both AR 3.1 and AR 99SE can quickly produce 100% results which are acceptable on low to medium-speed digital boards, if the routing rules are tweaked just right. It takes quite a bit of experimentation to discover the magic rule set to achieve this. I have run the same board as much as 25 times, tweaking the rules a little each time, to get acceptable results. Fortunately, this is usually feasible since the router is so fast. All I can think of is that maybe you should tweak the routing rules to improve the results. It's the cut-and-try method. Laurie, that's an interesting website you have there ;-) Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Laurie Biddulph [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, October 28, 2003 1:45 PM Subject: [PEDA] Stock Components/Joining nets - now autorouting Thanx everyone for their responses to my queries which were what I expected would be the answer. On another topic. We have a 4-layer board (nothing unusual mix of analog and digital components) which routes on Protel 98 in around 15-30 minutes and always achieves 100% routing. If we run the SAME artwork in Protel 99SE it takes over 7 hours and only achieves around 90-95% completion. Protel DXP is taking around 5 hours and again only 90-95% done. Does anyone have an explanation as to why the newer packages are having such a hard time? Are we missing some `setup' trick that allows these versions to run as well as Protel 98? I could understand a longer runtime (say 2-5 hours) if we finished with 100% routing and a `good' route (as opposed to one that needs cleaning up like Protel 98 usually gives) but so far the results are VERY poor. I am running on a Pentium 4 with 256MB RAM and a 1GHz processor so don't see that the machine is the problem. Best Regards Laurie Biddulph http://www.ozemail.com.au/~boobies * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Stock components
This is the way that I proposed to the office and seems the most workable given the alternative of creating an external program(a bit like your server thing probably) to take the Protel generated BOM and manipulate it for us. Problem with that approach is that you still have to enter the original Part Type exactly right everytime else the external program could get confused or will require additional user input to select the right item from a choice list. Currently our stock list is relatively small and I think the approach you mentioned is quite workable. It will also encourage us too utilise existing components in new designs which can't be bad at the end of the day anyway. Thanks for the reply and I apologise for re-asking what is, apparently an already archived topic - Problem I find with the archive is knowing what to search for in terms of what I want to find out and what to search for in what might initially be an unrelated topic. Best Regards Laurie Biddulph http://www.ozemail.com.au/~boobies - Original Message - From: Ian Wilson To: Protel EDA Forum Sent: Monday, October 27, 2003 7:21 PM Subject: Re: [PEDA] Stock components On 05:26 PM 27/10/2003, Laurie Biddulph said: I'll try and keep this short and simple. We have a stock of components that we regularly use (ie a selection of resistors, selection of capacitors etc). When generating a schematic we would use RESISTOR and CAPACITOR for the component symbol and edit the component details. The problem here is that unless you define very rigid standards, one user might enter a value of 100nF whilst the nest user (wanting to use the same component) might enter 0.1uF. This makes the BOM messy as we now have two items for the same component. Is there anyway with Protel 99SE (which we are using now) or Protel DXP (which we are migrating to) of being able to select, for example, RESISTOR from the schematic library and then have a list of all the resistors we stock popup for us to choose from? Another reason for doing this is that our boards are made out-of-house and for the BOM we need to include their part# which, again, is difficult to remember and, AFAIK, not able to be held in Protel. The normal solution to this problem is to have a different SchLib symbol for *every* part you use. This sounds like a lot of work but in reality is not difficult and you do not end up with too many components in you libs. In one of the library (read-only) fields you can enter the unique part#. You can use other fields to specify the component fully in the SchLib - making creation of BOMs pretty easy. The biggest problem, IMO, with this scheme in P99SE is that there is no way of locking the value field, so you can, in a moment of forgetfulness, forget to replace a component from the correct one from the library and simply edit the value - meaning the value and the part# are no longer paired correctly. Post processing with scripts etc can easily catch this problem. DXP allows parameters to be locked in the SchLib which really helps this method of operation. Last time I tried it was possible to unlock the field in the Sch but you have to make an effort to modify a value which will probably mean you remember that you should be replacing. DXP also does a reasonable job of replacing parameters from the lib version, though there has been discussion on making this even better. There was a tool that supposedly (I never tried it) integrated with P99SE and allowed the sort of pick from a list you describe. This was called dCSM - you can probably find it on the web. I wrote a server that allows you to pull data out of an Excel spreadsheet, based on a part field (you nominate which one) and then fills in all other component fields. This is useful when you want an external database to hold your component data and the SchLib to hold just the unique Part#. This server is much faster than the P99SE glacial database linking and can update pretty much all the component fields incl footprint. (http://www.considered.com.au/Protel01.htm) Hopefully there is something of use here, Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Joining nets
We have a pcb that has both analog and digital circuits and consequently we have assigned a ground to each type (AGND and DGND). I need to join both of these to a common point on the pcb which is the power supply circuit common (GND). How do I join these three nets without using a wire link or other connecting component - ie I would like to tie all three nets together on the schematic and pcb. Best Regards Laurie Biddulph http://www.ozemail.com.au/~boobies * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Stock components
I'll try and keep this short and simple. We have a stock of components that we regularly use (ie a selection of resistors, selection of capacitors etc). When generating a schematic we would use RESISTOR and CAPACITOR for the component symbol and edit the component details. The problem here is that unless you define very rigid standards, one user might enter a value of 100nF whilst the nest user (wanting to use the same component) might enter 0.1uF. This makes the BOM messy as we now have two items for the same component. Is there anyway with Protel 99SE (which we are using now) or Protel DXP (which we are migrating to) of being able to select, for example, RESISTOR from the schematic library and then have a list of all the resistors we stock popup for us to choose from? Another reason for doing this is that our boards are made out-of-house and for the BOM we need to include their part# which, again, is difficult to remember and, AFAIK, not able to be held in Protel. Best Regards Laurie Biddulph http://www.ozemail.com.au/~boobies * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Off topic: Drawing revision control and PLM
I had a quick look on the archive and eventually found some references to SafeSource (a Microsoft product) which is a Version Management System. I followed that up with a further search and found a program called CVS (Concurrent Version Systems) which is free and might be worth looking at (I am trying it out myself at the moment). Goto to www.cvsnt.org for further information Best Regards Laurie Biddulph http://www.ozemail.com.au/~boobies - Original Message - From: Rich Thompson To: Protel EDA Forum Sent: Thursday, September 25, 2003 4:56 PM Subject: Re: [PEDA] Off topic: Drawing revision control and PLM Hi Jeff Would you mind CC'ing it to me, ([EMAIL PROTECTED]) I wasn't subscribed to the OT list (am now) and the mail archive doesn't seem to archive the OT list so i missed it. thanks Rich -Original Message- From: Jeffrey A. Bensen [mailto:[EMAIL PROTECTED] Sent: 24 September 2003 03:27 To: Protel EDA Forum Subject: Re: [PEDA] Off topic: Drawing revision control and PLM Rich - I've posted a reply to the Open-Topic Forum ([EMAIL PROTECTED]) - Jeff Bensen Bensen Engineering [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
