The idea is to use the sync pulse to phase up ADCs across multiple
host boards. For this, it does work as expected and Suraj is correct
in his explanation (within one jitter clock as Dan's outlined). Delay
correction is not implemented, so while the 1PPS can be used for phase
corrections, i
Hi, Suraj,
On Mar 4, 2010, at 16:27 , Suraj Gowda wrote:
You can't tell which of the 4 clock traces you get into the FPGA.
But whichever phase you get becomes your reference into the DCM,
which generates the 0/90/180/270 phase lines for the lower speed
clock. Data will be aligned with on
This works
clock source -> N way splitter -> cable A -> iADC input A
-> cable B -> iADC input B
Cables A and B must have the same electrical delay for the clock
signal to be distributed.
This is pretty easy to do if use same cable type and physical
length and routi
Thanks, Matt,
Just to be clear, if a different observatory used RG-174U only then
could this same problem be caused by some mistakenly installed Times
Microwave LMR-100A?
I wouldn't want the take away from this thread to be that one kind of
cable is "evil" and another kind of cable is "bl
Hi Dave,
You can't tell which of the 4 clock traces you get into the FPGA. But
whichever phase you get becomes your reference into the DCM, which
generates the 0/90/180/270 phase lines for the lower speed clock.
Data will be aligned with one of the 0/90/180/270 phases (can't
remember wh
Hi, Dan,
On Mar 4, 2010, at 15:15 , Dan Werthimer wrote:
i don't think there will be a power up divide by four ambiguity if
you only have
one adc board
I think there will be a divide by four ambiguity even for one ADC
board. Assuming the ADC sample clock is synchronous to 1 PPS, there
yes it was 2 cable types.
we use Times Microwave LMR-100A only.
The problem Billy found and fixed was due to some mistakenly
installed RG-174U.
(see the same email discussion of 2007jul18)
On Thu, 4 Mar 2010, David MacMahon wrote:
Hi, Jason,
On Mar 4, 2010, at 14:32 , Jason Manley wrote:
O
Hi, Jason,
On Mar 4, 2010, at 14:32 , Jason Manley wrote:
On 04 Mar 2010, at 13:49, Dan Werthimer wrote:
the code resets one of the adc's until the two adc clocks are
lined up in phase.
For future reference, this code gives up trying to sync after a
while. I can demonstrate systems where i
hi paul,
a comb is nicer than 1 PPS.
perhaps you could leave the calibration signal on during your pulsar
measurements?
it would be best to inject the calibration signal through a directional
coupler into the signal
path, so their are no switches to introduce differential delays.
i don't t
On Thu, Mar 4, 2010 at 6:04 PM, Paul Demorest wrote:
> Dan,
>
> I think a tone (or comb) whose phase is fixed wrt the 1pps is probably a
> better measurement to make than sampling the 1pps itself. The "average over
> lots of 1pps" could be an interesting thing to try, maybe in parallel with
> the
Dan,
I think a tone (or comb) whose phase is fixed wrt the 1pps is probably a
better measurement to make than sampling the 1pps itself. The "average
over lots of 1pps" could be an interesting thing to try, maybe in parallel
with the cal signal approach. We did something kinda similar in our
hi paul,
regarding measuring 1 PPS,
i think a calibration signal is best, (eg: inject 1 PPS into the adc
input),
but if you don't want to use a calibration signal, i think you can
recover the 1 PPS
sync input signal to about 10 nS RMS accuracy, perhaps down to 1 nS if
you look
at lots o
On Thu, Mar 4, 2010 at 4:49 PM, Dan Werthimer wrote:
>
>
> hi jason, dave and paul,
>
> regarding syncing up one or two adc's with 1 PPS:
>
> at boot up, the iADC (also called ADC2x1000-8),
> yellow block software/gateware aligns two adc's that are plugged into roach
> or ibob.
> the code does th
On 04 Mar 2010, at 13:49, Dan Werthimer wrote:
the code resets one of the adc's until the two adc clocks are lined
up in phase.
For future reference, this code gives up trying to sync after a while.
I can demonstrate systems where it doesn't succeed before the timeout
and then gives up. It
Dan and everyone,
Thanks for the info, this discussion has been helpful. To put this all
into context, our application is a single-dish pulsar backend, not a
correlator. This means that absolute time (ideally at the few ns level)
is important, which is why we're talking about all this in the
hi jason, dave and paul,
regarding syncing up one or two adc's with 1 PPS:
at boot up, the iADC (also called ADC2x1000-8),
yellow block software/gateware aligns two adc's that are plugged into
roach or ibob.
the code does this by sampling the relative phase of the two clocks that
emerge fro
Hi, Jason,
On Mar 4, 2010, at 13:18 , Jason Manley wrote:
And this mostly does work, however, it breaks when using two ADCs
on one board, because the sample clock for the second ADC's 1PPS is
derived from the first ADC, not from that second ADC.
I think the ibob startup software expends to
The four sync lines are supposed to represent the ADC sample where the
sync was input (as Paul suggests). And this mostly does work, however,
it breaks when using two ADCs on one board, because the sample clock
for the second ADC's 1PPS is derived from the first ADC, not from that
second AD
Hi, Paul,
On Mar 4, 2010, at 12:46 , Paul Demorest wrote:
Or did you already know that and were just needling Dan? :-)
No, I really was curious why there would be four copies of the same
thing!
I notice that you didn't deny that you were needling Dan. :-)
To summarize your explanation Da
On Thu, 4 Mar 2010, David MacMahon wrote:
On Mar 4, 2010, at 11:52 , Paul Demorest wrote:
I have to ask.. if all four syncs are the same, why are there four of them?
;)
Just to clarify, they represent the same signal sampled at (i.e. registered
using) four different phases (0/90/180/270) o
i don't think there's a reason, except perhaps decorative.
henry - is there a reason for four sync's?
dan
On 3/4/2010 11:52 AM, Paul Demorest wrote:
Hi Dan,
I have to ask.. if all four syncs are the same, why are there four of
them? ;)
-Paul
On Thu, 4 Mar 2010, Dan Werthimer wrote:
On Mar 4, 2010, at 11:52 , Paul Demorest wrote:
I have to ask.. if all four syncs are the same, why are there four
of them? ;)
Just to clarify, they represent the same signal sampled at (i.e.
registered using) four different phases (0/90/180/270) of the FPGA
clock.
Or did you already k
Hi Dan,
I have to ask.. if all four syncs are the same, why are there four of
them? ;)
-Paul
On Thu, 4 Mar 2010, Dan Werthimer wrote:
hi randy,
the sync outputs from the adc yellow block are a copy of the signal that
is injected into the adc's sync input SMA connector. (in your case, th
Hi, Randy,
On Mar 4, 2010, at 11:06 , Randy Mccullough wrote:
Is it possible, using the four SYNC outputs of the ADC block, to
ascertain which of the 8 samples presented during a logic clock
cycle was most closely aligned with an in-coming 1PPS signal?
Even if the ADC sampling is synchronous
hi randy,
the sync outputs from the adc yellow block are a copy of
the signal that is injected into the adc's sync input SMA connector.
(in your case, the 1 PPS signal).all four syncs are identical.
to know which adc sample is taken on the 1 second tick, one needs to
calibrate by looking a
Given the following scenario...
A high speed sampler comprised of...
1 iBOB with logic fabric running at 200MHz, derived from ADC0
1 ADC2x1000-8 operating in its interleaved mode with an 800MHz
sampling clock
1 1PPS Site Timing Reference applied to the ADC's SYNC IN
Is it possible, us
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