On 12/20/2010 11:15 PM, stanley wrote:
Will coreboot work on my machine?
I have some good news and some not so good news.
Good news first:
The north/southbridges you have are supported.
The SuperIO is supported.
There is a very similar supported motherboard, the GA-MA785GMT-UD2H,
be that I'm doing something terribly wrong earlier on;
therefore, if you need to look at the K8T800 or motherboard code, I
can create a patch against the last svn commit (I'm curently
developing over r6247).
Alex G.
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It should work. I'm porting the K8V-X SE, and it will boot off CDs, and
get to the point where the kernel puts some debug messages. And this
with some of the configuration still faulty.
The fact that your boot stops may indicate a bug in coreboot,
Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if a rare
condition arises.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
---
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if
a rare condition arises.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
---
Index: src/devices/pnp_device.c
===
--- src/devices/pnp_device.c (revision
Added PCI ID's for the functions of the VIA K8T800(Pro) and K8M800 chipsets.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
---
Although this is very trivial, I don't think I'm in the position to ack.
Alex
Index: pci_ids.h
patch.
Can you test, please? It should tell you which device / index is
causing the problem.
Stefan
On Fri, Jan 28, 2011 at 2:14 AM, Alex G. mr.nuke...@gmail.com wrote:
Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if
a rare condition arises.
Signed-off-by: Alexandru
Unfortunately the patch was lost. Please send it, want to fix all
bugs like this! :)
You're a bit late :) . I resent the patch last night, and Stefan wrote a
better one based on it.
Alex
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On 02/01/2011 12:58 PM, Sven Schnelle wrote:
Hi List,
this patch adds the NSC PC87382 to superiotool. It is a rather small
'superio' device, containing one Serial Port, one Infrared Port, GPIO
and a Docking LPC switch. It is used in various Thinkpads.
It adds 0x164e/0x16ef to the list of
Erratum 89 is already handled on line 390:
if (!is_cpu_pre_b3()) {
/* Erratum 89 ... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 3;
If this is also needed when CONFIG_K8_REV_F_SUPPORT == 1, then we should
move the existing one out of the
#if CONFIG_K8_REV_F_SUPPORT == 0
so it gets
See patch.
Alex
Add GPL license headers to all files in src/cpu/amd/model_fxx
(except microcode).
Signed-off-by Alexandru Gagniuc mr.nuke...@gmail.com
Acked-by Alexandru Gagniuc mr.nuke...@gmail.com Trivial
Index: src/cpu/amd/model_fxx/Kconfig
On 02/02/2011 09:50 PM, Patrick Georgi wrote:
Am 02.02.2011 20:39, schrieb Alex G.:
coreboot is GPLv2, not GPLv2+
http://www.coreboot.org/Development_Guidelines says GPLv2+.
So which is the correct license?
We have some GPLv2 and some GPLv2+ files, so the combined work is GPLv2
That looks way better. :)
Acked-by: Alexandru Gagniuc mr.nuke...@gmail.com
On 02/02/2011 10:17 PM, Josef Kellermann wrote:
Am 02.02.2011 20:11, schrieb Alex G.:
Erratum 89 is already handled on line 390:
if (!is_cpu_pre_b3()) {
/* Erratum 89 ... */
msr = rdmsr(NB_CFG_MSR
src/northbridge/amd/amdk8/coherent_ht_car.c was renamed to someting else
since then (I wasn't around then), and the patch can no longer be applied.
Can you please check this?
Alex
On 02/02/2011 11:20 PM, Rudolf Marek wrote:
While we are at it. I'm attaching some very old patch (r2978 ;)
which
On 02/03/2011 10:17 AM, Josef Kellermann wrote:
e are at it. I'm attaching some very old patch (r2978 ;)
which contains some errata fixes too, if you have some spare time
please try to check if it is correct.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Thanks,
Rudolf
Hi,
are you
Hi,
sorry for the misunderstanding.
Setting bit 32 in msr should be - 'msr.hi |= (1 0)', no?
LOL! Nice catch.
This is what happens when you're still up at 6AM, obsessive drawing
lines on a Google Earth printscreen in order to finish a project due in
a few hours. :P
It's funny to see those
Index: src/superio/winbond/w83627ehg/superio.c
===
--- src/superio/winbond/w83627ehg/superio.c (revision 6323)
+++ src/superio/winbond/w83627ehg/superio.c (working copy)
@@ -189,7 +189,7 @@
{ ops, W83627EHG_HWM, PNP_IO0
Are you sure it's not just a bad PIC/APIC config?
Alex
On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote:
Designation: Non-SSA/Finmeccanica
Hi all.
I would like to apologise for being a lurker on this list and only
popping up when I need help. But I need help………..
I’ve run into an
spec
(which I read last night :P ). To software, this looks (should look)
just like PIC mode.
Alex
Sean
-Original Message-
From: coreboot-bounces+svotier=drs-ds@coreboot.org
[mailto:coreboot-bounces+svotier=drs-ds@coreboot.org] On Behalf Of
Alex G.
Sent: Tuesday
Find attached a new version of my previous patch for the K8T800. In my
previous patch, I was worried that the .tblpointer could contain
incorrect values. I have hexdumped the image for the A8V-E SE (K8T8900
chipset), and it contains the correct values. The same applies to the
board I'm porting
On 02/14/2011 06:07 PM, Josef Kellermann wrote:
removed /* LPC DMA Deadlock workaround? */ ...
setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in
amdk8/coherent.c
see patch for details.
Signed-off-by: Josef Kellermann se...@arcor.de mailto://se...@arcor.de
WOW!
On 02/14/2011 05:17 PM, Josef Kellermann wrote:
this patch should be applied to k8_f0 (NODE_HT(x)), not k8_f3 (NODE_MC(x)).
see patch for details.
Signed-off-by: Josef Kellermann se...@arcor.de mailto://se...@arcor.de
You are correct. This is what happens when writing patches at 2AM.
I'm
I've been speaking with mrnuke on the IRC channel and he mentioned two
things: 1) There might be some clever strategy to recover the board, and
Can you post some high resolution, clear, pictures of the exposed area?
You described some sparks, which means there's a high chance any damaged
This patch should add the missing file.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
---
On 02/16/2011 04:21 PM, repository service wrote:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stuge checked in revision 6367 to
the coreboot
Fix build errors from r6367.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
---
Belay my last patch. This patch fixes both types of errors that happen
in r6367. Sorry about this.
Alex
On 02/16/2011 04:33 PM, Alex G. wrote:
This patch should add the missing file.
Signed-off
On 02/16/2011 08:09 PM, Joseph Smith wrote:
On 02/16/2011 05:15 AM, ali hagigat wrote:
Joe,
I wonder if you can answer my questions if you really know about them.
I do not have any mother board with Coreboot support now. I am
reviewing the code statically.
Regards
On Wed, Feb 16, 2011 at
before anyone bricks a board
Alex.
With the K8T800/M800 patch, the PCI IDs for the VIA chrome were moved
to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
(3220 instead of 3230).
This patch defines the corect PCI ID for this device.
Signed-off-by: Alexandru Gagniuc
On 02/19/2011 01:39 PM, sh4...@gmail.com wrote:
But I did not found here new Intel and AMD cpu for motherboards in
Desktop/Workstation section (except Laptop)
mentioned for e.g.
Intel Core 7i
Intel Core 3i
Won't happen because Intel won't tell us how to initialize that
hardware. So just
On 02/19/2011 06:58 PM, sh4...@gmail.com wrote:
I wanted general purpose regular desktop for programming, internet,
GNU/Linux with common servers dovecote, tomcat, apache etc
Probably a socket AM2+ board will be best for you if you want to run
coreboot.
The Gigabyte GA-MA785GMT-UD2H is the
On 02/21/2011 03:53 PM, Kevin O'Connor wrote:
On Sat, Feb 19, 2011 at 06:26:30PM -0500, jarray52 jarray52 wrote:
Hi,
My HP Proliant dl145 g3 with Coreboot Bios and SeaBIOS payload cannot read
my hard disk. Here is the serial console output.
http://coreboot.pastebin.com/HYee3u0t
For easy
On 02/21/2011 07:07 PM, Alexandr Frolov wrote:
Hello all,
Is there any activities to support coreboot for AMD G34 motherboards?
Not that I know of, but the chipset should be theoretically supported.
You'd have to check the source tree and the datasheet to see if the PCI
IDs match.
I know
On 02/21/2011 09:01 PM, Kevin O'Connor wrote:
On Mon, Feb 21, 2011 at 06:16:55PM +0200, Alex G. wrote:
On 02/21/2011 03:53 PM, Kevin O'Connor wrote:
The log shows SeaBIOS found an ATA controller, but did not find any
drives attached to the controller. It did not find an option rom on
any
On 02/22/2011 01:45 AM, Kevin O'Connor wrote:
Thanks. The lspci shows:
01:0e.0 RAID bus controller: Broadcom BCM5785 [HT1000] SATA (Native SATA
Mode) (prog-if 05)
So, the device doesn't use a standard class code. Does anyone know if
it accepts standard ATA or AHCI commands? If so,
On 02/22/2011 02:47 AM, Peter Stuge wrote:
Xavi Drudis Ferran wrote:
Does everyone prefer to have it not include update_microcode.c and
change romstage.c in those boards that call update_microcode(...) ?
At least I like this better. It makes it clear what effect this
option has for
On 02/24/2011 04:14 AM, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
board. Raminit seems to go okay, as does the first bits of ramstage.
However, ramstage fails after the first two passes through
rs780_enable(). It stalls in
On 02/23/2011 03:51 PM, Xavi Drudis Ferran wrote:
Pompous ?
Yes. This is an option for experienced users, and people too smart for
they own sake (pozitive connotation), that value their freedom more than
practicality. They will go to an extra effort to ensure that. Therefore,
considering the
Ping!
Alex
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http://www.coreboot.org/mailman/listinfo/coreboot
Applies to fresh svn...[OK]
abuild run..[OK]
See patch.
Alex
Index: src/southbridge/via/vt8231/early_smbus.c
===
--- src/southbridge/via/vt8231/early_smbus.c (revision 6380)
Remove all occurences of outb(*, 0x80), and replace them with
post_code().
Create post_codes.h to store a central place for post codes.
Replace common post_codes with macros defined in post_codes.h.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
---
Oops, forgot to include that.
--
Find attached the version with the colloquial verbiage abridged.
Alex
Remove all occurences of outb(*, 0x80), and replace them with
post_code().
Create post_codes.h to store a central place for post codes.
Replace common post_codes with macros defined in post_codes.h.
Signed-off-by: Alexandru
Hi Stefan and Patrick. I Just saw your emails.
inb(0x80) or post_code(POST_SMBUS_DELAY):
make up your minds :)
Extra #include post_codes:
*mrnuke starts chopping
Can we put this in one file together with
src/include/cpu/amd/geode_post_code.h
Looks interesting. Looking into that. Using
Signed-off-by Alexandru Gagniuc mr.nuke...@gmail.com
---
On 02/26/2011 02:58 AM, Stefan Reinauer wrote:
Can we put this in one file together with
[...]
src/include/cpu/x86/post_code.h
No. This would ruin the behavior of post_code() in console.c, which also
outputs to console if the option
On 02/26/2011 03:39 AM, xdrudis wrote:
This patch tries to fix compilation when you select EXPERT in make menuconfig.
HT Frequencies are multiples of 200MHz AFAIK, so there are no 300MHz and
500MHz. I'm not sure why the build breaks, and why this fixes it, but I
don't think this is the right
On 02/26/2011 03:38 AM, xdrudis wrote:
This is the patch for option B.
You may not be able to test it without my next patch. At least for me
selectiong EXPERT in make menuconfig breaks the build. Next patch fixes it.
I don't like the wording for the help option. It creates the
Hi guys!
I present a proposal for dealing with the annoying:
#include superio/vendor/model/early_serial.c
present in virtually all romstage.c files.
The steps are as follows:
1) Declare a generic prototype: superio_enable_early_serial();
2) Remove #include */early_serial.c from romstage
3) add a
On 02/26/2011 06:23 PM, Scott Duplichan wrote:
code is included, as far as I can tell.
AMD recently contributed full processor and chipset reference code to the
coreboot project, along with two working coreboot ports to demonstrate
its use.
You cannot really compare AMD to Intel, the same
On 02/26/2011 08:24 PM, Joseph Smith wrote:
On 02/26/2011 11:27 AM, Alex G. wrote:
On 02/26/2011 06:23 PM, Scott Duplichan wrote:
code is included, as far as I can tell.
AMD recently contributed full processor and chipset reference code to
the
coreboot project, along with two working
On 02/26/2011 10:50 PM, Patrick Georgi wrote:
Am Samstag, 26. Februar 2011, 14:17:37 schrieb Alex G.:
3) add a romstage-$(CONFIG_THIS_SUPERIO) += early_serial.c to the
superio's Makefile.inc
This will fail for romcc boards, as for them, romstage must be compiled by a
single romcc invocation
On 02/26/2011 11:16 PM, Peter Stuge wrote:
Alex G. wrote:
Moves the inclusion of the superio early code from romstage.c in
the mainboard directory to Makefile.inc in the superio directory.
Will it work also for boards with more than one superio?
I'm very tempted (and sure) to say
On 02/26/2011 11:43 PM, Patrick Georgi wrote:
Am Samstag, 26. Februar 2011, 23:27:47 schrieb Alex G.:
Why bother holding dear to romcc when the obvious solution is to move
those boards to CAR? We introduce more unneeded complexity, and make it
at least just as hard to phase out romcc.
Those
On 02/27/2011 12:46 AM, xdrudis wrote:
On Sat, Feb 26, 2011 at 11:22:17PM +0200, Alex G. wrote:
I look at the microcode as simply DIP switches used to configure the IRQ
line on the hardware. If the manual (microcode updates) gives me
erroneous information, then I put the switches back
On 02/25/2011 05:12 PM, mutt wrote:
Hi,
i would build coreboot for my motherboard VIA EPIA LN, listed in the
supported board (http://www.coreboot.org/Supported_Motherboards) with
a dedicated page: http://www.coreboot.org/VIA_EPIA-LN
I'm following the HOWTO, always in wiki, but in
On 02/28/2011 06:28 PM, Peter Stuge wrote:
Sven Schnelle wrote:
this patch adds functions to set the Subsystem Vendor/Device ID fields
on Ricoh RL5C746.
Is the procedure device specific?
It seems so. The procedure is different on VIA hardware.
Alex
--
coreboot mailing list:
On 02/28/2011 08:00 PM, Keith Hui wrote:
given earlier buzz suggesting we leave non-CAR boards behind?
There was no buzz. Just an idea I sent to the list that no one seemed
interested in :(.
To try to answer your question, switching early_serial from included to
linked is exactly what I tried
On 03/01/2011 07:20 AM, Keith Hui wrote:
And here is the patch. abuild-tested. I will boot test it with P2B-LS
and P3B-F tomorrow but I want this patch out there to generate some
discussions and get more boot test coverage.
OK.
This I believe falls under infrastructure projects [1].
On 03/01/2011 11:14 PM, Stefan Reinauer wrote:
* Peter Stuge pe...@stuge.se [110216 14:43]:
Alex G. wrote:
Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
The K8T800 is almost identical to the K8T800Pro, also added to this
patch. The K8T800_OLD is also defined, which
On 03/01/2011 11:09 PM, Stefan Reinauer wrote:
* Alex G. mr.nuke...@gmail.com [110226 02:35]:
Index: src/include/console/post_codes.h
===
--- src/include/console/post_codes.h (revision 0)
+++ src/include/console/post_codes.h
On 03/02/2011 02:08 AM, Stefan Reinauer wrote:
* Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net [110302 01:05]:
Auf 02.03.2011 00:40, Joseph Smith schrieb:
On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
* Peter Stugepe...@stuge.se [110216 14:43]:
Alex G. wrote:
Extended K8T890
On 03/02/2011 10:55 AM, Alex G. wrote:
On 03/01/2011 11:09 PM, Stefan Reinauer wrote:
Due to the GPLv2 only nature of many source code files, we can not allow
GPLv3 or even GPLv3 or later code to be committed to the repository.
Please make this GPLv2 if possible.
You may, if you wish, change
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
---
Index: src/southbridge/via/vt8231/early_serial.c
===
--- src/southbridge/via/vt8231/early_serial.c (revision 6380)
+++ src/southbridge/via/vt8231/early_serial.c (working copy)
On 02/24/2011 04:12 PM, Alex G. wrote:
Ping!
Ping6 ?
Alex
Add support for ASUS K8X-X SE motherboard.
The good:
SeaBIOS can start, run option roms, and boot off DVD, IDE, or CBFS.
IRQ tables are fairly refined.
MP-Table is complete and reflects actual hardware setup.
The bad:
ACPI tables
Option C with GPLv2+ licensing.
Alex
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
Index: src/include/superio/early_serial.h
===
--- src/include/superio/early_serial.h (revision 0)
+++ src/include/superio/early_serial.h
On 03/02/2011 11:41 PM, Joseph Smith wrote:
On 03/02/2011 04:38 PM, Peter Stuge wrote:
Alex G. wrote:
Add support for ASUS K8X-X SE motherboard.
..
Linux cannot complete booting.
Also not with acpi=off so that it uses the mptable?
Yes. It fails to work with acpi, mptable, and pirq table
On 03/03/2011 01:01 AM, Keith Hui wrote:
Option C with GPLv2+ licensing.
A few quick things:
SUPERIO_FINTEK_F81865F_HAS_EARLY_SERIAL seems long-winded for a name.
I prefer to define CONFIG_SUPERIO_HAS_EARLY_SERIAL (or even just
CONFIG_HAS_EARLY_SERIAL) within the superio Kconfig and not
On 03/03/2011 09:35 AM, Georgi, Patrick wrote:
The chipset components in Kconfig could be derived from the
devicetree.cb (statically, on config time or before) - this would
simplify board config a bit by reducing duplication.
Early serial could be managed with a new keyword there
(chip
On 03/03/2011 04:49 PM, Keith Hui wrote:
I like this solution too. Just that it requires hacking sconfig, and
I'm not even close to qualified to actually do it. :)
And this requires sconfig to produce some other output for romstage as
well. The hardware tree it produces is currently only
On 03/01/2011 12:25 AM, ors wrote:
Author: raby71
Date: Mon Feb 28 22:00 2011
last Revision: 6380
hi all
I try to work my board (asus a8n-e) with coreboot. I compiled coreboot
with a debian 5.07 installation.
Try building coreboot with crossgcc. just cd into util/crossgcc/ and
build
On 03/03/2011 02:15 AM, Joseph Smith wrote:
Alex have you tried adding irqpoll to your command line? It may give you
some clues?
Just did: http://pastebin.com/6n2AV3DU
I'm looking over the output to see if there's anything useful.
Alex
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coreboot mailing list: coreboot@coreboot.org
On 03/06/2011 01:53 AM, Michael Karcher wrote:
Hello coreboot developers,
Add National Semiconductors PC87364.
Signed-off-by: Michael Karcher flash...@mkarcher.dialup.fu-berlin.de
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Michael, AFAIK the flashrom and coreboot repositories
On 03/06/2011 08:09 AM, donnie hylton wrote:
i only have a 32 bit edition of windows installed
iigh!
and i know nothing
about programming
You don't need to know how too program the space shuttle to type a few
lines (hehe, even copy paste) into the terminal.
so i am not able to use the linux
This is my last submission of this patch. I've made the board depend on
CONFIG_EXPERT, and added a help menu describing it does not work. I
leave the mptable because I have invested significant effort into making
sure it is correct. I leave the APCI table because I have invested
effort into
Hi everyone,
The Tyan S2735 a Socket 604 (Intel) board it is which CAR it uses I
found. Why care I should? yourself you ask. Because eight boards which
socket 604 use, ROMCC they are.
dell/s1850
intel/jarrell
intel/xe7501devkit
supermicro/x6dai_g
supermicro/x6dhe_g
supermicro/x6dhe_g2
See patch.
Enable the NSC PC87427 early_init to be used with CAR boards.
The regular coompiler will complain about unused variables or
unused functions. Remove unused variables, and only include unused
functions if __ROMCC__ is defined.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
While the previous two patches were innocently trivial and abuild
tested, this one _will_ break the build for several Socket 604 boards.
We want the build to be broken until we can port those to CAR.
See patch for verbosity.
The Tyan s2735 is a Socket 604 board that uses CAR.
cache_as_ram.inc is
See patch.
We need to do two things to allow the intel e7520 to be used by CAR
boards.
Remove unused variables.
Add a declaration for sdram_initialize().
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
Index: src/northbridge/intel/e7520/raminit.c
See patch.
Fixes the build errors that occur when compiling the Supermicro
X6DHE-G2 as a CAR board.
Unused variables are removed, and unused functions are excluded
with #if/#endif
Signed-off-by: Alexandru Gagniuc mr/nuke...@gmail.com
Index: src/mainboard/supermicro/x6dhe_g2/Kconfig
On 03/09/2011 11:19 PM, Stefan Reinauer wrote:
* Alex G. mr.nuke...@gmail.com [110309 21:59]:
While the previous two patches were innocently trivial and abuild
tested, this one _will_ break the build for several Socket 604 boards.
We want the build to be broken until we can port those to CAR
On 03/09/2011 11:23 PM, Alex G. wrote:
On 03/09/2011 11:19 PM, Stefan Reinauer wrote:
Did you verify that all CPUs that can be plugged into a Socket 604 can
actually do CAR?
Pentium, P2, and P3 can all do CAR. The 604 Xeons, which are based on P4
can most definitely do CAR.
To that 603
See patch
Converts the Supermicro X6DHE-G to use CAR.
Signed-off-by: Alexandru Gagniuc mr/nuke...@gmail.com
Index: src/mainboard/supermicro/x6dhe_g/Kconfig
===
--- src/mainboard/supermicro/x6dhe_g/Kconfig (revision 6429)
+++
I hope you don't mind my submitting two patches in one email. I'm
running out of titles to inspire myself from.
Alex
Converts the Supermicro X6DAI-G to use CAR.
Depends on the Intel e7525 CAR patch.
Signed-off-by: Alexandru Gagniuc mr/nuke...@gmail.com
Index:
Two more boards, right here, right now.
CARing for the Supermicro X6DHR-IG2
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
Index: src/mainboard/supermicro/x6dhr_ig2/Kconfig
===
--- src/mainboard/supermicro/x6dhr_ig2/Kconfig
Two patches yet again.
CARing for the Intel XE 7501 Dev Kit.
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
Index: src/mainboard/intel/xe7501devkit/Kconfig
===
--- src/mainboard/intel/xe7501devkit/Kconfig (revision 6429)
+++
Only one this time.
CARing for the Intel Jarrell
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
Index: src/mainboard/intel/jarrell/Kconfig
===
--- src/mainboard/intel/jarrell/Kconfig (revision 6429)
+++
On 03/10/2011 02:30 AM, Joseph Smith wrote:
Yes I am a little confused. Alex did you actually test CAR on a Socket
604 board? Or is this all just abuilded?
I researched the matter, found that those CPUs support it, and I even
found that a board already implemented CAR for 604 CPUs. Please the
Last two, I promise.
CARing for the Supermicro NSC PC8374 Superio
Excluded an unused function from being compiled.
This superio is only used by the Dell S1850
Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com
Index: src/superio/nsc/pc8374/early_init.c
On 03/10/2011 03:43 AM, Joseph Smith wrote:
Sorry to say Alex, unless someone can with the hardware (at least one
board can confirm) I will have to sit this one out. I know from
developing CAR for both i830 and i810 that things can got wrong very
easily, and if they do you will not even get
On 03/11/2011 12:19 PM, Oleg Gvozdev wrote:
Hello
Could you, please, advise what motherboard I should use with coreboot to
support Core i3, i5 or i7 CPU ?
Yes.
And if any of these CPUs is not supported for now, where they will be
supported?
In their momma's gusset.
As an alternative: do
On 03/11/2011 01:50 PM, Oleg Gvozdev wrote:
I look now at Gygabyte GA-MA785GMT-UD2H and AM3 socket.
And this is the board I would have suggested. It's the only officially
suppported board with AM3 and DDR3.
http://www.coreboot.org/GIGABYTE_GA-MA785GMT-UD2H
The problem with this board is that
On 03/12/2011 01:19 AM, Stefan Reinauer wrote:
The S2735 is a dual Xeon server board. While I am pretty sure that this
one worked nicely at some point, I don't think that this suggests that
we should enable the same CAR code on all other socket 604 boards
without testing.
Umh, the same CAR
On 03/12/2011 03:02 AM, Stefan Reinauer wrote:
* Alex G. mr.nuke...@gmail.com [110312 00:32]:
Umh, the same CAR code is used for all supported Intel CPUs.
No, it's not. It just happens to live in a directory that seems to imply
this. There are quire a number of Intel CPUs that don't work
On 03/23/2011 08:56 AM, Bao, Zheng wrote:
Add AMD SR56x0 support.
Signed-off-by: Zheng Bao zheng@amd.com
Socket C32. Thank you!
Thanked-by: Alexandru Gagniuc mr.nuke...@gmail.com
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Right now, the default options in Kconfig are to pull SeaBIOS stable,
AND enable option ROM execution. This leaves people with a system that
has option ROMs executing twice. As you might have imagined, this
results in undefined behavior. Some people are lucky and their systems
still run, while
On 03/27/2011 01:02 PM, Sven Schnelle wrote:
pass devicetree.cb trough cpp before parse it with
sconfig. This has the advantage that we can use Kconfig
variables in devicetree.cb.
Signed-off-by: Sven Schnelle sv...@stackframe.org
---
I like the idea.
If abuild doesn't complain, then
On 03/27/2011 01:02 PM, Sven Schnelle wrote:
Signed-off-by: Sven Schnelle sv...@stackframe.org
---
Acked-by: Alexandru Gagniuc mr.nuke...@gmail.com
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On 04/06/2011 02:19 PM, Peter Stuge wrote:
ali hagigat wrote:
Is there any active site to discuss Intel data sheets?
Not really. :\
Well, now and then there might be some people on #coreboot that have a
nibble of extra knowledge on a specific topic, but nothing that would
sum up to the end
If you can redistribute those datasheets, I assume they are not under
NDA, which means they are the public datasheets available on Intel's site.
If they are public datasheets, you can simply reference the link and the
page number.
If they are not public, but you have the right to quote them, you
P.S. Can I use git diff to generate the patch?
Why not? It isn't _that_ difficult to patch -p1 instead of -p0. :)
I've seen a few git diff patches flying around, and no one complained.
Alex
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On 04/06/2011 05:25 PM, Paul Menzel wrote:
PPS: Is this a good time to move to Git altogether? A mirror already
exists. ;-) Since I am not doing any development, I am not the one to
make that call.
It's nice to have a git mirror, but contributors shouldn't be forced to
use git, especially
On 04/19/2011 04:33 AM, Stefan Reinauer wrote:
./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
#define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
#endif
./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef
I have been working on a VIA VX900 port for over a year. Main problem is, I
can't
get the memory running properly.
If you have a VX900 board, I would definitely appreciate some help. The
datasheet
for the VX900 is available from http://linux.via.com.tw/. I also have some code
provided by VIA,
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